1 | (edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0)) |
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2 | (status (written (timeStamp 2009 10 1 13 34 19) |
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3 | (author "Xilinx, Inc.") |
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4 | (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 10.1.03; Cores Update # 3")))) |
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5 | (comment " |
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6 | This file is owned and controlled by Xilinx and must be used |
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7 | solely for design, simulation, implementation and creation of |
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8 | design files limited to Xilinx devices or technologies. Use |
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9 | with non-Xilinx devices or technologies is expressly prohibited |
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10 | and immediately terminates your license. |
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11 | |
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12 | XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS' |
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13 | SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR |
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14 | XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION |
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15 | AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION |
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16 | OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS |
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17 | IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, |
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18 | AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE |
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19 | FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY |
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20 | WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE |
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21 | IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR |
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22 | REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF |
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23 | INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
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24 | FOR A PARTICULAR PURPOSE. |
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25 | |
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26 | Xilinx products are not intended for use in life support |
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27 | appliances, devices, or systems. Use in such applications are |
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28 | expressly prohibited. |
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29 | |
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30 | (c) Copyright 1995-2007 Xilinx, Inc. |
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31 | All rights reserved. |
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32 | |
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33 | ") |
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34 | (comment "Core parameters: ") |
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35 | (comment "c_a_width = 11 ") |
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36 | (comment "c_out_width = 11 ") |
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37 | (comment "c_add_mode = 1 ") |
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38 | (comment "c_has_c_out = 0 ") |
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39 | (comment "c_b_type = 0 ") |
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40 | (comment "c_borrow_low = 1 ") |
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41 | (comment "c_ce_overrides_sclr = 0 ") |
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42 | (comment "c_implementation = 0 ") |
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43 | (comment "c_has_sclr = 0 ") |
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44 | (comment "c_verbosity = 0 ") |
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45 | (comment "c_latency = 0 ") |
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46 | (comment "c_has_bypass = 0 ") |
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47 | (comment "c_ainit_val = 0 ") |
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48 | (comment "c_bypass_low = 1 ") |
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49 | (comment "c_has_ce = 0 ") |
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50 | (comment "c_sclr_overrides_sset = 0 ") |
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51 | (comment "InstanceName = adder_subtracter_virtex4_10_0_80b315fd28a09ef0 ") |
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52 | (comment "c_sinit_val = 0 ") |
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53 | (comment "c_has_sset = 0 ") |
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54 | (comment "c_has_c_in = 0 ") |
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55 | (comment "c_has_sinit = 0 ") |
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56 | (comment "c_b_constant = 0 ") |
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57 | (comment "c_ce_overrides_bypass = 0 ") |
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58 | (comment "c_xdevicefamily = virtex4 ") |
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59 | (comment "c_a_type = 0 ") |
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60 | (comment "c_b_width = 11 ") |
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61 | (comment "c_b_value = 0 ") |
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62 | (external xilinxun (edifLevel 0) |
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63 | (technology (numberDefinition)) |
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64 | (cell VCC (cellType GENERIC) |
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65 | (view view_1 (viewType NETLIST) |
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66 | (interface |
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67 | (port P (direction OUTPUT)) |
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68 | ) |
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69 | ) |
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70 | ) |
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71 | (cell GND (cellType GENERIC) |
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72 | (view view_1 (viewType NETLIST) |
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73 | (interface |
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74 | (port G (direction OUTPUT)) |
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75 | ) |
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76 | ) |
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77 | ) |
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78 | ) |
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79 | (external adder_subtracter_virtex4_10_0_80b315fd28a09ef0_c_addsub_v10_0_xst_1_lib (edifLevel 0) |
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80 | (technology (numberDefinition)) |
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81 | (cell adder_subtracter_virtex4_10_0_80b315fd28a09ef0_c_addsub_v10_0_xst_1 (cellType GENERIC) |
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82 | (view view_1 (viewType NETLIST) |
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83 | (interface |
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84 | (port ( array ( rename a "a(10:0)") 11 ) (direction INPUT)) |
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85 | (port ( array ( rename b "b(10:0)") 11 ) (direction INPUT)) |
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86 | (port clk (direction INPUT)) |
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87 | (port add (direction INPUT)) |
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88 | (port c_in (direction INPUT)) |
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89 | (port ce (direction INPUT)) |
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90 | (port bypass (direction INPUT)) |
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91 | (port sclr (direction INPUT)) |
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92 | (port sset (direction INPUT)) |
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93 | (port sinit (direction INPUT)) |
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94 | (port c_out (direction OUTPUT)) |
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95 | (port ( array ( rename s "s(10:0)") 11 ) (direction OUTPUT)) |
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96 | ) |
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97 | ) |
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98 | ) |
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99 | ) |
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100 | (library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time)))) |
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101 | (cell adder_subtracter_virtex4_10_0_80b315fd28a09ef0 |
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102 | (cellType GENERIC) (view view_1 (viewType NETLIST) |
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103 | (interface |
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104 | (port ( array ( rename a "a(10:0)") 11 ) (direction INPUT)) |
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105 | (port ( array ( rename b "b(10:0)") 11 ) (direction INPUT)) |
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106 | (port ( array ( rename s "s(10:0)") 11 ) (direction OUTPUT)) |
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107 | ) |
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108 | (contents |
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109 | (instance VCC (viewRef view_1 (cellRef VCC (libraryRef xilinxun)))) |
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110 | (instance GND (viewRef view_1 (cellRef GND (libraryRef xilinxun)))) |
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111 | (instance BU2 |
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112 | (viewRef view_1 (cellRef adder_subtracter_virtex4_10_0_80b315fd28a09ef0_c_addsub_v10_0_xst_1 (libraryRef adder_subtracter_virtex4_10_0_80b315fd28a09ef0_c_addsub_v10_0_xst_1_lib))) |
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113 | ) |
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285 | (portRef (member s 6) (instanceRef BU2)) |
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309 | (portRef (member s 10) (instanceRef BU2)) |
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310 | ) |
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311 | ) |
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312 | )))) |
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313 | (design adder_subtracter_virtex4_10_0_80b315fd28a09ef0 (cellRef adder_subtracter_virtex4_10_0_80b315fd28a09ef0 (libraryRef test_lib)) |
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314 | (property X_CORE_INFO (string "c_addsub_v10_0, Xilinx CORE Generator 10.1.03_ip3")) |
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315 | (property PART (string "xc4vfx12-sf363-12") (owner "Xilinx")) |
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316 | )) |
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