source: PlatformSupport/Deprecated/pcores/Aurora_MGT/Pcore/mgt_fifo1_v1_00_a/data/mgt_fifo1_v2_1_0.mpd

## Copyright (c) 2004 Xilinx, Inc. All Rights Reserved.
## You may copy and modify these files for your own internal use solely with
## Xilinx programmable logic devices and  Xilinx EDK system or create IP
## modules solely for Xilinx programmable logic devices and Xilinx EDK system.
## No rights are granted to distribute any files unless they are distributed in
## Xilinx programmable logic devices.
###################################################################
##
## Name     : mgt_fifo1
## Desc     : Microprocessor Peripheral Description
##          : Automatically generated by PsfUtility
##
###################################################################

BEGIN mgt_fifo1

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = MIXED
OPTION USAGE_LEVEL = BASE_USER
OPTION IP_GROUP = MICROBLAZE:PPC:LOGICORE:IO ## was PPC:USER
OPTION CORE_STATE = ACTIVE ## WAS DEVELOPMENT
OPTION ARCH_SUPPORT = qrvirtex2:qvirtex2:spartan2:spartan2e:spartan3:virtex:virtex2:virtex2p:virtex4:virtexe:spartan3e

IO_INTERFACE IO_IF = mgt_fifo1_0, IO_TYPE = TAP_MGTFIFO1_V1


## Bus Interfaces
BUS_INTERFACE BUS = SOPB, BUS_TYPE = SLAVE, BUS_STD = OPB

## Generics for VHDL or Parameters for Verilog
PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x800, BUS = SOPB, ADDRESS = BASE, PAIR = C_HIGHADDR
PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, BUS = SOPB, ADDRESS = HIGH, PAIR = C_BASEADDR
PARAMETER C_OPB_AWIDTH = 32, DT = INTEGER, BUS = SOPB
PARAMETER C_OPB_DWIDTH = 32, DT = INTEGER, BUS = SOPB
PARAMETER C_FAMILY = virtex2p, DT = STRING

## Ports
 PORT OPB_Clk = "", DIR = I, SIGIS = Clk, BUS = SOPB
 PORT iTOP_REF_CLK = dcm_clk_s , DIR = I
 PORT OPB_Rst = OPB_Rst, DIR = I, SIGIS = Rst, BUS = SOPB
 PORT Sl_DBus = Sl_DBus, DIR = O, VEC = [0:(C_OPB_DWIDTH-1)], BUS = SOPB
 PORT Sl_errAck = Sl_errAck, DIR = O, BUS = SOPB
 PORT Sl_retry = Sl_retry, DIR = O, BUS = SOPB
 PORT Sl_toutSup = Sl_toutSup, DIR = O, BUS = SOPB
 PORT Sl_xferAck = Sl_xferAck, DIR = O, BUS = SOPB
 PORT OPB_ABus = OPB_ABus, DIR = I, VEC = [0:(C_OPB_AWIDTH-1)], BUS = SOPB
 PORT OPB_BE = OPB_BE, DIR = I, VEC = [0:((C_OPB_DWIDTH/8)-1)], BUS = SOPB
 PORT OPB_DBus = OPB_DBus, DIR = I, VEC = [0:(C_OPB_DWIDTH-1)], BUS = SOPB
 PORT OPB_RNW = OPB_RNW, DIR = I, BUS = SOPB
 PORT OPB_select = OPB_select, DIR = I, BUS = SOPB
 PORT OPB_seqAddr = OPB_seqAddr, DIR = I, BUS = SOPB
 PORT iTXN = "", DIR = O, PERMIT = BASE_USER, DESC = "Transmit-neg", IO_IF = mgt_fifo1_0, IO_IS = trans_neg
 PORT iTXP = "", DIR = O, PERMIT = BASE_USER, DESC = "Transit-pos", IO_IF = mgt_fifo1_0, IO_IS = trans_pos
 PORT iRXN = "", DIR = I, PERMIT = BASE_USER, DESC = "Receive-neg", IO_IF = mgt_fifo1_0, IO_IS = rec_neg
 PORT iRXP = "", DIR = I, PERMIT = BASE_USER, DESC = "Receive-pos", IO_IF = mgt_fifo1_0, IO_IS = rec_pos
 

END