source: PlatformSupport/Deprecated/pcores/Aurora_MGT/Pcore/mgt_fifo1_v1_00_a/data/mgt_fifo1_v2_1_0.pao

Last change on this file was 29, checked in by snovich, 19 years ago

This is the first fully succseful MGT Peripheral which has been incorproated into the current Rice TAP XBD file.

File size: 3.9 KB
Line 
1##############################################################################
2##
3## ***************************************************************************
4## **                                                                       **
5## ** Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.            **
6## **                                                                       **
7## ** You may copy and modify these files for your own internal use solely  **
8## ** with Xilinx programmable logic devices and Xilinx EDK system or       **
9## ** create IP modules solely for Xilinx programmable logic devices and    **
10## ** Xilinx EDK system. No rights are granted to distribute any files      **
11## ** unless they are distributed in Xilinx programmable logic devices.     **
12## **                                                                       **
13## ***************************************************************************
14##
15##############################################################################
16## Filename:          C:\edk_user_repository\MyProcessorIPLib\pcores\mgt_fifo1_v1_00_a\data\mgt_fifo1_v2_1_0.pao
17## Description:       Peripheral Analysis Order
18## Date:              Tue Jul 05 10:18:46 2005 (by Create and Import Peripheral Wizard)
19##############################################################################
20
21lib proc_common_v2_00_a proc_common_pkg vhdl
22lib proc_common_v2_00_a family vhdl
23lib proc_common_v2_00_a or_muxcy vhdl
24lib proc_common_v2_00_a or_gate vhdl
25lib proc_common_v2_00_a counter_bit vhdl
26lib proc_common_v2_00_a counter vhdl
27lib proc_common_v2_00_a inferred_lut4 vhdl
28lib proc_common_v2_00_a srl_fifo2 vhdl
29lib proc_common_v2_00_a pf_counter_bit vhdl
30lib proc_common_v2_00_a pf_counter vhdl
31lib proc_common_v2_00_a pf_counter_top vhdl
32lib proc_common_v2_00_a pf_occ_counter vhdl
33lib proc_common_v2_00_a pf_occ_counter_top vhdl
34lib proc_common_v2_00_a pf_adder_bit vhdl
35lib proc_common_v2_00_a pf_adder vhdl
36lib proc_common_v2_00_a pf_dpram_select vhdl
37lib proc_common_v2_00_a srl16_fifo vhdl
38lib proc_common_v2_00_a pselect vhdl
39lib proc_common_v2_00_a valid_be vhdl
40lib proc_common_v2_00_a ld_arith_reg vhdl
41lib proc_common_v2_00_a mux_onehot vhdl
42lib proc_common_v2_00_a down_counter vhdl
43lib proc_common_v2_00_a ipif_pkg vhdl
44lib proc_common_v2_00_a ipif_steer vhdl
45lib proc_common_v2_00_a direct_path_cntr_ai vhdl
46lib interrupt_control_v1_00_a interrupt_control vhdl
47lib wrpfifo_v1_01_b pf_dly1_mux vhdl
48lib wrpfifo_v1_01_b ipif_control_wr vhdl
49lib wrpfifo_v1_01_b wrpfifo_dp_cntl vhdl
50lib wrpfifo_v1_01_b wrpfifo_top vhdl
51lib rdpfifo_v1_01_b ipif_control_rd vhdl
52lib rdpfifo_v1_01_b rdpfifo_dp_cntl vhdl
53lib rdpfifo_v1_01_b rdpfifo_top vhdl
54lib opb_ipif_v3_01_a reset_mir vhdl
55lib opb_ipif_v3_01_a brst_addr_cntr vhdl
56lib opb_ipif_v3_01_a opb_flex_addr_cntr vhdl
57lib opb_ipif_v3_01_a brst_addr_cntr_reg vhdl
58lib opb_ipif_v3_01_a opb_be_gen vhdl
59lib opb_ipif_v3_01_a srl_fifo3 vhdl
60lib opb_ipif_v3_01_a write_buffer vhdl
61lib opb_ipif_v3_01_a opb_bam vhdl
62lib opb_ipif_v3_01_a opb_ipif vhdl
63lib mgt_fifo1_v1_00_a user_logic verilog
64lib mgt_fifo1_v1_00_a aurora_lane_4byte verilog
65lib mgt_fifo1_v1_00_a aurora4bitstream1 verilog
66lib mgt_fifo1_v1_00_a channel_error_detect verilog
67lib mgt_fifo1_v1_00_a channel_init_sm verilog
68lib mgt_fifo1_v1_00_a chbond_count_dec_4byte verilog
69lib mgt_fifo1_v1_00_a clock_module verilog
70lib mgt_fifo1_v1_00_a error_detect_4byte verilog
71lib mgt_fifo1_v1_00_a global_logic verilog
72lib mgt_fifo1_v1_00_a idle_and_ver_gen verilog
73lib mgt_fifo1_v1_00_a lane_init_sm_4byte verilog
74lib mgt_fifo1_v1_00_a phase_align verilog
75lib mgt_fifo1_v1_00_a rx_stream verilog
76lib mgt_fifo1_v1_00_a sym_dec_4byte verilog
77lib mgt_fifo1_v1_00_a sym_gen_4byte verilog
78lib mgt_fifo1_v1_00_a standard_cc_module verilog
79lib mgt_fifo1_v1_00_a tx_stream verilog
80lib mgt_fifo1_v1_00_a mgt_fifo1 vhdl
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