source: PlatformSupport/Deprecated/pcores/EEPROM_v1_01_a/data/EEPROM_v2_1_0.pao

Last change on this file was 564, checked in by murphpo, 17 years ago

Updated EEPROM core with synthesis constraints to prevent unnecessary BUFG usage
File size: 2.4 KB
Line 
1##############################################################################
2## Filename:          F:\localHome\bratton\WARPWork\IPs\MyProcessorIPLib\pcores/EEPROM_v1_00_a/data/EEPROM_v2_1_0.pao
3## Description:       Peripheral Analysis Order
4## Date:              Thu Aug 03 11:18:00 2006 (by Create and Import Peripheral Wizard)
5##############################################################################
6
7lib proc_common_v2_00_a proc_common_pkg vhdl
8lib proc_common_v2_00_a family vhdl
9lib proc_common_v2_00_a or_muxcy vhdl
10lib proc_common_v2_00_a or_gate vhdl
11lib proc_common_v2_00_a counter_bit vhdl
12lib proc_common_v2_00_a counter vhdl
13lib proc_common_v2_00_a inferred_lut4 vhdl
14lib proc_common_v2_00_a srl_fifo2 vhdl
15lib proc_common_v2_00_a pf_counter_bit vhdl
16lib proc_common_v2_00_a pf_counter vhdl
17lib proc_common_v2_00_a pf_counter_top vhdl
18lib proc_common_v2_00_a pf_occ_counter vhdl
19lib proc_common_v2_00_a pf_occ_counter_top vhdl
20lib proc_common_v2_00_a pf_adder_bit vhdl
21lib proc_common_v2_00_a pf_adder vhdl
22lib proc_common_v2_00_a pf_dpram_select vhdl
23lib proc_common_v2_00_a srl16_fifo vhdl
24lib proc_common_v2_00_a pselect vhdl
25lib proc_common_v2_00_a valid_be vhdl
26lib proc_common_v2_00_a ld_arith_reg vhdl
27lib proc_common_v2_00_a mux_onehot vhdl
28lib proc_common_v2_00_a down_counter vhdl
29lib proc_common_v2_00_a ipif_pkg vhdl
30lib proc_common_v2_00_a ipif_steer vhdl
31lib proc_common_v2_00_a direct_path_cntr_ai vhdl
32lib interrupt_control_v1_00_a interrupt_control vhdl
33lib wrpfifo_v1_01_b pf_dly1_mux vhdl
34lib wrpfifo_v1_01_b ipif_control_wr vhdl
35lib wrpfifo_v1_01_b wrpfifo_dp_cntl vhdl
36lib wrpfifo_v1_01_b wrpfifo_top vhdl
37lib rdpfifo_v1_01_b ipif_control_rd vhdl
38lib rdpfifo_v1_01_b rdpfifo_dp_cntl vhdl
39lib rdpfifo_v1_01_b rdpfifo_top vhdl
40lib opb_ipif_v3_01_c reset_mir vhdl
41lib opb_ipif_v3_01_c brst_addr_cntr vhdl
42lib opb_ipif_v3_01_c opb_flex_addr_cntr vhdl
43lib opb_ipif_v3_01_c brst_addr_cntr_reg vhdl
44lib opb_ipif_v3_01_c opb_be_gen vhdl
45lib opb_ipif_v3_01_c srl_fifo3 vhdl
46lib opb_ipif_v3_01_c write_buffer vhdl
47lib opb_ipif_v3_01_c opb_bam vhdl
48lib opb_ipif_v3_01_c opb_ipif vhdl
49lib EEPROM_v1_01_a clk_prescaler verilog
50lib EEPROM_v1_01_a one_wire_interface verilog
51lib EEPROM_v1_01_a one_wire_io verilog
52lib EEPROM_v1_01_a onewiremaster verilog
53lib EEPROM_v1_01_a OWM verilog
54lib EEPROM_v1_01_a user_logic verilog
55lib EEPROM_v1_01_a EEPROM vhdl
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