source:
PlatformSupport/Deprecated/pcores/EEPROM_v1_01_a/hdl/verilog
Name | Size | Rev | Age | Author | Last Change |
---|---|---|---|---|---|
../ | |||||
user_logic.v | 11.7 KB | 564 | 17 years | murphpo | Updated EEPROM core with synthesis constraints to prevent unnecessary … |
OWM.v | 6.4 KB | 564 | 17 years | murphpo | Updated EEPROM core with synthesis constraints to prevent unnecessary … |
onewiremaster.v | 49.1 KB | 564 | 17 years | murphpo | Updated EEPROM core with synthesis constraints to prevent unnecessary … |
one_wire_io.v | 4.3 KB | 564 | 17 years | murphpo | Updated EEPROM core with synthesis constraints to prevent unnecessary … |
one_wire_interface.v | 13.4 KB | 564 | 17 years | murphpo | Updated EEPROM core with synthesis constraints to prevent unnecessary … |
clk_prescaler.v | 5.4 KB | 564 | 17 years | murphpo | Updated EEPROM core with synthesis constraints to prevent unnecessary … |
Note: See TracBrowser
for help on using the repository browser.