1 | ------------------------------------------------------------------------------ |
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2 | -- EEPROM.vhd - entity/architecture pair |
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3 | ------------------------------------------------------------------------------ |
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4 | -- IMPORTANT: |
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5 | -- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS. |
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6 | -- |
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7 | -- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED. |
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8 | -- |
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9 | -- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW |
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10 | -- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION |
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11 | -- OF THE USER_LOGIC ENTITY. |
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12 | ------------------------------------------------------------------------------ |
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13 | -- |
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14 | -- *************************************************************************** |
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15 | -- ** Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. ** |
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16 | -- ** ** |
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17 | -- ** Xilinx, Inc. ** |
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18 | -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** |
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19 | -- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** |
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20 | -- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** |
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21 | -- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** |
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22 | -- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** |
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23 | -- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** |
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24 | -- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** |
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25 | -- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** |
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26 | -- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** |
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27 | -- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** |
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28 | -- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** |
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29 | -- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** |
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30 | -- ** FOR A PARTICULAR PURPOSE. ** |
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31 | -- ** ** |
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32 | -- *************************************************************************** |
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33 | -- |
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34 | ------------------------------------------------------------------------------ |
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35 | -- Filename: EEPROM.vhd |
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36 | -- Version: 1.00.a |
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37 | -- Description: Top level design, instantiates IPIF and user logic. |
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38 | -- Date: Fri Jul 28 13:08:06 2006 (by Create and Import Peripheral Wizard) |
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39 | -- VHDL Standard: VHDL'93 |
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40 | ------------------------------------------------------------------------------ |
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41 | -- Naming Conventions: |
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42 | -- active low signals: "*_n" |
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43 | -- clock signals: "clk", "clk_div#", "clk_#x" |
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44 | -- reset signals: "rst", "rst_n" |
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45 | -- generics: "C_*" |
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46 | -- user defined types: "*_TYPE" |
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47 | -- state machine next state: "*_ns" |
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48 | -- state machine current state: "*_cs" |
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49 | -- combinatorial signals: "*_com" |
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50 | -- pipelined or register delay signals: "*_d#" |
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51 | -- counter signals: "*cnt*" |
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52 | -- clock enable signals: "*_ce" |
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53 | -- internal version of output port: "*_i" |
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54 | -- device pins: "*_pin" |
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55 | -- ports: "- Names begin with Uppercase" |
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56 | -- processes: "*_PROCESS" |
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57 | -- component instantiations: "<ENTITY_>I_<#|FUNC>" |
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58 | ------------------------------------------------------------------------------ |
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59 | |
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60 | library ieee; |
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61 | use ieee.std_logic_1164.all; |
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62 | use ieee.std_logic_arith.all; |
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63 | use ieee.std_logic_unsigned.all; |
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64 | |
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65 | library proc_common_v2_00_a; |
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66 | use proc_common_v2_00_a.proc_common_pkg.all; |
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67 | use proc_common_v2_00_a.ipif_pkg.all; |
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68 | library opb_ipif_v3_01_c; |
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69 | use opb_ipif_v3_01_c.all; |
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70 | |
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71 | library EEPROM_v1_01_a; |
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72 | use EEPROM_v1_01_a.all; |
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73 | |
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74 | ------------------------------------------------------------------------------ |
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75 | -- Entity section |
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76 | ------------------------------------------------------------------------------ |
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77 | -- Definition of Generics: |
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78 | -- C_BASEADDR -- User logic base address |
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79 | -- C_HIGHADDR -- User logic high address |
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80 | -- C_OPB_AWIDTH -- OPB address bus width |
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81 | -- C_OPB_DWIDTH -- OPB data bus width |
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82 | -- C_USER_ID_CODE -- User ID to place in MIR/Reset register |
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83 | -- C_FAMILY -- Target FPGA architecture |
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84 | -- |
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85 | -- Definition of Ports: |
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86 | -- OPB_Clk -- OPB Clock |
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87 | -- OPB_Rst -- OPB Reset |
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88 | -- Sl_DBus -- Slave data bus |
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89 | -- Sl_errAck -- Slave error acknowledge |
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90 | -- Sl_retry -- Slave retry |
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91 | -- Sl_toutSup -- Slave timeout suppress |
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92 | -- Sl_xferAck -- Slave transfer acknowledge |
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93 | -- OPB_ABus -- OPB address bus |
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94 | -- OPB_BE -- OPB byte enable |
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95 | -- OPB_DBus -- OPB data bus |
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96 | -- OPB_RNW -- OPB read/not write |
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97 | -- OPB_select -- OPB select |
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98 | -- OPB_seqAddr -- OPB sequential address |
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99 | ------------------------------------------------------------------------------ |
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100 | |
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101 | entity EEPROM is |
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102 | generic |
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103 | ( |
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104 | -- ADD USER GENERICS BELOW THIS LINE --------------- |
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105 | --USER generics added here |
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106 | -- ADD USER GENERICS ABOVE THIS LINE --------------- |
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107 | |
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108 | -- DO NOT EDIT BELOW THIS LINE --------------------- |
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109 | -- Bus protocol parameters, do not add to or delete |
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110 | C_BASEADDR : std_logic_vector := X"FFFFFFFF"; |
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111 | C_HIGHADDR : std_logic_vector := X"00000000"; |
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112 | C_OPB_AWIDTH : integer := 32; |
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113 | C_OPB_DWIDTH : integer := 32; |
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114 | C_USER_ID_CODE : integer := 3; |
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115 | C_FAMILY : string := "virtex2p" |
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116 | -- DO NOT EDIT ABOVE THIS LINE --------------------- |
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117 | ); |
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118 | port |
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119 | ( |
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120 | -- ADD USER PORTS BELOW THIS LINE ------------------ |
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121 | DQ0_T : out std_logic; |
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122 | DQ0_O : out std_logic; |
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123 | DQ0_I : in std_logic; |
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124 | |
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125 | DQ1_T : out std_logic; |
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126 | DQ1_O : out std_logic; |
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127 | DQ1_I : in std_logic; |
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128 | |
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129 | DQ2_T : out std_logic; |
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130 | DQ2_O : out std_logic; |
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131 | DQ2_I : in std_logic; |
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132 | |
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133 | DQ3_T : out std_logic; |
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134 | DQ3_O : out std_logic; |
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135 | DQ3_I : in std_logic; |
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136 | |
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137 | DQ4_T : out std_logic; |
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138 | DQ4_O : out std_logic; |
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139 | DQ4_I : in std_logic; |
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140 | |
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141 | DQ5_T : out std_logic; |
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142 | DQ5_O : out std_logic; |
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143 | DQ5_I : in std_logic; |
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144 | |
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145 | DQ6_T : out std_logic; |
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146 | DQ6_O : out std_logic; |
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147 | DQ6_I : in std_logic; |
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148 | |
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149 | DQ7_T : out std_logic; |
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150 | DQ7_O : out std_logic; |
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151 | DQ7_I : in std_logic; |
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152 | |
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153 | -- ADD USER PORTS ABOVE THIS LINE ------------------ |
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154 | |
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155 | -- DO NOT EDIT BELOW THIS LINE --------------------- |
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156 | -- Bus protocol ports, do not add to or delete |
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157 | OPB_Clk : in std_logic; |
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158 | OPB_Rst : in std_logic; |
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159 | Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); |
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160 | Sl_errAck : out std_logic; |
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161 | Sl_retry : out std_logic; |
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162 | Sl_toutSup : out std_logic; |
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163 | Sl_xferAck : out std_logic; |
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164 | OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1); |
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165 | OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1); |
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166 | OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); |
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167 | OPB_RNW : in std_logic; |
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168 | OPB_select : in std_logic; |
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169 | OPB_seqAddr : in std_logic |
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170 | -- DO NOT EDIT ABOVE THIS LINE --------------------- |
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171 | ); |
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172 | |
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173 | attribute SIGIS : string; |
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174 | attribute SIGIS of OPB_Clk : signal is "Clk"; |
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175 | attribute SIGIS of OPB_Rst : signal is "Rst"; |
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176 | |
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177 | attribute MIN_SIZE : string; |
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178 | attribute MIN_SIZE of C_BASEADDR:constant is "0x100"; |
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179 | |
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180 | attribute INITIALVAL : string; |
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181 | attribute INITIALVAL of DQ1_I : signal is "VCC"; |
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182 | attribute INITIALVAL of DQ2_I : signal is "VCC"; |
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183 | attribute INITIALVAL of DQ3_I : signal is "VCC"; |
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184 | attribute INITIALVAL of DQ4_I : signal is "VCC"; |
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185 | attribute INITIALVAL of DQ5_I : signal is "VCC"; |
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186 | attribute INITIALVAL of DQ6_I : signal is "VCC"; |
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187 | attribute INITIALVAL of DQ7_I : signal is "VCC"; |
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188 | |
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189 | end entity EEPROM; |
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190 | |
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191 | ------------------------------------------------------------------------------ |
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192 | -- Architecture section |
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193 | ------------------------------------------------------------------------------ |
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194 | |
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195 | architecture IMP of EEPROM is |
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196 | |
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197 | ------------------------------------------ |
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198 | -- Constant: array of address range identifiers |
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199 | ------------------------------------------ |
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200 | constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE := |
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201 | ( |
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202 | 0 => USER_00, -- user logic address space |
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203 | 1 => IPIF_RST -- include IPIF S/W Reset/MIR service |
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204 | ); |
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205 | |
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206 | ------------------------------------------ |
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207 | -- Constant: array of address pairs for each address range |
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208 | ------------------------------------------ |
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209 | constant ZERO_ADDR_PAD : std_logic_vector(0 to 64-C_OPB_AWIDTH-1) := (others => '0'); |
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210 | |
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211 | constant USER_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000"; |
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212 | constant USER_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF"; |
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213 | |
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214 | constant RST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100"; |
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215 | constant RST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF"; |
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216 | |
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217 | constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := |
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218 | ( |
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219 | ZERO_ADDR_PAD & USER_BASEADDR, -- user logic base address |
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220 | ZERO_ADDR_PAD & USER_HIGHADDR, -- user logic high address |
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221 | ZERO_ADDR_PAD & RST_BASEADDR, -- MIR/Reset register base address |
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222 | ZERO_ADDR_PAD & RST_HIGHADDR -- MIR/Reset register high address |
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223 | ); |
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224 | |
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225 | ------------------------------------------ |
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226 | -- Constant: array of data widths for each target address range |
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227 | ------------------------------------------ |
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228 | constant USER_DWIDTH : integer := C_OPB_DWIDTH; |
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229 | |
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230 | constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE := |
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231 | ( |
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232 | 0 => USER_DWIDTH, -- user logic data width |
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233 | 1 => C_OPB_DWIDTH -- MIR/Reset register data width |
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234 | ); |
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235 | |
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236 | ------------------------------------------ |
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237 | -- Constant: array of desired number of chip enables for each address range |
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238 | ------------------------------------------ |
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239 | constant USER_NUM_CE : integer := 1; |
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240 | |
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241 | constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := |
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242 | ( |
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243 | 0 => pad_power2(USER_NUM_CE), -- user logic number of CEs |
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244 | 1 => 1 -- MIR/Reset register - 1 CE |
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245 | ); |
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246 | |
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247 | ------------------------------------------ |
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248 | -- Constant: array of unique properties for each address range |
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249 | ------------------------------------------ |
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250 | constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE := |
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251 | ( |
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252 | 0 => (others => 0), -- user logic slave space dependent properties (none defined) |
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253 | 1 => (others => 0) -- IPIF reset/mir dependent properties (none defined) |
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254 | ); |
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255 | |
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256 | ------------------------------------------ |
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257 | -- Constant: pipeline mode |
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258 | -- 1 = include OPB-In pipeline registers |
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259 | -- 2 = include IP pipeline registers |
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260 | -- 3 = include OPB-In and IP pipeline registers |
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261 | -- 4 = include OPB-Out pipeline registers |
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262 | -- 5 = include OPB-In and OPB-Out pipeline registers |
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263 | -- 6 = include IP and OPB-Out pipeline registers |
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264 | -- 7 = include OPB-In, IP, and OPB-Out pipeline registers |
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265 | -- Note: |
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266 | -- only mode 4, 5, 7 are supported for this release |
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267 | ------------------------------------------ |
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268 | constant PIPELINE_MODEL : integer := 5; |
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269 | |
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270 | ------------------------------------------ |
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271 | -- Constant: user core ID code |
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272 | ------------------------------------------ |
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273 | constant DEV_BLK_ID : integer := C_USER_ID_CODE; |
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274 | |
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275 | ------------------------------------------ |
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276 | -- Constant: enable MIR/Reset register |
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277 | ------------------------------------------ |
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278 | constant DEV_MIR_ENABLE : integer := 1; |
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279 | |
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280 | ------------------------------------------ |
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281 | -- Constant: array of IP interrupt mode |
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282 | -- 1 = Active-high interrupt condition |
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283 | -- 2 = Active-low interrupt condition |
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284 | -- 3 = Active-high pulse interrupt event |
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285 | -- 4 = Active-low pulse interrupt event |
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286 | -- 5 = Positive-edge interrupt event |
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287 | -- 6 = Negative-edge interrupt event |
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288 | ------------------------------------------ |
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289 | constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE := |
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290 | ( |
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291 | 0 => 0 -- not used |
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292 | ); |
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293 | |
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294 | ------------------------------------------ |
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295 | -- Constant: enable device burst |
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296 | ------------------------------------------ |
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297 | constant DEV_BURST_ENABLE : integer := 0; |
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298 | |
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299 | ------------------------------------------ |
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300 | -- Constant: include address counter for burst transfers |
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301 | ------------------------------------------ |
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302 | constant INCLUDE_ADDR_CNTR : integer := 0; |
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303 | |
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304 | ------------------------------------------ |
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305 | -- Constant: include write buffer that decouples OPB and IPIC write transactions |
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306 | ------------------------------------------ |
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307 | constant INCLUDE_WR_BUF : integer := 0; |
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308 | |
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309 | ------------------------------------------ |
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310 | -- Constant: index for CS/CE |
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311 | ------------------------------------------ |
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312 | constant USER_NUM_CS : integer := 1; |
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313 | |
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314 | constant USER00_CS_INDEX : integer := get_id_index(ARD_ID_ARRAY, USER_00); |
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315 | |
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316 | constant USER00_CE_INDEX : integer := calc_start_ce_index(ARD_NUM_CE_ARRAY, USER00_CS_INDEX); |
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317 | |
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318 | ------------------------------------------ |
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319 | -- IP Interconnect (IPIC) signal declarations -- do not delete |
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320 | -- prefix 'i' stands for IPIF while prefix 'u' stands for user logic |
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321 | -- typically user logic will be hooked up to IPIF directly via i<sig> |
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322 | -- unless signal slicing and muxing are needed via u<sig> |
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323 | ------------------------------------------ |
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324 | signal iBus2IP_CS : std_logic_vector(0 to ARD_ID_ARRAY'length-1); |
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325 | signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1); |
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326 | signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1); |
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327 | signal iBus2IP_Data : std_logic_vector(0 to C_OPB_DWIDTH-1); |
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328 | signal iBus2IP_Addr : std_logic_vector(0 to C_OPB_AWIDTH-1); |
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329 | signal iBus2IP_BE : std_logic_vector(0 to C_OPB_DWIDTH/8-1); |
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330 | signal iBus2IP_RNW : std_logic; |
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331 | signal iIP2Bus_Data : std_logic_vector(0 to C_OPB_DWIDTH-1) := (others => '0'); |
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332 | signal iIP2Bus_Ack : std_logic := '0'; |
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333 | signal iIP2Bus_Error : std_logic := '0'; |
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334 | signal iIP2Bus_Retry : std_logic := '0'; |
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335 | signal iIP2Bus_ToutSup : std_logic := '0'; |
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336 | signal iIP2Bus_PostedWrInh : std_logic_vector(0 to ARD_ID_ARRAY'length-1) := (others => '0'); |
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337 | signal ZERO_IP2RFIFO_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_RDFIFO_DATA))-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping |
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338 | signal ZERO_WFIFO2IP_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_WRFIFO_DATA))-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping |
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339 | signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping |
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340 | signal iBus2IP_Clk : std_logic; |
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341 | signal iBus2IP_Reset : std_logic; |
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342 | signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1); |
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343 | signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1); |
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344 | signal uBus2IP_CS : std_logic_vector(0 to USER_NUM_CS-1); |
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345 | signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1); |
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346 | signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1); |
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347 | signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1); |
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348 | signal uIP2Bus_PostedWrInh : std_logic; |
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349 | |
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350 | ------------------------------------------ |
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351 | -- Component declaration for verilog user logic |
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352 | ------------------------------------------ |
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353 | component user_logic is |
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354 | generic |
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355 | ( |
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356 | -- ADD USER GENERICS BELOW THIS LINE --------------- |
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357 | --USER generics added here |
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358 | -- ADD USER GENERICS ABOVE THIS LINE --------------- |
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359 | |
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360 | -- DO NOT EDIT BELOW THIS LINE --------------------- |
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361 | -- Bus protocol parameters, do not add to or delete |
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362 | C_AWIDTH : integer := 32; |
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363 | C_DWIDTH : integer := 32; |
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364 | C_NUM_CS : integer := 1; |
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365 | C_NUM_CE : integer := 1 |
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366 | -- DO NOT EDIT ABOVE THIS LINE --------------------- |
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367 | ); |
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368 | port |
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369 | ( |
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370 | -- ADD USER PORTS BELOW THIS LINE ------------------ |
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371 | DQ0_T : out std_logic; |
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372 | DQ0_O : out std_logic; |
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373 | DQ0_I : in std_logic; |
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374 | |
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375 | DQ1_T : out std_logic; |
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376 | DQ1_O : out std_logic; |
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377 | DQ1_I : in std_logic; |
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378 | |
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379 | DQ2_T : out std_logic; |
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380 | DQ2_O : out std_logic; |
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381 | DQ2_I : in std_logic; |
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382 | |
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383 | DQ3_T : out std_logic; |
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384 | DQ3_O : out std_logic; |
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385 | DQ3_I : in std_logic; |
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386 | |
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387 | DQ4_T : out std_logic; |
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388 | DQ4_O : out std_logic; |
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389 | DQ4_I : in std_logic; |
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390 | |
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391 | DQ5_T : out std_logic; |
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392 | DQ5_O : out std_logic; |
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393 | DQ5_I : in std_logic; |
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394 | |
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395 | DQ6_T : out std_logic; |
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396 | DQ6_O : out std_logic; |
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397 | DQ6_I : in std_logic; |
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398 | |
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399 | DQ7_T : out std_logic; |
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400 | DQ7_O : out std_logic; |
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401 | DQ7_I : in std_logic; |
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402 | -- ADD USER PORTS ABOVE THIS LINE ------------------ |
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403 | |
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404 | -- DO NOT EDIT BELOW THIS LINE --------------------- |
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405 | -- Bus protocol ports, do not add to or delete |
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406 | Bus2IP_Clk : in std_logic; |
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407 | Bus2IP_Reset : in std_logic; |
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408 | Bus2IP_Addr : in std_logic_vector(0 to C_AWIDTH-1); |
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409 | Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1); |
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410 | Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1); |
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411 | Bus2IP_RNW : in std_logic; |
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412 | Bus2IP_CS : in std_logic_vector(0 to C_NUM_CS-1); |
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413 | Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1); |
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414 | Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1); |
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415 | IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1); |
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416 | IP2Bus_Ack : out std_logic; |
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417 | IP2Bus_Retry : out std_logic; |
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418 | IP2Bus_Error : out std_logic; |
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419 | IP2Bus_ToutSup : out std_logic; |
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420 | IP2Bus_PostedWrInh : out std_logic |
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421 | -- DO NOT EDIT ABOVE THIS LINE --------------------- |
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422 | ); |
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423 | end component user_logic; |
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424 | |
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425 | begin |
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426 | |
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427 | ------------------------------------------ |
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428 | -- instantiate the OPB IPIF |
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429 | ------------------------------------------ |
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430 | OPB_IPIF_I : entity opb_ipif_v3_01_c.opb_ipif |
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431 | generic map |
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432 | ( |
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433 | C_ARD_ID_ARRAY => ARD_ID_ARRAY, |
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434 | C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY, |
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435 | C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY, |
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436 | C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY, |
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437 | C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY, |
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438 | C_PIPELINE_MODEL => PIPELINE_MODEL, |
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439 | C_DEV_BLK_ID => DEV_BLK_ID, |
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440 | C_DEV_MIR_ENABLE => DEV_MIR_ENABLE, |
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441 | C_OPB_AWIDTH => C_OPB_AWIDTH, |
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442 | C_OPB_DWIDTH => C_OPB_DWIDTH, |
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443 | C_FAMILY => C_FAMILY, |
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444 | C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY, |
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445 | C_DEV_BURST_ENABLE => DEV_BURST_ENABLE, |
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446 | C_INCLUDE_ADDR_CNTR => INCLUDE_ADDR_CNTR, |
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447 | C_INCLUDE_WR_BUF => INCLUDE_WR_BUF |
---|
448 | ) |
---|
449 | port map |
---|
450 | ( |
---|
451 | OPB_select => OPB_select, |
---|
452 | OPB_DBus => OPB_DBus, |
---|
453 | OPB_ABus => OPB_ABus, |
---|
454 | OPB_BE => OPB_BE, |
---|
455 | OPB_RNW => OPB_RNW, |
---|
456 | OPB_seqAddr => OPB_seqAddr, |
---|
457 | Sln_DBus => Sl_DBus, |
---|
458 | Sln_xferAck => Sl_xferAck, |
---|
459 | Sln_errAck => Sl_errAck, |
---|
460 | Sln_retry => Sl_retry, |
---|
461 | Sln_toutSup => Sl_toutSup, |
---|
462 | Bus2IP_CS => iBus2IP_CS, |
---|
463 | Bus2IP_CE => open, |
---|
464 | Bus2IP_RdCE => iBus2IP_RdCE, |
---|
465 | Bus2IP_WrCE => iBus2IP_WrCE, |
---|
466 | Bus2IP_Data => iBus2IP_Data, |
---|
467 | Bus2IP_Addr => iBus2IP_Addr, |
---|
468 | Bus2IP_AddrValid => open, |
---|
469 | Bus2IP_BE => iBus2IP_BE, |
---|
470 | Bus2IP_RNW => iBus2IP_RNW, |
---|
471 | Bus2IP_Burst => open, |
---|
472 | IP2Bus_Data => iIP2Bus_Data, |
---|
473 | IP2Bus_Ack => iIP2Bus_Ack, |
---|
474 | IP2Bus_AddrAck => '0', |
---|
475 | IP2Bus_Error => iIP2Bus_Error, |
---|
476 | IP2Bus_Retry => iIP2Bus_Retry, |
---|
477 | IP2Bus_ToutSup => iIP2Bus_ToutSup, |
---|
478 | IP2Bus_PostedWrInh => iIP2Bus_PostedWrInh, |
---|
479 | IP2RFIFO_Data => ZERO_IP2RFIFO_Data, |
---|
480 | IP2RFIFO_WrMark => '0', |
---|
481 | IP2RFIFO_WrRelease => '0', |
---|
482 | IP2RFIFO_WrReq => '0', |
---|
483 | IP2RFIFO_WrRestore => '0', |
---|
484 | RFIFO2IP_AlmostFull => open, |
---|
485 | RFIFO2IP_Full => open, |
---|
486 | RFIFO2IP_Vacancy => open, |
---|
487 | RFIFO2IP_WrAck => open, |
---|
488 | IP2WFIFO_RdMark => '0', |
---|
489 | IP2WFIFO_RdRelease => '0', |
---|
490 | IP2WFIFO_RdReq => '0', |
---|
491 | IP2WFIFO_RdRestore => '0', |
---|
492 | WFIFO2IP_AlmostEmpty => open, |
---|
493 | WFIFO2IP_Data => ZERO_WFIFO2IP_Data, |
---|
494 | WFIFO2IP_Empty => open, |
---|
495 | WFIFO2IP_Occupancy => open, |
---|
496 | WFIFO2IP_RdAck => open, |
---|
497 | IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent, |
---|
498 | IP2INTC_Irpt => open, |
---|
499 | Freeze => '0', |
---|
500 | Bus2IP_Freeze => open, |
---|
501 | OPB_Clk => OPB_Clk, |
---|
502 | Bus2IP_Clk => iBus2IP_Clk, |
---|
503 | IP2Bus_Clk => '0', |
---|
504 | Reset => OPB_Rst, |
---|
505 | Bus2IP_Reset => iBus2IP_Reset |
---|
506 | ); |
---|
507 | |
---|
508 | ------------------------------------------ |
---|
509 | -- instantiate the User Logic |
---|
510 | ------------------------------------------ |
---|
511 | USER_LOGIC_I : component user_logic |
---|
512 | generic map |
---|
513 | ( |
---|
514 | -- MAP USER GENERICS BELOW THIS LINE --------------- |
---|
515 | --USER generics mapped here |
---|
516 | -- MAP USER GENERICS ABOVE THIS LINE --------------- |
---|
517 | |
---|
518 | C_DWIDTH => USER_DWIDTH, |
---|
519 | C_NUM_CE => USER_NUM_CE, |
---|
520 | C_AWIDTH => C_OPB_AWIDTH, |
---|
521 | C_NUM_CS => USER_NUM_CS |
---|
522 | ) |
---|
523 | port map |
---|
524 | ( |
---|
525 | -- MAP USER PORTS BELOW THIS LINE ------------------ |
---|
526 | DQ0_T => DQ0_T, |
---|
527 | DQ0_O => DQ0_O, |
---|
528 | DQ0_I => DQ0_I, |
---|
529 | |
---|
530 | DQ1_T => DQ1_T, |
---|
531 | DQ1_O => DQ1_O, |
---|
532 | DQ1_I => DQ1_I, |
---|
533 | |
---|
534 | DQ2_T => DQ2_T, |
---|
535 | DQ2_O => DQ2_O, |
---|
536 | DQ2_I => DQ2_I, |
---|
537 | |
---|
538 | DQ3_T => DQ3_T, |
---|
539 | DQ3_O => DQ3_O, |
---|
540 | DQ3_I => DQ3_I, |
---|
541 | |
---|
542 | DQ4_T => DQ4_T, |
---|
543 | DQ4_O => DQ4_O, |
---|
544 | DQ4_I => DQ4_I, |
---|
545 | |
---|
546 | DQ5_T => DQ5_T, |
---|
547 | DQ5_O => DQ5_O, |
---|
548 | DQ5_I => DQ5_I, |
---|
549 | |
---|
550 | DQ6_T => DQ6_T, |
---|
551 | DQ6_O => DQ6_O, |
---|
552 | DQ6_I => DQ6_I, |
---|
553 | |
---|
554 | DQ7_T => DQ7_T, |
---|
555 | DQ7_O => DQ7_O, |
---|
556 | DQ7_I => DQ7_I, |
---|
557 | -- MAP USER PORTS ABOVE THIS LINE ------------------ |
---|
558 | |
---|
559 | Bus2IP_Clk => iBus2IP_Clk, |
---|
560 | Bus2IP_Reset => iBus2IP_Reset, |
---|
561 | Bus2IP_Addr => iBus2IP_Addr, |
---|
562 | Bus2IP_Data => uBus2IP_Data, |
---|
563 | Bus2IP_BE => uBus2IP_BE, |
---|
564 | Bus2IP_RNW => iBus2IP_RNW, |
---|
565 | Bus2IP_CS => uBus2IP_CS, |
---|
566 | Bus2IP_RdCE => uBus2IP_RdCE, |
---|
567 | Bus2IP_WrCE => uBus2IP_WrCE, |
---|
568 | IP2Bus_Data => uIP2Bus_Data, |
---|
569 | IP2Bus_Ack => iIP2Bus_Ack, |
---|
570 | IP2Bus_Retry => iIP2Bus_Retry, |
---|
571 | IP2Bus_Error => iIP2Bus_Error, |
---|
572 | IP2Bus_ToutSup => iIP2Bus_ToutSup, |
---|
573 | IP2Bus_PostedWrInh => uIP2Bus_PostedWrInh |
---|
574 | ); |
---|
575 | |
---|
576 | ------------------------------------------ |
---|
577 | -- hooking up signal slicing |
---|
578 | ------------------------------------------ |
---|
579 | uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1); |
---|
580 | uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1); |
---|
581 | uBus2IP_CS <= iBus2IP_CS(USER00_CS_INDEX to USER00_CS_INDEX+USER_NUM_CS-1); |
---|
582 | uBus2IP_RdCE <= iBus2IP_RdCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1); |
---|
583 | uBus2IP_WrCE <= iBus2IP_WrCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1); |
---|
584 | iIP2Bus_PostedWrInh <= (others => uIP2Bus_PostedWrInh); |
---|
585 | iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data; |
---|
586 | |
---|
587 | end IMP; |
---|