1 | ## Copyright (c) 2004 Xilinx, Inc. All Rights Reserved.
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2 | ## You may copy and modify these files for your own internal use solely with
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3 | ## Xilinx programmable logic devices and Xilinx EDK system or create IP
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4 | ## modules solely for Xilinx programmable logic devices and Xilinx EDK system.
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5 | ## No rights are granted to distribute any files unless they are distributed in
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6 | ## Xilinx programmable logic devices.
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7 | ###################################################################
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8 | ##
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9 | ## Name : ourspi
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10 | ## Desc : Microprocessor Peripheral Description
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11 | ## : Automatically generated by PsfUtility
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12 | ##
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13 | ###################################################################
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14 |
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15 | BEGIN ourspi
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16 |
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17 | ## Peripheral Options
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18 | OPTION IPTYPE = PERIPHERAL
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19 | OPTION IMP_NETLIST = TRUE
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20 | OPTION HDL = VERILOG
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21 | OPTION CORE_STATE = ACTIVE
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22 | OPTION IP_GROUP = MICROBLAZE:PPC:USER
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23 | OPTION STYLE = MIX
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24 | OPTION RUN_NGCBUILD = TRUE
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25 |
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26 |
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27 | ## Bus Interfaces
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28 | BUS_INTERFACE BUS = SOPB, BUS_TYPE = SLAVE, BUS_STD = OPB
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29 |
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30 | ## Generics for VHDL or Parameters for Verilog
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31 | PARAMETER C_BASEADDR = 0x80000000, BUS = SOPB, ADDRESS = BASE, PAIR = C_HIGHADDR, MIN_SIZE = 0x100
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32 | PARAMETER C_HIGHADDR = 0x800000ff, BUS = SOPB, ADDRESS = HIGH, PAIR = C_BASEADDR
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33 |
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34 | ## Ports
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35 | PORT OPB_Clk = "", DIR = I, BUS = SOPB
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36 | PORT rst = OPB_Rst, DIR = I, BUS = SOPB
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37 | PORT opb_abus = OPB_ABus, DIR = I, VEC = [31:0], BUS = SOPB
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38 | PORT opb_be = OPB_BE, DIR = I, VEC = [3:0], BUS = SOPB
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39 | PORT opb_dbus = OPB_DBus, DIR = I, VEC = [31:0], BUS = SOPB
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40 | PORT opb_rnw = OPB_RNW, DIR = I, BUS = SOPB
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41 | PORT opb_select = OPB_select, DIR = I, BUS = SOPB
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42 | PORT opb_seqaddr = OPB_seqAddr, DIR = I, BUS = SOPB
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43 | PORT sl_dbus = Sl_DBus, DIR = O, VEC = [31:0], BUS = SOPB
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44 | PORT sl_errack = Sl_errAck, DIR = O, BUS = SOPB
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45 | PORT sl_retry = Sl_retry, DIR = O, BUS = SOPB
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46 | PORT sl_toutsup = Sl_toutSup, DIR = O, BUS = SOPB
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47 | PORT sl_xferack = Sl_xferAck, DIR = O, BUS = SOPB
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48 | PORT radio1_sclk = "", DIR = O
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49 | PORT radio1_dout = "", DIR = O
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50 | PORT radio1_cs = "", DIR = O
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51 | PORT radio2_sclk = "", DIR = O
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52 | PORT radio2_dout = "", DIR = O
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53 | PORT radio2_cs = "", DIR = O
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54 | PORT radio3_sclk = "", DIR = O
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55 | PORT radio3_dout = "", DIR = O
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56 | PORT radio3_cs = "", DIR = O
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57 | PORT radio4_sclk = "", DIR = O
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58 | PORT radio4_dout = "", DIR = O
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59 | PORT radio4_cs = "", DIR = O
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60 | PORT dac1_sclk = "", DIR = O
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61 | PORT dac1_dout = "", DIR = O
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62 | PORT dac1_cs = "", DIR = O
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63 | PORT dac2_sclk = "", DIR = O
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64 | PORT dac2_dout = "", DIR = O
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65 | PORT dac2_cs = "", DIR = O
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66 | PORT dac3_sclk = "", DIR = O
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67 | PORT dac3_dout = "", DIR = O
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68 | PORT dac3_cs = "", DIR = O
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69 | PORT dac4_sclk = "", DIR = O
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70 | PORT dac4_dout = "", DIR = O
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71 | PORT dac4_cs = "", DIR = O
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72 |
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73 | END
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