source: PlatformSupport/Deprecated/pcores/SPI_Controller/data/ourspi_v2_1_0.pao

Last change on this file was 35, checked in by snovich, 19 years ago

Working new radio controller and working spi controller
File size: 1.5 KB
Line 
1##############################################################################
2##
3## ***************************************************************************
4## **                                                                       **
5## ** Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.            **
6## **                                                                       **
7## ** You may copy and modify these files for your own internal use solely  **
8## ** with Xilinx programmable logic devices and Xilinx EDK system or       **
9## ** create IP modules solely for Xilinx programmable logic devices and    **
10## ** Xilinx EDK system. No rights are granted to distribute any files      **
11## ** unless they are distributed in Xilinx programmable logic devices.     **
12## **                                                                       **
13## ***************************************************************************
14##
15##############################################################################
16## Filename:          C:\edk_user_repository\MyProcessorIPLib\pcores\ourspi\data\ourspi_v2_1_0.pao
17## Description:       Peripheral Analysis Order
18## Date:              Wed Jun 22 10:30:03 2005 (by Create and Import Peripheral Wizard)
19##############################################################################
20
21lib ourspi opb2wb_shell verilog
22lib ourspi spi_clgen verilog
23lib ourspi spi_defines verilog
24lib ourspi spi_shift verilog
25lib ourspi timescale verilog
26lib ourspi spi_top verilog
27lib ourspi ourspi verilog
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