source: PlatformSupport/Deprecated/pcores/SPI_Controller/hdl/verilog/spi_defines.v

Last change on this file was 35, checked in by snovich, 19 years ago

Working new radio controller and working spi controller
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1//////////////////////////////////////////////////////////////////////
2////                                                              ////
3////  spi_define.v                                                ////
4////                                                              ////
5////  This file is part of the SPI IP core project                ////
6////  http://www.opencores.org/projects/spi/                      ////
7////                                                              ////
8////  Author(s):                                                  ////
9////      - Simon Srot (simons@opencores.org)                     ////
10////                                                              ////
11////  All additional information is avaliable in the Readme.txt   ////
12////  file.                                                       ////
13////                                                              ////
14//////////////////////////////////////////////////////////////////////
15////                                                              ////
16//// Copyright (C) 2002 Authors                                   ////
17////                                                              ////
18//// This source file may be used and distributed without         ////
19//// restriction provided that this copyright statement is not    ////
20//// removed from the file and that any derivative work contains  ////
21//// the original copyright notice and the associated disclaimer. ////
22////                                                              ////
23//// This source file is free software; you can redistribute it   ////
24//// and/or modify it under the terms of the GNU Lesser General   ////
25//// Public License as published by the Free Software Foundation; ////
26//// either version 2.1 of the License, or (at your option) any   ////
27//// later version.                                               ////
28////                                                              ////
29//// This source is distributed in the hope that it will be       ////
30//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32//// PURPOSE.  See the GNU Lesser General Public License for more ////
33//// details.                                                     ////
34////                                                              ////
35//// You should have received a copy of the GNU Lesser General    ////
36//// Public License along with this source; if not, download it   ////
37//// from http://www.opencores.org/lgpl.shtml                     ////
38////                                                              ////
39//////////////////////////////////////////////////////////////////////
40
41//
42// Number of bits used for devider register. If used in system with
43// low frequency of system clock this can be reduced.
44// Use SPI_DIVIDER_LEN for fine tuning theexact number.
45//
46`define SPI_DIVIDER_LEN_8
47//`define SPI_DIVIDER_LEN_16
48//`define SPI_DIVIDER_LEN_24
49//`define SPI_DIVIDER_LEN_32
50
51`ifdef SPI_DIVIDER_LEN_8
52//  `define SPI_DIVIDER_LEN       8    // Can be set from 1 to 8
53  `define SPI_DIVIDER_LEN       1    // Can be set from 1 to 8
54`endif                                                         
55`ifdef SPI_DIVIDER_LEN_16                                       
56  `define SPI_DIVIDER_LEN       16   // Can be set from 9 to 16
57`endif                                                         
58`ifdef SPI_DIVIDER_LEN_24                                       
59  `define SPI_DIVIDER_LEN       24   // Can be set from 17 to 24
60`endif                                                         
61`ifdef SPI_DIVIDER_LEN_32                                       
62  `define SPI_DIVIDER_LEN       32   // Can be set from 25 to 32
63`endif
64
65//
66// Maximum nuber of bits that can be send/received at once.
67// Use SPI_MAX_CHAR for fine tuning the exact number, when using
68// SPI_MAX_CHAR_32, SPI_MAX_CHAR_24, SPI_MAX_CHAR_16, SPI_MAX_CHAR_8.
69//
70//`define SPI_MAX_CHAR_128
71//`define SPI_MAX_CHAR_64
72//`define SPI_MAX_CHAR_32
73`define SPI_MAX_CHAR_24
74//`define SPI_MAX_CHAR_16
75//`define SPI_MAX_CHAR_8
76
77`ifdef SPI_MAX_CHAR_128
78  `define SPI_MAX_CHAR          128  // Can only be set to 128
79  `define SPI_CHAR_LEN_BITS     7
80`endif
81`ifdef SPI_MAX_CHAR_64
82  `define SPI_MAX_CHAR          64   // Can only be set to 64
83  `define SPI_CHAR_LEN_BITS     6
84`endif
85`ifdef SPI_MAX_CHAR_32
86  `define SPI_MAX_CHAR          32   // Can be set from 25 to 32
87  `define SPI_CHAR_LEN_BITS     5
88`endif
89`ifdef SPI_MAX_CHAR_24
90//  `define SPI_MAX_CHAR          24   // Can be set from 17 to 24
91  `define SPI_MAX_CHAR          18   // Can be set from 17 to 24
92  `define SPI_CHAR_LEN_BITS     5
93`endif
94`ifdef SPI_MAX_CHAR_16
95  `define SPI_MAX_CHAR          16   // Can be set from 9 to 16
96  `define SPI_CHAR_LEN_BITS     4
97`endif
98`ifdef SPI_MAX_CHAR_8
99  `define SPI_MAX_CHAR          8    // Can be set from 1 to 8
100  `define SPI_CHAR_LEN_BITS     3
101`endif
102
103//
104// Number of device select signals. Use SPI_SS_NB for fine tuning the
105// exact number.
106//
107`define SPI_SS_NB_8
108//`define SPI_SS_NB_16
109//`define SPI_SS_NB_24
110//`define SPI_SS_NB_32
111
112`ifdef SPI_SS_NB_8
113//  `define SPI_SS_NB             8    // Can be set from 1 to 8
114  `define SPI_SS_NB             8    // Can be set from 1 to 8
115`endif
116`ifdef SPI_SS_NB_16
117  `define SPI_SS_NB             16   // Can be set from 9 to 16
118`endif
119`ifdef SPI_SS_NB_24
120  `define SPI_SS_NB             24   // Can be set from 17 to 24
121`endif
122`ifdef SPI_SS_NB_32
123  `define SPI_SS_NB             32   // Can be set from 25 to 32
124`endif
125
126//
127// Bits of WISHBONE address used for partial decoding of SPI registers.
128//
129`define SPI_OFS_BITS              4:2
130
131//
132// Register offset
133//
134`define SPI_RX_0                0
135`define SPI_RX_1                1
136`define SPI_RX_2                2
137`define SPI_RX_3                3
138`define SPI_TX_0                0
139`define SPI_TX_1                1
140`define SPI_TX_2                2
141`define SPI_TX_3                3
142`define SPI_CTRL                4
143`define SPI_DEVIDE              5
144`define SPI_SS                  6
145
146//
147// Number of bits in ctrl register
148//
149`define SPI_CTRL_BIT_NB         14
150
151//
152// Control register bit position
153//
154`define SPI_CTRL_ASS            13
155`define SPI_CTRL_IE             12
156`define SPI_CTRL_LSB            11
157`define SPI_CTRL_TX_NEGEDGE     10
158`define SPI_CTRL_RX_NEGEDGE     9
159`define SPI_CTRL_GO             8
160`define SPI_CTRL_RES_1          7
161`define SPI_CTRL_CHAR_LEN       6:0
162
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