1 | ////////////////////////////////////////////////////////////////////// |
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2 | //// //// |
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3 | //// spi_top.v //// |
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4 | //// //// |
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5 | //// This file is part of the SPI IP core project //// |
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6 | //// http://www.opencores.org/projects/spi/ //// |
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7 | //// //// |
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8 | //// Author(s): //// |
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9 | //// - Simon Srot (simons@opencores.org) //// |
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10 | //// //// |
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11 | //// All additional information is avaliable in the Readme.txt //// |
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12 | //// file. //// |
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13 | //// //// |
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14 | ////////////////////////////////////////////////////////////////////// |
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15 | //// //// |
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16 | //// Copyright (C) 2002 Authors //// |
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17 | //// //// |
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18 | //// This source file may be used and distributed without //// |
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19 | //// restriction provided that this copyright statement is not //// |
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20 | //// removed from the file and that any derivative work contains //// |
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21 | //// the original copyright notice and the associated disclaimer. //// |
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22 | //// //// |
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23 | //// This source file is free software; you can redistribute it //// |
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24 | //// and/or modify it under the terms of the GNU Lesser General //// |
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25 | //// Public License as published by the Free Software Foundation; //// |
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26 | //// either version 2.1 of the License, or (at your option) any //// |
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27 | //// later version. //// |
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28 | //// //// |
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29 | //// This source is distributed in the hope that it will be //// |
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30 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
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31 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
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32 | //// PURPOSE. See the GNU Lesser General Public License for more //// |
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33 | //// details. //// |
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34 | //// //// |
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35 | //// You should have received a copy of the GNU Lesser General //// |
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36 | //// Public License along with this source; if not, download it //// |
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37 | //// from http://www.opencores.org/lgpl.shtml //// |
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38 | //// //// |
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39 | ////////////////////////////////////////////////////////////////////// |
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40 | |
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41 | |
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42 | `include "spi_defines.v" |
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43 | |
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44 | module spi_top |
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45 | ( |
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46 | // Wishbone signals |
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47 | wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_sel_i, |
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48 | wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_err_o, wb_int_o, |
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49 | |
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50 | // SPI signals |
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51 | ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i |
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52 | ); |
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53 | |
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54 | parameter Tp = 1; |
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55 | |
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56 | |
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57 | |
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58 | // Wishbone signals |
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59 | input wb_clk_i; // master clock input |
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60 | input wb_rst_i; // synchronous active high reset |
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61 | input [31:0] wb_adr_i; // lower address bits |
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62 | input [32-1:0] wb_dat_i; // databus input |
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63 | output [32-1:0] wb_dat_o; // databus output |
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64 | input [3:0] wb_sel_i; // byte select inputs |
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65 | input wb_we_i; // write enable input |
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66 | input wb_stb_i; // stobe/core select signal |
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67 | input wb_cyc_i; // valid bus cycle input |
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68 | output wb_ack_o; // bus cycle acknowledge output |
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69 | output wb_err_o; // termination w/ error |
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70 | output wb_int_o; // interrupt request signal output |
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71 | |
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72 | // SPI signals |
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73 | output [`SPI_SS_NB-1:0] ss_pad_o; // slave select |
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74 | output sclk_pad_o; // serial clock |
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75 | output mosi_pad_o; // master out slave in |
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76 | input miso_pad_i; // master in slave out |
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77 | |
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78 | reg [32-1:0] wb_dat_o; |
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79 | reg wb_ack_o; |
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80 | reg wb_int_o; |
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81 | |
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82 | // Internal signals |
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83 | reg [`SPI_DIVIDER_LEN-1:0] divider; // Divider register |
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84 | reg [`SPI_CTRL_BIT_NB-1:0] ctrl; // Control and status register |
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85 | reg [`SPI_SS_NB-1:0] ss; // Slave select register |
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86 | reg [32-1:0] wb_dat; // wb data out |
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87 | wire [`SPI_MAX_CHAR-1:0] rx; // Rx register |
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88 | wire rx_negedge; // miso is sampled on negative edge |
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89 | wire tx_negedge; // mosi is driven on negative edge |
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90 | wire [`SPI_CHAR_LEN_BITS-1:0] char_len; // char len |
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91 | wire go; // go |
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92 | wire lsb; // lsb first on line |
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93 | wire ie; // interrupt enable |
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94 | wire ass; // automatic slave select |
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95 | wire spi_divider_sel; // divider register select |
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96 | wire spi_ctrl_sel; // ctrl register select |
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97 | wire [3:0] spi_tx_sel; // tx_l register select |
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98 | wire spi_ss_sel; // ss register select |
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99 | wire tip; // transfer in progress |
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100 | wire pos_edge; // recognize posedge of sclk |
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101 | wire neg_edge; // recognize negedge of sclk |
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102 | wire last_bit; // marks last character bit |
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103 | |
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104 | // Address decoder |
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105 | assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_DEVIDE); |
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106 | assign spi_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_CTRL); |
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107 | assign spi_tx_sel[0] = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_0); |
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108 | assign spi_tx_sel[1] = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_1); |
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109 | assign spi_tx_sel[2] = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_2); |
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110 | assign spi_tx_sel[3] = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_3); |
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111 | assign spi_ss_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_SS); |
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112 | |
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113 | // Read from registers |
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114 | always @(wb_adr_i[`SPI_OFS_BITS] or rx or ctrl or divider or ss) |
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115 | begin |
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116 | case (wb_adr_i[`SPI_OFS_BITS]) |
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117 | `ifdef SPI_MAX_CHAR_128 |
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118 | `SPI_RX_0: wb_dat = rx[31:0]; |
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119 | `SPI_RX_1: wb_dat = rx[63:32]; |
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120 | `SPI_RX_2: wb_dat = rx[95:64]; |
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121 | `SPI_RX_3: wb_dat = {{128-`SPI_MAX_CHAR{1'b0}}, rx[`SPI_MAX_CHAR-1:96]}; |
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122 | `else |
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123 | `ifdef SPI_MAX_CHAR_64 |
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124 | `SPI_RX_0: wb_dat = rx[31:0]; |
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125 | `SPI_RX_1: wb_dat = {{64-`SPI_MAX_CHAR{1'b0}}, rx[`SPI_MAX_CHAR-1:32]}; |
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126 | `SPI_RX_2: wb_dat = 32'b0; |
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127 | `SPI_RX_3: wb_dat = 32'b0; |
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128 | `else |
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129 | `SPI_RX_0: wb_dat = {{32-`SPI_MAX_CHAR{1'b0}}, rx[`SPI_MAX_CHAR-1:0]}; |
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130 | `SPI_RX_1: wb_dat = 32'b0; |
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131 | `SPI_RX_2: wb_dat = 32'b0; |
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132 | `SPI_RX_3: wb_dat = 32'b0; |
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133 | `endif |
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134 | `endif |
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135 | `SPI_CTRL: wb_dat = {{32-`SPI_CTRL_BIT_NB{1'b0}}, ctrl}; |
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136 | `SPI_DEVIDE: wb_dat = {{32-`SPI_DIVIDER_LEN{1'b0}}, divider}; |
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137 | `SPI_SS: wb_dat = {{32-`SPI_SS_NB{1'b0}}, ss}; |
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138 | default: wb_dat = 32'bx; |
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139 | endcase |
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140 | end |
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141 | |
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142 | // Wb data out |
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143 | always @(posedge wb_clk_i or posedge wb_rst_i) |
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144 | begin |
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145 | if (wb_rst_i) |
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146 | wb_dat_o <= #Tp 32'b0; |
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147 | else |
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148 | wb_dat_o <= #Tp wb_dat; |
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149 | end |
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150 | |
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151 | // Wb acknowledge |
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152 | always @(posedge wb_clk_i or posedge wb_rst_i) |
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153 | begin |
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154 | if (wb_rst_i) |
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155 | wb_ack_o <= #Tp 1'b0; |
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156 | else |
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157 | wb_ack_o <= #Tp wb_cyc_i & wb_stb_i & ~wb_ack_o; |
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158 | end |
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159 | |
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160 | // Wb error |
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161 | assign wb_err_o = 1'b0; |
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162 | |
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163 | // Interrupt |
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164 | always @(posedge wb_clk_i or posedge wb_rst_i) |
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165 | begin |
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166 | if (wb_rst_i) |
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167 | wb_int_o <= #Tp 1'b0; |
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168 | else if (ie && tip && last_bit && pos_edge) |
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169 | wb_int_o <= #Tp 1'b1; |
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170 | else if (wb_ack_o) |
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171 | wb_int_o <= #Tp 1'b0; |
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172 | end |
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173 | |
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174 | // Divider register |
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175 | always @(posedge wb_clk_i or posedge wb_rst_i) |
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176 | begin |
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177 | if (wb_rst_i) |
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178 | divider <= #Tp {`SPI_DIVIDER_LEN{1'b0}}; |
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179 | else if (spi_divider_sel && wb_we_i && !tip) |
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180 | begin |
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181 | `ifdef SPI_DIVIDER_LEN_8 |
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182 | if (wb_sel_i[0]) |
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183 | divider <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:0]; |
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184 | `endif |
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185 | `ifdef SPI_DIVIDER_LEN_16 |
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186 | if (wb_sel_i[0]) |
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187 | divider[7:0] <= #Tp wb_dat_i[7:0]; |
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188 | if (wb_sel_i[1]) |
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189 | divider[`SPI_DIVIDER_LEN-1:8] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:8]; |
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190 | `endif |
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191 | `ifdef SPI_DIVIDER_LEN_24 |
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192 | if (wb_sel_i[0]) |
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193 | divider[7:0] <= #Tp wb_dat_i[7:0]; |
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194 | if (wb_sel_i[1]) |
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195 | divider[15:8] <= #Tp wb_dat_i[15:8]; |
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196 | if (wb_sel_i[2]) |
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197 | divider[`SPI_DIVIDER_LEN-1:16] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:16]; |
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198 | `endif |
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199 | `ifdef SPI_DIVIDER_LEN_32 |
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200 | if (wb_sel_i[0]) |
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201 | divider[7:0] <= #Tp wb_dat_i[7:0]; |
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202 | if (wb_sel_i[1]) |
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203 | divider[15:8] <= #Tp wb_dat_i[15:8]; |
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204 | if (wb_sel_i[2]) |
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205 | divider[23:16] <= #Tp wb_dat_i[23:16]; |
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206 | if (wb_sel_i[3]) |
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207 | divider[`SPI_DIVIDER_LEN-1:24] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:24]; |
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208 | `endif |
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209 | end |
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210 | end |
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211 | |
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212 | // Ctrl register |
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213 | always @(posedge wb_clk_i or posedge wb_rst_i) |
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214 | begin |
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215 | if (wb_rst_i) |
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216 | ctrl <= #Tp {`SPI_CTRL_BIT_NB{1'b0}}; |
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217 | else if(spi_ctrl_sel && wb_we_i && !tip) |
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218 | begin |
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219 | if (wb_sel_i[0]) |
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220 | ctrl[7:0] <= #Tp wb_dat_i[7:0] | {7'b0, ctrl[0]}; |
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221 | if (wb_sel_i[1]) |
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222 | ctrl[`SPI_CTRL_BIT_NB-1:8] <= #Tp wb_dat_i[`SPI_CTRL_BIT_NB-1:8]; |
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223 | end |
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224 | else if(tip && last_bit && pos_edge) |
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225 | ctrl[`SPI_CTRL_GO] <= #Tp 1'b0; |
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226 | end |
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227 | |
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228 | assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE]; |
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229 | assign tx_negedge = ctrl[`SPI_CTRL_TX_NEGEDGE]; |
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230 | assign go = ctrl[`SPI_CTRL_GO]; |
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231 | assign char_len = ctrl[`SPI_CTRL_CHAR_LEN]; |
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232 | assign lsb = ctrl[`SPI_CTRL_LSB]; |
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233 | assign ie = ctrl[`SPI_CTRL_IE]; |
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234 | assign ass = ctrl[`SPI_CTRL_ASS]; |
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235 | |
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236 | // Slave select register |
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237 | always @(posedge wb_clk_i or posedge wb_rst_i) |
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238 | begin |
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239 | if (wb_rst_i) |
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240 | ss <= #Tp {`SPI_SS_NB{1'b0}}; |
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241 | else if(spi_ss_sel && wb_we_i && !tip) |
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242 | begin |
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243 | `ifdef SPI_SS_NB_8 |
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244 | if (wb_sel_i[0]) |
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245 | ss <= #Tp wb_dat_i[`SPI_SS_NB-1:0]; |
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246 | `endif |
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247 | `ifdef SPI_SS_NB_16 |
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248 | if (wb_sel_i[0]) |
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249 | ss[7:0] <= #Tp wb_dat_i[7:0]; |
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250 | if (wb_sel_i[1]) |
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251 | ss[`SPI_SS_NB-1:8] <= #Tp wb_dat_i[`SPI_SS_NB-1:8]; |
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252 | `endif |
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253 | `ifdef SPI_SS_NB_24 |
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254 | if (wb_sel_i[0]) |
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255 | ss[7:0] <= #Tp wb_dat_i[7:0]; |
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256 | if (wb_sel_i[1]) |
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257 | ss[15:8] <= #Tp wb_dat_i[15:8]; |
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258 | if (wb_sel_i[2]) |
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259 | ss[`SPI_SS_NB-1:16] <= #Tp wb_dat_i[`SPI_SS_NB-1:16]; |
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260 | `endif |
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261 | `ifdef SPI_SS_NB_32 |
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262 | if (wb_sel_i[0]) |
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263 | ss[7:0] <= #Tp wb_dat_i[7:0]; |
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264 | if (wb_sel_i[1]) |
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265 | ss[15:8] <= #Tp wb_dat_i[15:8]; |
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266 | if (wb_sel_i[2]) |
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267 | ss[23:16] <= #Tp wb_dat_i[23:16]; |
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268 | if (wb_sel_i[3]) |
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269 | ss[`SPI_SS_NB-1:24] <= #Tp wb_dat_i[`SPI_SS_NB-1:24]; |
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270 | `endif |
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271 | end |
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272 | end |
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273 | |
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274 | assign ss_pad_o = ~((ss & {`SPI_SS_NB{tip & ass}}) | (ss & {`SPI_SS_NB{!ass}})); |
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275 | |
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276 | spi_clgen clgen (.clk_in(wb_clk_i), .rst(wb_rst_i), .go(go), .enable(tip), .last_clk(last_bit), |
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277 | .divider(divider), .clk_out(sclk_pad_o), .pos_edge(pos_edge), |
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278 | .neg_edge(neg_edge)); |
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279 | |
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280 | spi_shift shift (.clk(wb_clk_i), .rst(wb_rst_i), .len(char_len[`SPI_CHAR_LEN_BITS-1:0]), |
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281 | .latch(spi_tx_sel[3:0] & {4{wb_we_i}}), .byte_sel(wb_sel_i), .lsb(lsb), |
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282 | .go(go), .pos_edge(pos_edge), .neg_edge(neg_edge), |
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283 | .rx_negedge(rx_negedge), .tx_negedge(tx_negedge), |
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284 | .tip(tip), .last(last_bit), |
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285 | .p_in(wb_dat_i), .p_out(rx), |
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286 | .s_clk(sclk_pad_o), .s_in(miso_pad_i), .s_out(mosi_pad_o)); |
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287 | endmodule |
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288 | |
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