1 | ###################################################################
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2 | ##
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3 | ## Name : clock_board_config
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4 | ## Desc : Microprocessor Peripheral Description
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5 | ## : Automatically generated by PsfUtility
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6 | ##
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7 | ###################################################################
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8 |
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9 | BEGIN clock_board_config
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10 |
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11 | ## Peripheral Options
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12 | OPTION IPTYPE = PERIPHERAL
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13 | OPTION IMP_NETLIST = TRUE
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14 | OPTION HDL = VERILOG
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15 | OPTION ARCH_SUPPORT_MAP = (virtex2p=PREFERRED, virtex4=PREFERRED, others=AVAILABLE)
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16 | OPTION IP_GROUP = USER
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17 | OPTION USAGE_LEVEL = BASE_USER
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18 |
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19 | IO_INTERFACE IO_IF = CLKBRDCONFIG, IO_TYPE = WARP_CLKBRD_CONFIG_V1
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20 |
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21 | ## Bus Interfaces
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22 | # This core is not attached to any busses
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23 |
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24 | ## Generics for VHDL or Parameters for Verilog
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25 |
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26 | #platgen will infer these hex values and defparam them in the Verilog like "defparam clkbrdconfig_0.fpga_radio_clk_source = 'h1AFF;"
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27 | #since they're 16 bits anyway, the ambiguous bit length in the defparam'd value is no problem
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28 | PARAMETER fpga_radio_clk_source = 0x1AFF, DT = std_logic_vector, DESC = Selects radio reference clock source, VALUES = (0x1AFF=Oscillator, 0x1DFF=External Coax), PERMIT = BASE_USER
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29 | PARAMETER fpga_logic_clk_source = 0x1AFF, DT = std_logic_vector, DESC = Selects FPGA/sampling clock source, VALUES = (0x1AFF=Oscillator, 0x1DFF=External Coax), PERMIT = BASE_USER
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30 |
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31 | # Parameters controlling en/disable on radio reference clk outputs
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32 | # 0x01ff disables the corresponding output
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33 | # 0x1eff enables the corresponding ouptput
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34 | # By default, outputs for slots 2 and 3 are enabled, matching
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35 | # the hardware config for a WARP MIMO kit
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36 | PARAMETER radio_clk_out0_mode = 0x01ff, DT = std_logic_vector, DESC = Selects whether to enable or disable the radio reference clock for slot 1 - disabled by default, VALUES = (0x01ff=Disabled, 0x1eff=Enabled), PERMIT = BASE_USER
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37 | PARAMETER radio_clk_out1_mode = 0x1eff, DT = std_logic_vector, DESC = Selects whether to enable or disable the radio reference clock for slot 2 - disabled by default, VALUES = (0x01ff=Disabled, 0x1eff=Enabled), PERMIT = BASE_USER
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38 | PARAMETER radio_clk_out2_mode = 0x1eff, DT = std_logic_vector, DESC = Selects whether to enable or disable the radio reference clock for slot 2 - disabled by default, VALUES = (0x01ff=Disabled, 0x1eff=Enabled), PERMIT = BASE_USER
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39 | PARAMETER radio_clk_out3_mode = 0x01ff, DT = std_logic_vector, DESC = Selects whether to enable or disable the radio reference clock for slot 4 - disabled by default, VALUES = (0x01ff=Disabled, 0x1eff=Enabled), PERMIT = BASE_USER
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40 |
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41 | # Parameters controlling en/disable on radio sampling clk outputs
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42 | # 0x02ff disables the corresponding output
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43 | # 0x04ff enables the corresponding output with min (340mV) drive
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44 | # 0x08ff enables the corresponding output with max (810mV) drive
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45 | # By default, outputs for slots 2 and 3 are enabled, matching
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46 | # the hardware config for a WARP MIMO kit
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47 | PARAMETER logic_clk_out0_mode = 0x02ff, DT = std_logic_vector, DESC = Selects whether to enable or disable the sampling clock for slot 1 - disabled by default, VALUES = (0x02ff=Disabled, 0x04ff=Enabled - 340mV drive, 0x08ff=Enabled - 810mV drive), PERMIT = BASE_USER
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48 | PARAMETER logic_clk_out1_mode = 0x08ff, DT = std_logic_vector, DESC = Selects whether to enable or disable the sampling clock for slot 2 - 810mV drive by default, VALUES = (0x02ff=Disabled, 0x04ff=Enabled - 340mV drive, 0x08ff=Enabled - 810mV drive), PERMIT = BASE_USER
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49 | PARAMETER logic_clk_out2_mode = 0x08ff, DT = std_logic_vector, DESC = Selects whether to enable or disable the sampling clock for slot 3 - 810mV drive by default, VALUES = (0x02ff=Disabled, 0x04ff=Enabled - 340mV drive, 0x08ff=Enabled - 810mV drive), PERMIT = BASE_USER
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50 | PARAMETER logic_clk_out3_mode = 0x02ff, DT = std_logic_vector, DESC = Selects whether to enable or disable the sampling clock for slot 4 - disabled by default, VALUES = (0x02ff=Disabled, 0x04ff=Enabled - 340mV drive, 0x08ff=Enabled - 810mV drive), PERMIT = BASE_USER
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51 |
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52 |
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53 | PARAMETER sys_clk_freq_hz = 0x05f5e100, DT = std_logic_vector, DESC = Frequency of clock at sys_clk input, VALUES = (0x05f5e100=100MHz, 0x1F78A40=33MHz), PERMIT = BASE_USER
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54 | PARAMETER scp_min_freq_hz = 0x002625a0, DT = std_logic_vector, DESC = Minimum serial I/O frequency, VALUES = (0x002625a0=25MHz), PERMIT = BASE_USER
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55 |
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56 | PARAMETER scp_cyc_leng_a = 0x00000028, DT = std_logic_vector, DESC = Length of serial I/O write cycle, VALUES = (0x00000028=40), PERMIT = BASE_USER
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57 | PARAMETER scp_cyc_leng_b = 0x00000028, DT = std_logic_vector, DESC = Length of serial I/O write cycle, VALUES = (0x00000028=40), PERMIT = BASE_USER
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58 | PARAMETER scp_cyc_leng = 0x00000028, DT = std_logic_vector, DESC = Length of serial I/O write cycle, VALUES = (0x00000028=40), PERMIT = BASE_USER
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59 |
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60 | ## Ports
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61 | PORT sys_clk = "", DIR = I, SIGIS = CLK
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62 | PORT sys_rst = "net_gnd", DIR = I, SIGIS = RST
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63 | PORT cfg_radio_dat_out = "", DIR = O
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64 | PORT cfg_radio_csb_out = "", DIR = O
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65 | PORT cfg_radio_en_out = "", DIR = O
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66 | PORT cfg_radio_clk_out = "", DIR = O
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67 | PORT cfg_logic_dat_out = "", DIR = O
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68 | PORT cfg_logic_csb_out = "", DIR = O
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69 | PORT cfg_logic_en_out = "", DIR = O
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70 | PORT cfg_logic_clk_out = "", DIR = O
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71 |
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72 | PORT config_invalid = "", DIR = O
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73 |
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74 | END
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