1 | // The two clocks fed to the FPGA over the clock board |
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2 | // header orginate in the AD9510 that supplied A/D and |
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3 | // D/A (logic) clocks. OUT5 supplies the two series |
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4 | // terminated CMOS outputs, while OUT4 supplies the LVDS |
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5 | // outputs that are (should be) parallel terminated at |
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6 | // the inputs of the FPGA. |
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7 | // |
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8 | // To support various operating modes, a variable is |
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9 | // defined to specify the operating modes for OUT4 and |
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10 | // OUT5. |
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11 | // |
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12 | // OUT 5 supplies + and - CMOS outputs (test mode) : 16'h1EFF |
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13 | // OUT 5 supplies + CMOS output only (normal mode) : 16'h0EFF |
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14 | // OUT 5 powered down : 16'h0FFF |
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15 | |
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16 | `define fpga_clk_out5_reg 16'h0EFF |
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17 | |
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18 | // OUT 4 supplies + and - CMOS outputs (test mode) : 16'h1EFF |
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19 | // OUT 4 powered down (normal mode) : 16'h07FF |
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20 | // OUT 4 supplies LVDS outputs : 16'h06FF |
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21 | |
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22 | `define fpga_clk_out4_reg 16'h07FF |
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23 | |
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24 | module clock_board_config ( |
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25 | sys_clk, |
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26 | sys_rst, |
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27 | |
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28 | cfg_radio_dat_out, |
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29 | cfg_radio_csb_out, |
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30 | cfg_radio_en_out, |
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31 | cfg_radio_clk_out, |
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32 | |
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33 | cfg_logic_dat_out, |
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34 | cfg_logic_csb_out, |
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35 | cfg_logic_en_out, |
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36 | cfg_logic_clk_out, |
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37 | |
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38 | config_invalid |
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39 | ); |
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40 | |
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41 | parameter sys_clk_freq_hz = 120000000; |
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42 | |
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43 | // Select the input source for the radio clocks. |
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44 | // CLK source for radio distribution = oscillator : 16'h1AFF |
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45 | // CLK source for radio distribution = external coax : 16'h1DFF |
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46 | parameter fpga_radio_clk_source = 16'h1Aff; |
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47 | |
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48 | // Select the input source for the logic (A/D and D/A) clocks. |
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49 | // CLK source for logic distribution = oscillator : 16'h1AFF |
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50 | // CLK source for logic distribution = external coax : 16'h1DFF |
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51 | parameter fpga_logic_clk_source = 16'h1Aff; |
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52 | |
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53 | // Parameters controlling en/disable on radio reference clk outputs |
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54 | // 0x01ff disables the corresponding output |
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55 | // 0x1eff enables the corresponding ouptput |
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56 | // By default, outputs for slots 2 and 3 are enabled, matching |
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57 | // the hardware config for a WARP MIMO kit |
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58 | parameter radio_clk_out4_mode = 16'h01ff; //J12 |
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59 | parameter radio_clk_out5_mode = 16'h1eff; //J11 (usually radio in slot 3) |
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60 | parameter radio_clk_out6_mode = 16'h1eff; //J10 (usually radio in slot 2) |
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61 | parameter radio_clk_out7_mode = 16'h01ff; //J6 |
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62 | |
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63 | // Parameter controlling whether to enable the off-board output of |
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64 | // the radio reference clock (used for dasiy-chaining clocks) |
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65 | // 0x0BFF is disabled; 0x08FF is enabled |
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66 | parameter radio_clk_forward_out_mode = 16'h0BFF; |
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67 | |
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68 | // Parameters controlling en/disable on radio sampling clk outputs |
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69 | // 0x02ff disables the corresponding output |
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70 | // 0x04ff enables the corresponding output with min (340mV) drive |
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71 | // 0x08ff enables the corresponding output with max (810mV) drive |
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72 | // By default, outputs for slots 2 and 3 are enabled, matching |
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73 | // the hardware config for a WARP MIMO kit |
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74 | parameter logic_clk_out0_mode = 16'h02ff; //J8 |
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75 | parameter logic_clk_out1_mode = 16'h02ff; //J7 |
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76 | parameter logic_clk_out2_mode = 16'h08ff; //J9 (usually radio in slot 3) |
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77 | parameter logic_clk_out3_mode = 16'h08ff; //J13 (usually radio in slot 2) |
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78 | |
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79 | // Parameter controlling whether to enable the off-board output of |
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80 | // the radio sampling clock (used for dasiy-chaining clocks) |
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81 | // 0xh1FFF is disabled; 0xh1EFF is enabled |
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82 | parameter logic_clk_forward_out_mode = 16'h1FFF; |
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83 | |
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84 | input sys_clk; |
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85 | input sys_rst; |
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86 | |
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87 | output cfg_radio_dat_out; reg cfg_radio_dat_out = 1'b1; |
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88 | output cfg_radio_csb_out; reg cfg_radio_csb_out = 1'b1; |
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89 | output cfg_radio_en_out; reg cfg_radio_en_out = 1'b1; |
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90 | output cfg_radio_clk_out; reg cfg_radio_clk_out = 1'b1; |
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91 | |
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92 | output cfg_logic_dat_out; reg cfg_logic_dat_out = 1'b1; |
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93 | output cfg_logic_csb_out; reg cfg_logic_csb_out = 1'b1; |
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94 | output cfg_logic_en_out; reg cfg_logic_en_out = 1'b1; |
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95 | output cfg_logic_clk_out; reg cfg_logic_clk_out = 1'b1; |
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96 | |
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97 | output config_invalid; |
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98 | |
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99 | // SCP_CNT [7:0] increments throughout each clock period |
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100 | // of the AD9510 serial control port (SCP). The absolute |
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101 | // maximum clock frequency for the SCP is 25 MHz, but I'm |
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102 | // limiting it to 12.5 MHz to be conservative. If the |
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103 | // system clock operates at exactly 87.5 MHz, then the |
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104 | // minimum SCP clock period would equal exactly seven |
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105 | // SYS_CLK periods. In this case, SCP_CNT cycles through |
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106 | // seven values -- 0, 1, 2, ..., 6 -- durin each SCP clock |
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107 | // period. The result is an SCP clock period of 80 nsec |
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108 | // (12.5 MHz).. |
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109 | // |
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110 | // SCP_CYC_START and SCP_CYC_MID detect the start and middle |
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111 | // of each SCP cycle, respectively. The assertion of |
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112 | // SCP_CYC_START, when appropriate, causes the SCP clock |
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113 | // to go low. In this state, the assertion of SCP_CYC_MID |
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114 | // causes the SCP clock to return to its high state. |
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115 | |
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116 | parameter scp_min_freq_hz = 2500000; |
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117 | |
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118 | // a : How many SYS_CLK cycles per SCP cycle -- CEIL(X/Y)? |
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119 | // b : Impose a minimum of 2 SYS_CLK cycles per SCP cycle. |
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120 | |
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121 | parameter scp_cyc_leng_a = ((sys_clk_freq_hz + scp_min_freq_hz - 1) / scp_min_freq_hz); |
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122 | parameter scp_cyc_leng_b = (scp_cyc_leng_a < 2) ? 2 : scp_cyc_leng_a; |
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123 | parameter scp_cyc_leng = scp_cyc_leng_b; |
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124 | |
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125 | reg [3:0] scp_cnt_en = 4'b0000; // enable used for graceful power-up |
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126 | reg [7:0] scp_cnt = 8'b00000000; // SCP cycle counter |
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127 | reg scp_cnt_tc = 1'b0; // pulses HIGH during last SCP cycle to reset counter |
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128 | reg scp_cyc_start = 1'b0; // pulses high to denote start of each SCP clock period |
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129 | reg scp_cyc_mid = 1'b0; // pulses high to denote middle of each SCP clock period |
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130 | |
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131 | always @ (posedge sys_clk) |
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132 | begin |
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133 | scp_cnt_en [3:0] <= {1'b1,scp_cnt_en [3:1]}; |
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134 | |
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135 | if (~scp_cnt_en [0]) |
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136 | begin |
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137 | scp_cnt [7:0] <= 8'b00000000; |
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138 | scp_cnt_tc <= 1'b0; |
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139 | scp_cyc_start <= 1'b0; |
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140 | scp_cyc_mid <= 1'b0; |
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141 | end |
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142 | |
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143 | else |
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144 | begin |
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145 | if (~scp_cnt_tc) scp_cnt [7:0] <= scp_cnt [7:0] + 1; |
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146 | else scp_cnt [7:0] <= 8'b00000000; |
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147 | |
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148 | scp_cnt_tc <= (scp_cnt [7:0] == ((scp_cyc_leng + 0) - 2)); |
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149 | scp_cyc_start <= (scp_cnt [7:0] == 0 ); |
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150 | scp_cyc_mid <= (scp_cnt [7:0] == ((scp_cyc_leng + 1) / 2)); |
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151 | end |
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152 | |
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153 | end |
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154 | |
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155 | |
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156 | |
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157 | reg [3:0] sys_rst_lock = 4'b1111; |
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158 | reg [2:0] sys_rst_sync = 3'b111; |
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159 | |
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160 | always @ (posedge sys_clk or posedge sys_rst) |
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161 | begin |
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162 | if (sys_rst) sys_rst_lock [3] <= 1'b1; |
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163 | else sys_rst_lock [3] <= 1'b0; |
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164 | end |
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165 | |
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166 | always @ (posedge sys_clk or posedge sys_rst_lock [3]) |
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167 | begin |
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168 | if (sys_rst_lock [3]) sys_rst_lock [2:0] <= 3'b111; |
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169 | else sys_rst_lock [2:0] <= {1'b0,sys_rst_lock [2:1]}; |
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170 | end |
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171 | |
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172 | always @ (posedge sys_clk) |
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173 | begin |
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174 | sys_rst_sync [2:0] <= {sys_rst_lock [0],sys_rst_sync [2:1]}; |
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175 | end |
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176 | |
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177 | |
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178 | |
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179 | // CFG_CYC [9:0] increments by 1 following each assertion |
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180 | // of SCP_CYC_MID, until it finally "rolls over" to 0. |
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181 | // Coincident with this roll-over is the assertion of |
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182 | // CFG_CYC_DONE, thereby preventing any further increments |
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183 | // to CFG_CYC. The net result?... SCP_CYC_START and |
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184 | // SCP_CYC_MID each pulse high 1024 times while |
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185 | // CFG_CYC_DONE is deasserted (low). After this, |
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186 | // CFG_CYC_START and CFG_CYC_MID continue to pulse, but |
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187 | // CFG_CYC_DONE is asserted to mask of any "events" that |
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188 | // depend upon the START and MID pulses. |
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189 | // |
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190 | // EXAMPLE : SCP_CYC_LENG = 6... |
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191 | // |
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192 | // SYS_CLK : \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ |
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193 | // SCP_CYC_START : 0|0|0|0|0|0|0|0|0|1|0|0|0|0|0|1|0|0|0|0|0|1| ... |0|0|0|1|0|0|0|0|0|1|0|0|0|0|0|1| |
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194 | // SCP_CYC_MID : 0|0|0|0|0|0|0|0|0|0|0|0|1|0|0|0|0|0|1|0|0|0| ... |1|0|0|0|0|0|1|0|0|0|0|0|1|0|0|0| |
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195 | // CFG_CYC : 0 | 1 | 2 ... | 1023 | 0 |
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196 | // CFG_DONE : 0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0| ... |0|0|0|0|0|0|0|1|1|1|1|1|1|1|1|1| |
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197 | // |
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198 | // EXAMPLE : SCP_CYC_LENG = 2... |
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199 | // |
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200 | // Same as in the previous example, except that |
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201 | // SCP_CYC_START and SCP_CYC_MID are alternately pulsing |
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202 | // high and low 180 degrees out of phase with respect to |
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203 | // one another. |
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204 | |
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205 | reg [9:0] cfg_cyc = 10'b0000000000; |
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206 | reg cfg_cyc_done = 1'b1; |
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207 | reg cfg_restart = 1'b0; |
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208 | reg cfg_clk_low = 1'b0; |
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209 | reg cfg_clk_high = 1'b0; |
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210 | |
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211 | reg cfg_cyc_done_d1 = 1'b1; |
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212 | |
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213 | always @ (posedge sys_clk) |
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214 | begin |
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215 | cfg_cyc_done_d1 <= cfg_cyc_done; |
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216 | end |
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217 | |
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218 | |
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219 | |
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220 | always @ (posedge sys_clk) |
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221 | begin |
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222 | |
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223 | if (~scp_cyc_mid) |
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224 | begin |
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225 | cfg_cyc [9:0] <= cfg_cyc [9:0]; |
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226 | cfg_cyc_done <= cfg_cyc_done; |
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227 | end |
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228 | |
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229 | else |
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230 | begin |
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231 | if (cfg_cyc_done) |
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232 | begin |
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233 | cfg_cyc [9:0] <= 10'b0000000000; |
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234 | cfg_cyc_done <= ~cfg_restart; |
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235 | end |
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236 | |
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237 | else |
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238 | begin |
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239 | cfg_cyc [9:0] <= cfg_cyc [9:0] + 1; |
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240 | cfg_cyc_done <= (cfg_cyc [9:0] == 10'b1111111111); |
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241 | end |
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242 | end |
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243 | |
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244 | cfg_restart <= ~cfg_restart & cfg_cyc_done & (sys_rst_sync [1:0] == 2'b01) |
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245 | | cfg_restart & cfg_cyc_done & ~scp_cyc_mid; |
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246 | |
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247 | cfg_clk_low <= ~cfg_cyc_done & scp_cyc_start; |
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248 | cfg_clk_high <= ~cfg_cyc_done & scp_cyc_mid; |
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249 | end |
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250 | |
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251 | |
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252 | |
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253 | // For a given sequence generation register (chain of |
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254 | // SRLs), the SRL having index 0 delivers its data |
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255 | // first, followed by the SRL having index 1. The SRL |
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256 | // having index 63 delivers its data last. Hence the |
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257 | // input of SRL N is fed by the output of SRL N + 1. |
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258 | // The last SRL in each chain is fed with the output |
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259 | // of the first SRL in he chain so that the configuration |
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260 | // may be repeated on demand. |
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261 | // |
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262 | // Two sequence generators are defined, one for the |
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263 | // AD9510 that clocks the radio ICs for up- and down- |
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264 | // conversion, and another that clocks the FPGA and |
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265 | // the radio boards' converters. |
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266 | |
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267 | wire srl_shift; |
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268 | |
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269 | wire [63:0] srl_radio_d; |
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270 | wire [63:0] srl_radio_q; |
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271 | |
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272 | wire [63:0] srl_logic_d; |
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273 | wire [63:0] srl_logic_q; |
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274 | |
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275 | assign srl_shift = cfg_clk_low; |
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276 | assign srl_radio_d [63:0] = {srl_radio_q [0],srl_radio_q [63:1]}; |
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277 | assign srl_logic_d [63:0] = {srl_logic_q [0],srl_logic_q [63:1]}; |
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278 | |
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279 | reg config_invalid = 1'b1; |
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280 | |
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281 | always @(posedge sys_clk) |
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282 | begin |
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283 | if(cfg_cyc_done & ~cfg_cyc_done_d1) |
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284 | config_invalid <= 1'b0; |
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285 | else if(cfg_restart) |
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286 | config_invalid <= 1'b1; |
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287 | end |
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288 | |
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289 | // ALL SRLs in this module are configured for a static |
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290 | // shift length of 16. For a given 16-bit SRL INIT |
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291 | // value, the high order bit will be shifted out first, |
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292 | // while the low order bit will be shifted out last. |
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293 | // It is, therefore, VERY convenient to operate the |
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294 | // AD9510s in MSB first mode. Pros : This is the |
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295 | // default operating mode for the AD9510, and requires |
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296 | // no additional hocus pocus. Cons : Addresses are |
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297 | // decremented as data is written into each device. |
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298 | // This requires an extra control access to address |
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299 | // 5A in order to force the update -- not rocket science, |
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300 | // but very important to remember. See the AD9510 data |
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301 | // sheet, revision A, pages 42 and 43 for details. |
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302 | |
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303 | genvar ii; |
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304 | generate |
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305 | for (ii = 0 ; ii < 64 ; ii = ii + 1) |
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306 | begin : gen_srls |
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307 | |
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308 | SRL16E srl_radio ( |
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309 | .Q (srl_radio_q [ii]), |
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310 | .A0 (1'b1 ), |
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311 | .A1 (1'b1 ), |
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312 | .A2 (1'b1 ), |
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313 | .A3 (1'b1 ), |
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314 | .CE (srl_shift ), |
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315 | .CLK (sys_clk ), |
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316 | .D (srl_radio_d [ii]) |
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317 | ); |
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318 | |
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319 | SRL16E srl_logic ( |
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320 | .Q (srl_logic_q [ii]), |
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321 | .A0 (1'b1 ), |
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322 | .A1 (1'b1 ), |
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323 | .A2 (1'b1 ), |
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324 | .A3 (1'b1 ), |
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325 | .CE (srl_shift ), |
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326 | .CLK (sys_clk ), |
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327 | .D (srl_logic_d [ii]) |
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328 | ); |
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329 | |
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330 | end |
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331 | endgenerate |
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332 | |
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333 | |
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334 | // Here's where we define the register contents |
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335 | // Each "defparam gen_srls" corresponds to one 16 bit SPI transaction |
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336 | |
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337 | // Register contents for the radio reference generator |
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338 | |
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339 | // Leave some emtpy clock cycles at boot to let things settle |
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340 | defparam gen_srls[ 0].srl_radio.INIT = 16'hFFFF; // CYCLES 0 - 15 |
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341 | defparam gen_srls[ 1].srl_radio.INIT = 16'hFFFF; // CYCLES 16 - 31 |
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342 | defparam gen_srls[ 2].srl_radio.INIT = 16'hFFFF; // CYCLES 32 - 47 |
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343 | defparam gen_srls[ 3].srl_radio.INIT = 16'hFFFF; // CYCLES 48 - 63 |
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344 | defparam gen_srls[ 4].srl_radio.INIT = 16'hFFFF; // CYCLES 64 - 79 |
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345 | defparam gen_srls[ 5].srl_radio.INIT = 16'hFFFF; // CYCLES 80 - 95 |
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346 | |
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347 | // Issue soft-reset; does *not* require write to 5A to take effect |
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348 | // reg[0] <= 30, then 10 (assert, then de-assert reset bit) |
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349 | defparam gen_srls[ 6].srl_radio.INIT = 16'h0000; // CYCLES 96 - 111 |
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350 | defparam gen_srls[ 7].srl_radio.INIT = 16'h30FF; // CYCLES 112 - 127 |
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351 | |
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352 | defparam gen_srls[ 8].srl_radio.INIT = 16'h0000; // CYCLES 128 - 143 |
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353 | defparam gen_srls[ 9].srl_radio.INIT = 16'h10FF; // CYCLES 144 - 159 |
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354 | |
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355 | // Switch clock input to CLK2; power-down CLK1 and PLL input |
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356 | // reg[45] <= 1A |
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357 | defparam gen_srls[10].srl_radio.INIT = 16'h0045; // CYCLES 160 - 175 |
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358 | //defparam gen_srls[11].srl_radio.INIT = `fpga_radio_clk_source; // CYCLES 176 - 191 |
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359 | defparam gen_srls[11].srl_radio.INIT = fpga_radio_clk_source; // CYCLES 176 - 191 |
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360 | |
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361 | // Bypass dividers on all clocks |
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362 | // reg[49,4B,4D,4F,51,53,55,57] <= 80 |
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363 | |
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364 | defparam gen_srls[12].srl_radio.INIT = 16'h0049; // CYCLES 192 - 207 |
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365 | defparam gen_srls[13].srl_radio.INIT = 16'h80FF; // CYCLES 208 - 223 |
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366 | |
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367 | defparam gen_srls[14].srl_radio.INIT = 16'h004B; // CYCLES 224 - 239 |
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368 | defparam gen_srls[15].srl_radio.INIT = 16'h80FF; // CYCLES 240 - 255 |
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369 | |
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370 | defparam gen_srls[16].srl_radio.INIT = 16'h004D; // CYCLES 256 - 271 |
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371 | defparam gen_srls[17].srl_radio.INIT = 16'h80FF; // CYCLES 272 - 287 |
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372 | |
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373 | defparam gen_srls[18].srl_radio.INIT = 16'h004F; // CYCLES 288 - 303 |
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374 | defparam gen_srls[19].srl_radio.INIT = 16'h80FF; // CYCLES 304 - 319 |
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375 | |
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376 | defparam gen_srls[20].srl_radio.INIT = 16'h0051; // CYCLES 320 - 335 |
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377 | defparam gen_srls[21].srl_radio.INIT = 16'h80FF; // CYCLES 336 - 351 |
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378 | |
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379 | defparam gen_srls[22].srl_radio.INIT = 16'h0053; // CYCLES 352 - 367 |
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380 | defparam gen_srls[23].srl_radio.INIT = 16'h80FF; // CYCLES 368 - 383 |
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381 | |
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382 | defparam gen_srls[24].srl_radio.INIT = 16'h0055; // CYCLES 384 - 399 |
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383 | defparam gen_srls[25].srl_radio.INIT = 16'h80FF; // CYCLES 400 - 415 |
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384 | |
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385 | defparam gen_srls[26].srl_radio.INIT = 16'h0057; // CYCLES 416 - 431 |
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386 | defparam gen_srls[27].srl_radio.INIT = 16'h80FF; // CYCLES 432 - 447 |
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387 | |
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388 | // Configure the output properties on the CMOS clock outputs. |
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389 | // Enabled outputs require CMOS (not LVDS), invertered output enabled |
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390 | // reg[40,41,42,43] <= 1E means output is enabled |
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391 | // reg[40,41,42,43] <= 01 means output is disabled |
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392 | defparam gen_srls[28].srl_radio.INIT = 16'h0040; // CYCLES 448 - 463 |
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393 | defparam gen_srls[29].srl_radio.INIT = radio_clk_out4_mode; // CYCLES 464 - 479 |
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394 | |
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395 | defparam gen_srls[30].srl_radio.INIT = 16'h0041; // CYCLES 480 - 495 |
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396 | defparam gen_srls[31].srl_radio.INIT = radio_clk_out5_mode; // CYCLES 496 - 511 |
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397 | |
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398 | defparam gen_srls[32].srl_radio.INIT = 16'h0042; // CYCLES 512 - 527 |
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399 | defparam gen_srls[33].srl_radio.INIT = radio_clk_out6_mode; // CYCLES 528 - 543 |
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400 | |
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401 | defparam gen_srls[34].srl_radio.INIT = 16'h0043; // CYCLES 544 - 559 |
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402 | defparam gen_srls[35].srl_radio.INIT = radio_clk_out7_mode; // CYCLES 560 - 575 |
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403 | |
---|
404 | // Configure the output properties on the PECL clock outputs |
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405 | // OUT0 enabled, 810mV drive; OUT1/2/3 disabled |
---|
406 | // reg[3C] <= 08; reg[3D,3E,3F] <= 0B |
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407 | defparam gen_srls[36].srl_radio.INIT = 16'h003C; // CYCLES 576 - 591 |
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408 | //defparam gen_srls[37].srl_radio.INIT = 16'h08FF; // CYCLES 592 - 607 |
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409 | defparam gen_srls[37].srl_radio.INIT = radio_clk_forward_out_mode; // CYCLES 592 - 607 |
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410 | |
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411 | defparam gen_srls[38].srl_radio.INIT = 16'h003D; // CYCLES 608 - 623 |
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412 | defparam gen_srls[39].srl_radio.INIT = 16'h0BFF; // CYCLES 624 - 639 |
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413 | |
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414 | defparam gen_srls[40].srl_radio.INIT = 16'h003E; // CYCLES 640 - 655 |
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415 | defparam gen_srls[41].srl_radio.INIT = 16'h0BFF; // CYCLES 656 - 671 |
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416 | |
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417 | defparam gen_srls[42].srl_radio.INIT = 16'h003F; // CYCLES 672 - 687 |
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418 | defparam gen_srls[43].srl_radio.INIT = 16'h0BFF; // CYCLES 688 - 703 |
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419 | |
---|
420 | |
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421 | // Latch the loaded values into the actual config registers |
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422 | // reg[5A] <= FF |
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423 | defparam gen_srls[44].srl_radio.INIT = 16'h005A; // CYCLES 704 - 719 |
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424 | defparam gen_srls[45].srl_radio.INIT = 16'hFFFF; // CYCLES 720 - 735 |
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425 | |
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426 | // unused cycles |
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427 | defparam gen_srls[46].srl_radio.INIT = 16'hFFFF; // CYCLES 736 - 751 |
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428 | defparam gen_srls[47].srl_radio.INIT = 16'hFFFF; // CYCLES 752 - 767 |
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429 | defparam gen_srls[48].srl_radio.INIT = 16'hFFFF; // CYCLES 768 - 783 |
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430 | defparam gen_srls[49].srl_radio.INIT = 16'hFFFF; // CYCLES 784 - 799 |
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431 | defparam gen_srls[50].srl_radio.INIT = 16'hFFFF; // CYCLES 800 - 815 |
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432 | defparam gen_srls[51].srl_radio.INIT = 16'hFFFF; // CYCLES 816 - 831 |
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433 | defparam gen_srls[52].srl_radio.INIT = 16'hFFFF; // CYCLES 832 - 847 |
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434 | defparam gen_srls[53].srl_radio.INIT = 16'hFFFF; // CYCLES 848 - 863 |
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435 | defparam gen_srls[54].srl_radio.INIT = 16'hFFFF; // CYCLES 864 - 879 |
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436 | defparam gen_srls[55].srl_radio.INIT = 16'hFFFF; // CYCLES 880 - 895 |
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437 | defparam gen_srls[56].srl_radio.INIT = 16'hFFFF; // CYCLES 896 - 911 |
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438 | defparam gen_srls[57].srl_radio.INIT = 16'hFFFF; // CYCLES 912 - 927 |
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439 | defparam gen_srls[58].srl_radio.INIT = 16'hFFFF; // CYCLES 928 - 943 |
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440 | defparam gen_srls[59].srl_radio.INIT = 16'hFFFF; // CYCLES 944 - 959 |
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441 | defparam gen_srls[60].srl_radio.INIT = 16'hFFFF; // CYCLES 960 - 975 |
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442 | defparam gen_srls[61].srl_radio.INIT = 16'hFFFF; // CYCLES 976 - 991 |
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443 | defparam gen_srls[62].srl_radio.INIT = 16'hFFFF; // CYCLES 992 - 1007 |
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444 | defparam gen_srls[63].srl_radio.INIT = 16'hFFFF; // CYCLES 1008 - 1023 |
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445 | |
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446 | // Here's some m-code that will help generate these vectors: |
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447 | // csb_low = 96 + 32*[0:15];sprintf('cfg_cyc == %d | ',csb_low) |
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448 | // csb_high = 96-8 + 32*[1:16];sprintf('cfg_cyc == %d | ',csb_high) |
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449 | |
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450 | `define RADIO_CSB_LOW_DECODE ((cfg_cyc == 96) | (cfg_cyc == 128) | (cfg_cyc == 160) | (cfg_cyc == 192) | (cfg_cyc == 224) | (cfg_cyc == 256) | (cfg_cyc == 288) | (cfg_cyc == 320) | (cfg_cyc == 352) | (cfg_cyc == 384) | (cfg_cyc == 416) | (cfg_cyc == 448) | (cfg_cyc == 480) | (cfg_cyc == 512) | (cfg_cyc == 544) | (cfg_cyc == 576) | (cfg_cyc == 608) | (cfg_cyc == 640) | (cfg_cyc == 672) | (cfg_cyc == 704)) |
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451 | `define RADIO_CSB_HIGH_DECODE ((cfg_cyc == 120) | (cfg_cyc == 152) | (cfg_cyc == 184) | (cfg_cyc == 216) | (cfg_cyc == 248) | (cfg_cyc == 280) | (cfg_cyc == 312) | (cfg_cyc == 344) | (cfg_cyc == 376) | (cfg_cyc == 408) | (cfg_cyc == 440) | (cfg_cyc == 472) | (cfg_cyc == 504) | (cfg_cyc == 536) | (cfg_cyc == 568) | (cfg_cyc == 600) | (cfg_cyc == 632) | (cfg_cyc == 664) | (cfg_cyc == 696) | (cfg_cyc == 728)) |
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452 | `define RADIO_EN_LOW_DECODE ( cfg_cyc == 0) |
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453 | `define RADIO_EN_HIGH_DECODE ( cfg_cyc == 4) |
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454 | |
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455 | //Register contents for the converter clock generator |
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456 | |
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457 | // Leave some emtpy clock cycles at boot to let things settle |
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458 | defparam gen_srls[ 0].srl_logic.INIT = 16'hFFFF; // CYCLES 0 - 15 |
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459 | defparam gen_srls[ 1].srl_logic.INIT = 16'hFFFF; // CYCLES 16 - 31 |
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460 | defparam gen_srls[ 2].srl_logic.INIT = 16'hFFFF; // CYCLES 32 - 47 |
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461 | defparam gen_srls[ 3].srl_logic.INIT = 16'hFFFF; // CYCLES 48 - 63 |
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462 | defparam gen_srls[ 4].srl_logic.INIT = 16'hFFFF; // CYCLES 64 - 79 |
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463 | defparam gen_srls[ 5].srl_logic.INIT = 16'hFFFF; // CYCLES 80 - 95 |
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464 | |
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465 | // Issue soft-reset; does *not* require write to 5A to take effect |
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466 | // reg[0] <= 30, then 10 (assert, then de-assert reset bit) |
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467 | defparam gen_srls[ 6].srl_logic.INIT = 16'h0000; // CYCLES 96 - 111 |
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468 | defparam gen_srls[ 7].srl_logic.INIT = 16'h30FF; // CYCLES 112 - 127 |
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469 | |
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470 | defparam gen_srls[ 8].srl_logic.INIT = 16'h0000; // CYCLES 128 - 143 |
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471 | defparam gen_srls[ 9].srl_logic.INIT = 16'h10FF; // CYCLES 144 - 159 |
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472 | |
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473 | // Switch clock input to CLK2; power-down CLK1 and PLL input |
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474 | // reg[45] <= 1A |
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475 | // defparam gen_srls[10].srl_logic.INIT = 16'h0045; // CYCLES 160 - 175 |
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476 | // defparam gen_srls[11].srl_logic.INIT = 16'h1AFF; // CYCLES 176 - 191 |
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477 | |
---|
478 | // For now, switch clock input to CLK1; power-down CLK2 and PLL input |
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479 | // reg[45] <= 1D |
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480 | defparam gen_srls[10].srl_logic.INIT = 16'h0045; // CYCLES 160 - 175 |
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481 | defparam gen_srls[11].srl_logic.INIT = fpga_logic_clk_source; // CYCLES 176 - 191 |
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482 | |
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483 | // Bypass dividers on all clocks |
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484 | // reg[49,4B,4D,4F,51,53,55,57] <= 80 |
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485 | |
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486 | defparam gen_srls[12].srl_logic.INIT = 16'h0049; // CYCLES 192 - 207 |
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487 | defparam gen_srls[13].srl_logic.INIT = 16'h80FF; // CYCLES 208 - 223 |
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488 | |
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489 | defparam gen_srls[14].srl_logic.INIT = 16'h004B; // CYCLES 224 - 239 |
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490 | defparam gen_srls[15].srl_logic.INIT = 16'h80FF; // CYCLES 240 - 255 |
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491 | |
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492 | defparam gen_srls[16].srl_logic.INIT = 16'h004D; // CYCLES 256 - 271 |
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493 | defparam gen_srls[17].srl_logic.INIT = 16'h80FF; // CYCLES 272 - 287 |
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494 | |
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495 | defparam gen_srls[18].srl_logic.INIT = 16'h004F; // CYCLES 288 - 303 |
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496 | defparam gen_srls[19].srl_logic.INIT = 16'h80FF; // CYCLES 304 - 319 |
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497 | |
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498 | defparam gen_srls[20].srl_logic.INIT = 16'h0051; // CYCLES 320 - 335 |
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499 | defparam gen_srls[21].srl_logic.INIT = 16'h80FF; // CYCLES 336 - 351 |
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500 | |
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501 | defparam gen_srls[22].srl_logic.INIT = 16'h0053; // CYCLES 352 - 367 |
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502 | defparam gen_srls[23].srl_logic.INIT = 16'h80FF; // CYCLES 368 - 383 |
---|
503 | |
---|
504 | defparam gen_srls[24].srl_logic.INIT = 16'h0055; // CYCLES 384 - 399 |
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505 | defparam gen_srls[25].srl_logic.INIT = 16'h80FF; // CYCLES 400 - 415 |
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506 | |
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507 | defparam gen_srls[26].srl_logic.INIT = 16'h0057; // CYCLES 416 - 431 |
---|
508 | defparam gen_srls[27].srl_logic.INIT = 16'h80FF; // CYCLES 432 - 447 |
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509 | |
---|
510 | // Configure the output properties on the PECL clock outputs |
---|
511 | // OUT0-OUT3 enabled, 810mV drive; |
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512 | // reg[3C,3D,3E,3F] <= 08; enables outputs with max (810mV) drive |
---|
513 | // reg[3C,3D,3E,3F] <= 04; enables outputs with min (340mV) drive |
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514 | // reg[3C,3D,3E,3F] <= 02; disables outputs |
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515 | |
---|
516 | defparam gen_srls[28].srl_logic.INIT = 16'h003C; // CYCLES 448 - 463 |
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517 | defparam gen_srls[29].srl_logic.INIT = logic_clk_out0_mode; // CYCLES 464 - 479 |
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518 | |
---|
519 | defparam gen_srls[30].srl_logic.INIT = 16'h003D; // CYCLES 480 - 495 |
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520 | defparam gen_srls[31].srl_logic.INIT = logic_clk_out1_mode; // CYCLES 496 - 511 |
---|
521 | |
---|
522 | defparam gen_srls[32].srl_logic.INIT = 16'h003E; // CYCLES 512 - 527 |
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523 | defparam gen_srls[33].srl_logic.INIT = logic_clk_out2_mode; // CYCLES 528 - 543 |
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524 | |
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525 | defparam gen_srls[34].srl_logic.INIT = 16'h003F; // CYCLES 544 - 559 |
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526 | defparam gen_srls[35].srl_logic.INIT = logic_clk_out3_mode; // CYCLES 560 - 575 |
---|
527 | |
---|
528 | // Configure the output properties for the forwarded clock (OUT7) |
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529 | // CMOS (not LVDS), inverted output enabled, maximum drive current |
---|
530 | // reg[43] <= 1E; |
---|
531 | defparam gen_srls[36].srl_logic.INIT = 16'h0043; // CYCLES 576 - 591 |
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532 | //defparam gen_srls[37].srl_logic.INIT = 16'h1EFF; // CYCLES 592 - 607 |
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533 | defparam gen_srls[37].srl_logic.INIT = logic_clk_forward_out_mode; // CYCLES 592 - 607 |
---|
534 | |
---|
535 | // Power down CMOS OUT6 |
---|
536 | // reg[42] <= 1F; |
---|
537 | defparam gen_srls[38].srl_logic.INIT = 16'h0042; // CYCLES 608 - 623 |
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538 | defparam gen_srls[39].srl_logic.INIT = 16'h1FFF; // CYCLES 624 - 639 |
---|
539 | |
---|
540 | // OUT5 : See comments at the top of this file |
---|
541 | defparam gen_srls[40].srl_logic.INIT = 16'h0041; // CYCLES 640 - 655 |
---|
542 | defparam gen_srls[41].srl_logic.INIT = `fpga_clk_out5_reg; // CYCLES 656 - 671 |
---|
543 | |
---|
544 | // OUT4 : See comments at the top of this file |
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545 | defparam gen_srls[42].srl_logic.INIT = 16'h0040; // CYCLES 672 - 687 |
---|
546 | defparam gen_srls[43].srl_logic.INIT = `fpga_clk_out4_reg; // CYCLES 688 - 703 |
---|
547 | |
---|
548 | // Latch the loaded values into the actual config registers |
---|
549 | // reg[5A] <= FF |
---|
550 | |
---|
551 | defparam gen_srls[44].srl_logic.INIT = 16'h005A; // CYCLES 704 - 719 |
---|
552 | defparam gen_srls[45].srl_logic.INIT = 16'hFFFF; // CYCLES 720 - 735 |
---|
553 | |
---|
554 | // unused cycles |
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555 | defparam gen_srls[46].srl_logic.INIT = 16'h0000; // CYCLES 736 - 751 |
---|
556 | defparam gen_srls[47].srl_logic.INIT = 16'h0000; // CYCLES 752 - 767 |
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557 | defparam gen_srls[48].srl_logic.INIT = 16'h0000; // CYCLES 768 - 783 |
---|
558 | defparam gen_srls[49].srl_logic.INIT = 16'h0000; // CYCLES 784 - 799 |
---|
559 | defparam gen_srls[50].srl_logic.INIT = 16'h0000; // CYCLES 800 - 815 |
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560 | defparam gen_srls[51].srl_logic.INIT = 16'h0000; // CYCLES 816 - 831 |
---|
561 | defparam gen_srls[52].srl_logic.INIT = 16'h0000; // CYCLES 832 - 847 |
---|
562 | defparam gen_srls[53].srl_logic.INIT = 16'h0000; // CYCLES 848 - 863 |
---|
563 | defparam gen_srls[54].srl_logic.INIT = 16'h0000; // CYCLES 864 - 879 |
---|
564 | defparam gen_srls[55].srl_logic.INIT = 16'h0000; // CYCLES 880 - 895 |
---|
565 | defparam gen_srls[56].srl_logic.INIT = 16'h0000; // CYCLES 896 - 911 |
---|
566 | defparam gen_srls[57].srl_logic.INIT = 16'h0000; // CYCLES 912 - 927 |
---|
567 | defparam gen_srls[58].srl_logic.INIT = 16'h0000; // CYCLES 928 - 943 |
---|
568 | defparam gen_srls[59].srl_logic.INIT = 16'h0000; // CYCLES 944 - 959 |
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569 | defparam gen_srls[60].srl_logic.INIT = 16'h0000; // CYCLES 960 - 975 |
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570 | defparam gen_srls[61].srl_logic.INIT = 16'h0000; // CYCLES 976 - 991 |
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571 | defparam gen_srls[62].srl_logic.INIT = 16'h0000; // CYCLES 992 - 1007 |
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572 | defparam gen_srls[63].srl_logic.INIT = 16'h0000; // CYCLES 1008 - 1023 |
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573 | |
---|
574 | `define LOGIC_CSB_LOW_DECODE ((cfg_cyc == 96) | (cfg_cyc == 128) | (cfg_cyc == 160) | (cfg_cyc == 192) | (cfg_cyc == 224) | (cfg_cyc == 256) | (cfg_cyc == 288) | (cfg_cyc == 320) | (cfg_cyc == 352) | (cfg_cyc == 384) | (cfg_cyc == 416) | (cfg_cyc == 448) | (cfg_cyc == 480) | (cfg_cyc == 512) | (cfg_cyc == 544) | (cfg_cyc == 576) | (cfg_cyc == 608) | (cfg_cyc == 640) | (cfg_cyc == 672) | (cfg_cyc == 704)) |
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575 | `define LOGIC_CSB_HIGH_DECODE ((cfg_cyc == 120) | (cfg_cyc == 152) | (cfg_cyc == 184) | (cfg_cyc == 216) | (cfg_cyc == 248) | (cfg_cyc == 280) | (cfg_cyc == 312) | (cfg_cyc == 344) | (cfg_cyc == 376) | (cfg_cyc == 408) | (cfg_cyc == 440) | (cfg_cyc == 472) | (cfg_cyc == 504) | (cfg_cyc == 536) | (cfg_cyc == 568) | (cfg_cyc == 600) | (cfg_cyc == 632) | (cfg_cyc == 664) | (cfg_cyc == 696) | (cfg_cyc == 728)) |
---|
576 | `define LOGIC_EN_LOW_DECODE (cfg_cyc == 0) |
---|
577 | `define LOGIC_EN_HIGH_DECODE (cfg_cyc == 4) |
---|
578 | |
---|
579 | // Decode various values of CFG_CYC to assert and deassert |
---|
580 | // control signals at various bit positions within the |
---|
581 | // configuration sequences. CFG_RADIO_CSB_LOW, for example, |
---|
582 | // should decode the value of CFG_CYC corresponding to the |
---|
583 | // first bit of an SCP command. CFG_RADIO_CSB_HIGH should |
---|
584 | // likewise decode the value corresponding to the first |
---|
585 | // bit FOLLOWING a streaming register access. |
---|
586 | |
---|
587 | reg cfg_radio_csb_low = 1'b0; |
---|
588 | reg cfg_radio_csb_high = 1'b0; |
---|
589 | reg cfg_radio_en_low = 1'b0; |
---|
590 | reg cfg_radio_en_high = 1'b0; |
---|
591 | |
---|
592 | reg cfg_logic_csb_low = 1'b0; |
---|
593 | reg cfg_logic_csb_high = 1'b0; |
---|
594 | reg cfg_logic_en_low = 1'b0; |
---|
595 | reg cfg_logic_en_high = 1'b0; |
---|
596 | |
---|
597 | always @ (posedge sys_clk) |
---|
598 | begin |
---|
599 | if (~scp_cyc_start) |
---|
600 | begin |
---|
601 | cfg_radio_csb_low <= 1'b0; |
---|
602 | cfg_radio_csb_high <= 1'b0; |
---|
603 | cfg_radio_en_low <= 1'b0; |
---|
604 | cfg_radio_en_high <= 1'b0; |
---|
605 | |
---|
606 | cfg_logic_csb_low <= 1'b0; |
---|
607 | cfg_logic_csb_high <= 1'b0; |
---|
608 | cfg_logic_en_low <= 1'b0; |
---|
609 | cfg_logic_en_high <= 1'b0; |
---|
610 | end |
---|
611 | |
---|
612 | else |
---|
613 | begin |
---|
614 | if (cfg_cyc_done) |
---|
615 | begin |
---|
616 | cfg_radio_csb_low <= 1'b0; |
---|
617 | cfg_radio_csb_high <= 1'b1; |
---|
618 | cfg_radio_en_low <= 1'b0; |
---|
619 | cfg_radio_en_high <= 1'b1; |
---|
620 | |
---|
621 | cfg_logic_csb_low <= 1'b0; |
---|
622 | cfg_logic_csb_high <= 1'b1; |
---|
623 | cfg_logic_en_low <= 1'b0; |
---|
624 | cfg_logic_en_high <= 1'b1; |
---|
625 | end |
---|
626 | else |
---|
627 | begin |
---|
628 | cfg_radio_csb_low <= `RADIO_CSB_LOW_DECODE; |
---|
629 | cfg_radio_csb_high <= `RADIO_CSB_HIGH_DECODE; |
---|
630 | cfg_radio_en_low <= `RADIO_EN_LOW_DECODE; |
---|
631 | cfg_radio_en_high <= `RADIO_EN_HIGH_DECODE; |
---|
632 | |
---|
633 | cfg_logic_csb_low <= `LOGIC_CSB_LOW_DECODE; |
---|
634 | cfg_logic_csb_high <= `LOGIC_CSB_HIGH_DECODE; |
---|
635 | cfg_logic_en_low <= `LOGIC_EN_LOW_DECODE; |
---|
636 | cfg_logic_en_high <= `LOGIC_EN_HIGH_DECODE; |
---|
637 | end |
---|
638 | |
---|
639 | end |
---|
640 | |
---|
641 | end |
---|
642 | |
---|
643 | |
---|
644 | |
---|
645 | always @ (posedge sys_clk) |
---|
646 | begin |
---|
647 | if (srl_shift) cfg_radio_dat_out <= srl_radio_q [0]; |
---|
648 | else cfg_radio_dat_out <= cfg_radio_dat_out; |
---|
649 | |
---|
650 | cfg_radio_csb_out <= cfg_radio_csb_out & ~cfg_radio_csb_low |
---|
651 | | ~cfg_radio_csb_out & cfg_radio_csb_high; |
---|
652 | cfg_radio_en_out <= cfg_radio_en_out & ~cfg_radio_en_low |
---|
653 | | ~cfg_radio_en_out & cfg_radio_en_high; |
---|
654 | cfg_radio_clk_out <= cfg_radio_clk_out & ~cfg_clk_low |
---|
655 | | ~cfg_radio_clk_out & cfg_clk_high; |
---|
656 | |
---|
657 | if (srl_shift) cfg_logic_dat_out <= srl_logic_q [0]; |
---|
658 | else cfg_logic_dat_out <= cfg_logic_dat_out; |
---|
659 | |
---|
660 | cfg_logic_csb_out <= cfg_logic_csb_out & ~cfg_logic_csb_low |
---|
661 | | ~cfg_logic_csb_out & cfg_logic_csb_high; |
---|
662 | cfg_logic_en_out <= cfg_logic_en_out & ~cfg_logic_en_low |
---|
663 | | ~cfg_logic_en_out & cfg_logic_en_high; |
---|
664 | cfg_logic_clk_out <= cfg_logic_clk_out & ~cfg_clk_low |
---|
665 | | ~cfg_logic_clk_out & cfg_clk_high; |
---|
666 | end |
---|
667 | |
---|
668 | endmodule |
---|