source: PlatformSupport/Deprecated/pcores/difclk_v1_00_a/data/difclk_v2_1_0.mpd

###################################################################
##
## Name     : difclk
## Desc     : Microprocessor Peripheral Description
##          : Automatically generated by PsfUtility
##
###################################################################

BEGIN difclk

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION USAGE_LEVEL = BASE_USER
OPTION HDL = VHDL
OPTION ARCH_SUPPORT_MAP = (virtex2p=PREFERRED, virtex4=PREFERRED, others=AVAILABLE)
OPTION IP_GROUP = USER
OPTION RUN_NGCBUILD = TRUE

IO_INTERFACE IO_IF = mgt_difclk1_0, IO_TYPE = WARP_MGTDIFCLK1_V1

## Bus Interfaces

## Generics for VHDL or Parameters for Verilog

## Ports
PORT top_ref_clk_p = "", DIR = I, IOB_STATE=BUF, IO_IS = difclk_p
PORT top_ref_clk_n = "", DIR = I, IOB_STATE=BUF, IO_IS = difclk_n
PORT user_clk_i = mgt_usr_clk, DIR = O
PORT top_ref_clk_i = mgt_top_ref_clk, DIR = O

END