1 | ################################################################### |
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2 | # Copyright (c) 2006 Rice University |
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3 | # All Rights Reserved |
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4 | # This code is covered by the Rice-WARP license |
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5 | # See http://warp.rice.edu/license/ for details |
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6 | ################################################################### |
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7 | |
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8 | BEGIN eeprom |
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9 | |
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10 | ## Peripheral Options |
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11 | OPTION IPTYPE = PERIPHERAL |
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12 | OPTION IMP_NETLIST = TRUE |
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13 | OPTION HDL = MIXED |
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14 | OPTION ARCH_SUPPORT_MAP = (virtex2p=PREFERRED, virtex4=PREFERRED, others=AVAILABLE) |
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15 | OPTION IP_GROUP = MICROBLAZE:PPC:USER |
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16 | OPTION USAGE_LEVEL = BASE_USER |
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17 | |
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18 | IO_INTERFACE IO_IF = EEPROM, IO_TYPE = WARP_EEPROM_V1 |
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19 | |
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20 | ## Bus Interfaces |
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21 | BUS_INTERFACE BUS = SOPB, BUS_TYPE = SLAVE, BUS_STD = OPB |
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22 | |
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23 | ## Generics for VHDL or Parameters for Verilog |
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24 | PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, BUS = SOPB, ADDRESS = BASE, PAIR = C_HIGHADDR, MIN_SIZE = 0x00010000 |
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25 | PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, BUS = SOPB, ADDRESS = HIGH, PAIR = C_BASEADDR |
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26 | PARAMETER C_OPB_AWIDTH = 32, DT = INTEGER, BUS = SOPB |
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27 | PARAMETER C_OPB_DWIDTH = 32, DT = INTEGER, BUS = SOPB |
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28 | PARAMETER C_USER_ID_CODE = 3, DT = INTEGER |
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29 | PARAMETER C_FAMILY = virtex2p, DT = STRING |
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30 | |
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31 | ## Ports |
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32 | PORT DQ0 = "", DIR = IO, THREE_STATE = TRUE, TRI_I = DQ0_I, TRI_O = DQ0_O, TRI_T = DQ0_T |
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33 | PORT DQ0_T = "", DIR = O |
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34 | PORT DQ0_O = "", DIR = O |
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35 | PORT DQ0_I = "", DIR = I |
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36 | |
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37 | PORT DQ1 = "", DIR = IO, THREE_STATE = TRUE, TRI_I = DQ1_I, TRI_O = DQ1_O, TRI_T = DQ1_T |
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38 | PORT DQ1_T = "", DIR = O |
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39 | PORT DQ1_O = "", DIR = O |
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40 | PORT DQ1_I = "", DIR = I, INITIALVAL = VCC |
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41 | |
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42 | PORT DQ2 = "", DIR = IO, THREE_STATE = TRUE, TRI_I = DQ2_I, TRI_O = DQ2_O, TRI_T = DQ2_T |
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43 | PORT DQ2_T = "", DIR = O |
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44 | PORT DQ2_O = "", DIR = O |
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45 | PORT DQ2_I = "", DIR = I, INITIALVAL = VCC |
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46 | |
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47 | PORT DQ3 = "", DIR = IO, THREE_STATE = TRUE, TRI_I = DQ3_I, TRI_O = DQ3_O, TRI_T = DQ3_T |
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48 | PORT DQ3_T = "", DIR = O |
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49 | PORT DQ3_O = "", DIR = O |
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50 | PORT DQ3_I = "", DIR = I, INITIALVAL = VCC |
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51 | |
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52 | PORT DQ4 = "", DIR = IO, THREE_STATE = TRUE, TRI_I = DQ4_I, TRI_O = DQ4_O, TRI_T = DQ4_T |
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53 | PORT DQ4_T = "", DIR = O |
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54 | PORT DQ4_O = "", DIR = O |
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55 | PORT DQ4_I = "", DIR = I, INITIALVAL = VCC |
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56 | |
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57 | PORT DQ5 = "", DIR = IO, THREE_STATE = TRUE, TRI_I = DQ5_I, TRI_O = DQ5_O, TRI_T = DQ5_T |
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58 | PORT DQ5_T = "", DIR = O |
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59 | PORT DQ5_O = "", DIR = O |
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60 | PORT DQ5_I = "", DIR = I, INITIALVAL = VCC |
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61 | |
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62 | PORT DQ6 = "", DIR = IO, THREE_STATE = TRUE, TRI_I = DQ6_I, TRI_O = DQ6_O, TRI_T = DQ6_T |
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63 | PORT DQ6_T = "", DIR = O |
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64 | PORT DQ6_O = "", DIR = O |
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65 | PORT DQ6_I = "", DIR = I, INITIALVAL = VCC |
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66 | |
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67 | PORT DQ7 = "", DIR = IO, THREE_STATE = TRUE, TRI_I = DQ7_I, TRI_O = DQ7_O, TRI_T = DQ7_T |
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68 | PORT DQ7_T = "", DIR = O |
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69 | PORT DQ7_O = "", DIR = O |
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70 | PORT DQ7_I = "", DIR = I, INITIALVAL = VCC |
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71 | |
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72 | PORT OPB_Clk = "", DIR = I, SIGIS = Clk, BUS = SOPB |
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73 | PORT OPB_Rst = OPB_Rst, DIR = I, SIGIS = Rst, BUS = SOPB |
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74 | PORT Sl_DBus = Sl_DBus, DIR = O, VEC = [0:(C_OPB_DWIDTH-1)], BUS = SOPB |
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75 | PORT Sl_errAck = Sl_errAck, DIR = O, BUS = SOPB |
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76 | PORT Sl_retry = Sl_retry, DIR = O, BUS = SOPB |
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77 | PORT Sl_toutSup = Sl_toutSup, DIR = O, BUS = SOPB |
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78 | PORT Sl_xferAck = Sl_xferAck, DIR = O, BUS = SOPB |
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79 | PORT OPB_ABus = OPB_ABus, DIR = I, VEC = [0:(C_OPB_AWIDTH-1)], BUS = SOPB |
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80 | PORT OPB_BE = OPB_BE, DIR = I, VEC = [0:((C_OPB_DWIDTH/8)-1)], BUS = SOPB |
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81 | PORT OPB_DBus = OPB_DBus, DIR = I, VEC = [0:(C_OPB_DWIDTH-1)], BUS = SOPB |
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82 | PORT OPB_RNW = OPB_RNW, DIR = I, BUS = SOPB |
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83 | PORT OPB_select = OPB_select, DIR = I, BUS = SOPB |
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84 | PORT OPB_seqAddr = OPB_seqAddr, DIR = I, BUS = SOPB |
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85 | |
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86 | END |
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