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source: PlatformSupport/Deprecated/pcores/eeprom_v1_02_a/hdl/vhdl/eeprom.vhd

Last change on this file was 949, checked in by murphpo, 16 years ago
re-adding OPB-based EEPROM
File size: 27.3 KB

Line
1	------------------------------------------------------------------------------
2	-- EEPROM.vhd - entity/architecture pair
3	------------------------------------------------------------------------------
4	-- IMPORTANT:
5	-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
6	--
7	-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
8	--
9	-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
10	-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
11	-- OF THE USER_LOGIC ENTITY.
12	------------------------------------------------------------------------------
13	--
14	-- ***************************************************************************
15	-- Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
16	--
17	-- Xilinx, Inc.
18	-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
19	-- AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
20	-- SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
21	-- OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
22	-- APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
23	-- THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
24	-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
25	-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
26	-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
27	-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
28	-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
29	-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
30	-- FOR A PARTICULAR PURPOSE.
31	--
32	-- ***************************************************************************
33	--
34	------------------------------------------------------------------------------
35	-- Filename: EEPROM.vhd
36	-- Version: 1.00.a
37	-- Description: Top level design, instantiates IPIF and user logic.
38	-- Date: Fri Jul 28 13:08:06 2006 (by Create and Import Peripheral Wizard)
39	-- VHDL Standard: VHDL'93
40	------------------------------------------------------------------------------
41	-- Naming Conventions:
42	-- active low signals: "*_n"
43	-- clock signals: "clk", "clk_div#", "clk_#x"
44	-- reset signals: "rst", "rst_n"
45	-- generics: "C_*"
46	-- user defined types: "*_TYPE"
47	-- state machine next state: "*_ns"
48	-- state machine current state: "*_cs"
49	-- combinatorial signals: "*_com"
50	-- pipelined or register delay signals: "*_d#"
51	-- counter signals: "cnt"
52	-- clock enable signals: "*_ce"
53	-- internal version of output port: "*_i"
54	-- device pins: "*_pin"
55	-- ports: "- Names begin with Uppercase"
56	-- processes: "*_PROCESS"
57	-- component instantiations: "<ENTITY_>I_<#\|FUNC>"
58	------------------------------------------------------------------------------
59
60	library ieee;
61	use ieee.std_logic_1164.all;
62	use ieee.std_logic_arith.all;
63	use ieee.std_logic_unsigned.all;
64
65	library proc_common_v2_00_a;
66	use proc_common_v2_00_a.proc_common_pkg.all;
67	use proc_common_v2_00_a.ipif_pkg.all;
68	library opb_ipif_v3_01_c;
69	use opb_ipif_v3_01_c.all;
70
71	library eeprom_v1_02_a;
72	use eeprom_v1_02_a.all;
73
74	------------------------------------------------------------------------------
75	-- Entity section
76	------------------------------------------------------------------------------
77	-- Definition of Generics:
78	-- C_BASEADDR -- User logic base address
79	-- C_HIGHADDR -- User logic high address
80	-- C_OPB_AWIDTH -- OPB address bus width
81	-- C_OPB_DWIDTH -- OPB data bus width
82	-- C_USER_ID_CODE -- User ID to place in MIR/Reset register
83	-- C_FAMILY -- Target FPGA architecture
84	--
85	-- Definition of Ports:
86	-- OPB_Clk -- OPB Clock
87	-- OPB_Rst -- OPB Reset
88	-- Sl_DBus -- Slave data bus
89	-- Sl_errAck -- Slave error acknowledge
90	-- Sl_retry -- Slave retry
91	-- Sl_toutSup -- Slave timeout suppress
92	-- Sl_xferAck -- Slave transfer acknowledge
93	-- OPB_ABus -- OPB address bus
94	-- OPB_BE -- OPB byte enable
95	-- OPB_DBus -- OPB data bus
96	-- OPB_RNW -- OPB read/not write
97	-- OPB_select -- OPB select
98	-- OPB_seqAddr -- OPB sequential address
99	------------------------------------------------------------------------------
100
101	entity eeprom is
102	generic
103	(
104	-- ADD USER GENERICS BELOW THIS LINE ---------------
105	--USER generics added here
106	-- ADD USER GENERICS ABOVE THIS LINE ---------------
107
108	-- DO NOT EDIT BELOW THIS LINE ---------------------
109	-- Bus protocol parameters, do not add to or delete
110	C_BASEADDR : std_logic_vector := X"FFFFFFFF";
111	C_HIGHADDR : std_logic_vector := X"00000000";
112	C_OPB_AWIDTH : integer := 32;
113	C_OPB_DWIDTH : integer := 32;
114	C_USER_ID_CODE : integer := 3;
115	C_FAMILY : string := "virtex2p"
116	-- DO NOT EDIT ABOVE THIS LINE ---------------------
117	);
118	port
119	(
120	-- ADD USER PORTS BELOW THIS LINE ------------------
121	DQ0_T : out std_logic;
122	DQ0_O : out std_logic;
123	DQ0_I : in std_logic;
124
125	DQ1_T : out std_logic;
126	DQ1_O : out std_logic;
127	DQ1_I : in std_logic;
128
129	DQ2_T : out std_logic;
130	DQ2_O : out std_logic;
131	DQ2_I : in std_logic;
132
133	DQ3_T : out std_logic;
134	DQ3_O : out std_logic;
135	DQ3_I : in std_logic;
136
137	DQ4_T : out std_logic;
138	DQ4_O : out std_logic;
139	DQ4_I : in std_logic;
140
141	DQ5_T : out std_logic;
142	DQ5_O : out std_logic;
143	DQ5_I : in std_logic;
144
145	DQ6_T : out std_logic;
146	DQ6_O : out std_logic;
147	DQ6_I : in std_logic;
148
149	DQ7_T : out std_logic;
150	DQ7_O : out std_logic;
151	DQ7_I : in std_logic;
152
153	-- ADD USER PORTS ABOVE THIS LINE ------------------
154
155	-- DO NOT EDIT BELOW THIS LINE ---------------------
156	-- Bus protocol ports, do not add to or delete
157	OPB_Clk : in std_logic;
158	OPB_Rst : in std_logic;
159	Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
160	Sl_errAck : out std_logic;
161	Sl_retry : out std_logic;
162	Sl_toutSup : out std_logic;
163	Sl_xferAck : out std_logic;
164	OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
165	OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
166	OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
167	OPB_RNW : in std_logic;
168	OPB_select : in std_logic;
169	OPB_seqAddr : in std_logic
170	-- DO NOT EDIT ABOVE THIS LINE ---------------------
171	);
172
173	attribute SIGIS : string;
174	attribute SIGIS of OPB_Clk : signal is "Clk";
175	attribute SIGIS of OPB_Rst : signal is "Rst";
176
177	attribute MIN_SIZE : string;
178	attribute MIN_SIZE of C_BASEADDR:constant is "0x100";
179
180	attribute INITIALVAL : string;
181	attribute INITIALVAL of DQ1_I : signal is "VCC";
182	attribute INITIALVAL of DQ2_I : signal is "VCC";
183	attribute INITIALVAL of DQ3_I : signal is "VCC";
184	attribute INITIALVAL of DQ4_I : signal is "VCC";
185	attribute INITIALVAL of DQ5_I : signal is "VCC";
186	attribute INITIALVAL of DQ6_I : signal is "VCC";
187	attribute INITIALVAL of DQ7_I : signal is "VCC";
188
189	end entity eeprom;
190
191	------------------------------------------------------------------------------
192	-- Architecture section
193	------------------------------------------------------------------------------
194
195	architecture IMP of eeprom is
196
197	------------------------------------------
198	-- Constant: array of address range identifiers
199	------------------------------------------
200	constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE :=
201	(
202	0 => USER_00, -- user logic address space
203	1 => IPIF_RST -- include IPIF S/W Reset/MIR service
204	);
205
206	------------------------------------------
207	-- Constant: array of address pairs for each address range
208	------------------------------------------
209	constant ZERO_ADDR_PAD : std_logic_vector(0 to 64-C_OPB_AWIDTH-1) := (others => '0');
210
211	constant USER_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
212	constant USER_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
213
214	constant RST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
215	constant RST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
216
217	constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
218	(
219	ZERO_ADDR_PAD & USER_BASEADDR, -- user logic base address
220	ZERO_ADDR_PAD & USER_HIGHADDR, -- user logic high address
221	ZERO_ADDR_PAD & RST_BASEADDR, -- MIR/Reset register base address
222	ZERO_ADDR_PAD & RST_HIGHADDR -- MIR/Reset register high address
223	);
224
225	------------------------------------------
226	-- Constant: array of data widths for each target address range
227	------------------------------------------
228	constant USER_DWIDTH : integer := C_OPB_DWIDTH;
229
230	constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
231	(
232	0 => USER_DWIDTH, -- user logic data width
233	1 => C_OPB_DWIDTH -- MIR/Reset register data width
234	);
235
236	------------------------------------------
237	-- Constant: array of desired number of chip enables for each address range
238	------------------------------------------
239	constant USER_NUM_CE : integer := 1;
240
241	constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
242	(
243	0 => pad_power2(USER_NUM_CE), -- user logic number of CEs
244	1 => 1 -- MIR/Reset register - 1 CE
245	);
246
247	------------------------------------------
248	-- Constant: array of unique properties for each address range
249	------------------------------------------
250	constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE :=
251	(
252	0 => (others => 0), -- user logic slave space dependent properties (none defined)
253	1 => (others => 0) -- IPIF reset/mir dependent properties (none defined)
254	);
255
256	------------------------------------------
257	-- Constant: pipeline mode
258	-- 1 = include OPB-In pipeline registers
259	-- 2 = include IP pipeline registers
260	-- 3 = include OPB-In and IP pipeline registers
261	-- 4 = include OPB-Out pipeline registers
262	-- 5 = include OPB-In and OPB-Out pipeline registers
263	-- 6 = include IP and OPB-Out pipeline registers
264	-- 7 = include OPB-In, IP, and OPB-Out pipeline registers
265	-- Note:
266	-- only mode 4, 5, 7 are supported for this release
267	------------------------------------------
268	constant PIPELINE_MODEL : integer := 5;
269
270	------------------------------------------
271	-- Constant: user core ID code
272	------------------------------------------
273	constant DEV_BLK_ID : integer := C_USER_ID_CODE;
274
275	------------------------------------------
276	-- Constant: enable MIR/Reset register
277	------------------------------------------
278	constant DEV_MIR_ENABLE : integer := 1;
279
280	------------------------------------------
281	-- Constant: array of IP interrupt mode
282	-- 1 = Active-high interrupt condition
283	-- 2 = Active-low interrupt condition
284	-- 3 = Active-high pulse interrupt event
285	-- 4 = Active-low pulse interrupt event
286	-- 5 = Positive-edge interrupt event
287	-- 6 = Negative-edge interrupt event
288	------------------------------------------
289	constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
290	(
291	0 => 0 -- not used
292	);
293
294	------------------------------------------
295	-- Constant: enable device burst
296	------------------------------------------
297	constant DEV_BURST_ENABLE : integer := 0;
298
299	------------------------------------------
300	-- Constant: include address counter for burst transfers
301	------------------------------------------
302	constant INCLUDE_ADDR_CNTR : integer := 0;
303
304	------------------------------------------
305	-- Constant: include write buffer that decouples OPB and IPIC write transactions
306	------------------------------------------
307	constant INCLUDE_WR_BUF : integer := 0;
308
309	------------------------------------------
310	-- Constant: index for CS/CE
311	------------------------------------------
312	constant USER_NUM_CS : integer := 1;
313
314	constant USER00_CS_INDEX : integer := get_id_index(ARD_ID_ARRAY, USER_00);
315
316	constant USER00_CE_INDEX : integer := calc_start_ce_index(ARD_NUM_CE_ARRAY, USER00_CS_INDEX);
317
318	------------------------------------------
319	-- IP Interconnect (IPIC) signal declarations -- do not delete
320	-- prefix 'i' stands for IPIF while prefix 'u' stands for user logic
321	-- typically user logic will be hooked up to IPIF directly via i<sig>
322	-- unless signal slicing and muxing are needed via u<sig>
323	------------------------------------------
324	signal iBus2IP_CS : std_logic_vector(0 to ARD_ID_ARRAY'length-1);
325	signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
326	signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
327	signal iBus2IP_Data : std_logic_vector(0 to C_OPB_DWIDTH-1);
328	signal iBus2IP_Addr : std_logic_vector(0 to C_OPB_AWIDTH-1);
329	signal iBus2IP_BE : std_logic_vector(0 to C_OPB_DWIDTH/8-1);
330	signal iBus2IP_RNW : std_logic;
331	signal iIP2Bus_Data : std_logic_vector(0 to C_OPB_DWIDTH-1) := (others => '0');
332	signal iIP2Bus_Ack : std_logic := '0';
333	signal iIP2Bus_Error : std_logic := '0';
334	signal iIP2Bus_Retry : std_logic := '0';
335	signal iIP2Bus_ToutSup : std_logic := '0';
336	signal iIP2Bus_PostedWrInh : std_logic_vector(0 to ARD_ID_ARRAY'length-1) := (others => '0');
337	signal ZERO_IP2RFIFO_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_RDFIFO_DATA))-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
338	signal ZERO_WFIFO2IP_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_WRFIFO_DATA))-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
339	signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
340	signal iBus2IP_Clk : std_logic;
341	signal iBus2IP_Reset : std_logic;
342	signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1);
343	signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1);
344	signal uBus2IP_CS : std_logic_vector(0 to USER_NUM_CS-1);
345	signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1);
346	signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1);
347	signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1);
348	signal uIP2Bus_PostedWrInh : std_logic;
349
350	------------------------------------------
351	-- Component declaration for verilog user logic
352	------------------------------------------
353	component user_logic is
354	generic
355	(
356	-- ADD USER GENERICS BELOW THIS LINE ---------------
357	--USER generics added here
358	-- ADD USER GENERICS ABOVE THIS LINE ---------------
359
360	-- DO NOT EDIT BELOW THIS LINE ---------------------
361	-- Bus protocol parameters, do not add to or delete
362	C_AWIDTH : integer := 32;
363	C_DWIDTH : integer := 32;
364	C_NUM_CS : integer := 1;
365	C_NUM_CE : integer := 1
366	-- DO NOT EDIT ABOVE THIS LINE ---------------------
367	);
368	port
369	(
370	-- ADD USER PORTS BELOW THIS LINE ------------------
371	DQ0_T : out std_logic;
372	DQ0_O : out std_logic;
373	DQ0_I : in std_logic;
374
375	DQ1_T : out std_logic;
376	DQ1_O : out std_logic;
377	DQ1_I : in std_logic;
378
379	DQ2_T : out std_logic;
380	DQ2_O : out std_logic;
381	DQ2_I : in std_logic;
382
383	DQ3_T : out std_logic;
384	DQ3_O : out std_logic;
385	DQ3_I : in std_logic;
386
387	DQ4_T : out std_logic;
388	DQ4_O : out std_logic;
389	DQ4_I : in std_logic;
390
391	DQ5_T : out std_logic;
392	DQ5_O : out std_logic;
393	DQ5_I : in std_logic;
394
395	DQ6_T : out std_logic;
396	DQ6_O : out std_logic;
397	DQ6_I : in std_logic;
398
399	DQ7_T : out std_logic;
400	DQ7_O : out std_logic;
401	DQ7_I : in std_logic;
402	-- ADD USER PORTS ABOVE THIS LINE ------------------
403
404	-- DO NOT EDIT BELOW THIS LINE ---------------------
405	-- Bus protocol ports, do not add to or delete
406	Bus2IP_Clk : in std_logic;
407	Bus2IP_Reset : in std_logic;
408	Bus2IP_Addr : in std_logic_vector(0 to C_AWIDTH-1);
409	Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
410	Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
411	Bus2IP_RNW : in std_logic;
412	Bus2IP_CS : in std_logic_vector(0 to C_NUM_CS-1);
413	Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1);
414	Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1);
415	IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
416	IP2Bus_Ack : out std_logic;
417	IP2Bus_Retry : out std_logic;
418	IP2Bus_Error : out std_logic;
419	IP2Bus_ToutSup : out std_logic;
420	IP2Bus_PostedWrInh : out std_logic
421	-- DO NOT EDIT ABOVE THIS LINE ---------------------
422	);
423	end component user_logic;
424
425	begin
426
427	------------------------------------------
428	-- instantiate the OPB IPIF
429	------------------------------------------
430	OPB_IPIF_I : entity opb_ipif_v3_01_c.opb_ipif
431	generic map
432	(
433	C_ARD_ID_ARRAY => ARD_ID_ARRAY,
434	C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
435	C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY,
436	C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
437	C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY,
438	C_PIPELINE_MODEL => PIPELINE_MODEL,
439	C_DEV_BLK_ID => DEV_BLK_ID,
440	C_DEV_MIR_ENABLE => DEV_MIR_ENABLE,
441	C_OPB_AWIDTH => C_OPB_AWIDTH,
442	C_OPB_DWIDTH => C_OPB_DWIDTH,
443	C_FAMILY => C_FAMILY,
444	C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
445	C_DEV_BURST_ENABLE => DEV_BURST_ENABLE,
446	C_INCLUDE_ADDR_CNTR => INCLUDE_ADDR_CNTR,
447	C_INCLUDE_WR_BUF => INCLUDE_WR_BUF
448	)
449	port map
450	(
451	OPB_select => OPB_select,
452	OPB_DBus => OPB_DBus,
453	OPB_ABus => OPB_ABus,
454	OPB_BE => OPB_BE,
455	OPB_RNW => OPB_RNW,
456	OPB_seqAddr => OPB_seqAddr,
457	Sln_DBus => Sl_DBus,
458	Sln_xferAck => Sl_xferAck,
459	Sln_errAck => Sl_errAck,
460	Sln_retry => Sl_retry,
461	Sln_toutSup => Sl_toutSup,
462	Bus2IP_CS => iBus2IP_CS,
463	Bus2IP_CE => open,
464	Bus2IP_RdCE => iBus2IP_RdCE,
465	Bus2IP_WrCE => iBus2IP_WrCE,
466	Bus2IP_Data => iBus2IP_Data,
467	Bus2IP_Addr => iBus2IP_Addr,
468	Bus2IP_AddrValid => open,
469	Bus2IP_BE => iBus2IP_BE,
470	Bus2IP_RNW => iBus2IP_RNW,
471	Bus2IP_Burst => open,
472	IP2Bus_Data => iIP2Bus_Data,
473	IP2Bus_Ack => iIP2Bus_Ack,
474	IP2Bus_AddrAck => '0',
475	IP2Bus_Error => iIP2Bus_Error,
476	IP2Bus_Retry => iIP2Bus_Retry,
477	IP2Bus_ToutSup => iIP2Bus_ToutSup,
478	IP2Bus_PostedWrInh => iIP2Bus_PostedWrInh,
479	IP2RFIFO_Data => ZERO_IP2RFIFO_Data,
480	IP2RFIFO_WrMark => '0',
481	IP2RFIFO_WrRelease => '0',
482	IP2RFIFO_WrReq => '0',
483	IP2RFIFO_WrRestore => '0',
484	RFIFO2IP_AlmostFull => open,
485	RFIFO2IP_Full => open,
486	RFIFO2IP_Vacancy => open,
487	RFIFO2IP_WrAck => open,
488	IP2WFIFO_RdMark => '0',
489	IP2WFIFO_RdRelease => '0',
490	IP2WFIFO_RdReq => '0',
491	IP2WFIFO_RdRestore => '0',
492	WFIFO2IP_AlmostEmpty => open,
493	WFIFO2IP_Data => ZERO_WFIFO2IP_Data,
494	WFIFO2IP_Empty => open,
495	WFIFO2IP_Occupancy => open,
496	WFIFO2IP_RdAck => open,
497	IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent,
498	IP2INTC_Irpt => open,
499	Freeze => '0',
500	Bus2IP_Freeze => open,
501	OPB_Clk => OPB_Clk,
502	Bus2IP_Clk => iBus2IP_Clk,
503	IP2Bus_Clk => '0',
504	Reset => OPB_Rst,
505	Bus2IP_Reset => iBus2IP_Reset
506	);
507
508	------------------------------------------
509	-- instantiate the User Logic
510	------------------------------------------
511	USER_LOGIC_I : component user_logic
512	generic map
513	(
514	-- MAP USER GENERICS BELOW THIS LINE ---------------
515	--USER generics mapped here
516	-- MAP USER GENERICS ABOVE THIS LINE ---------------
517
518	C_DWIDTH => USER_DWIDTH,
519	C_NUM_CE => USER_NUM_CE,
520	C_AWIDTH => C_OPB_AWIDTH,
521	C_NUM_CS => USER_NUM_CS
522	)
523	port map
524	(
525	-- MAP USER PORTS BELOW THIS LINE ------------------
526	DQ0_T => DQ0_T,
527	DQ0_O => DQ0_O,
528	DQ0_I => DQ0_I,
529
530	DQ1_T => DQ1_T,
531	DQ1_O => DQ1_O,
532	DQ1_I => DQ1_I,
533
534	DQ2_T => DQ2_T,
535	DQ2_O => DQ2_O,
536	DQ2_I => DQ2_I,
537
538	DQ3_T => DQ3_T,
539	DQ3_O => DQ3_O,
540	DQ3_I => DQ3_I,
541
542	DQ4_T => DQ4_T,
543	DQ4_O => DQ4_O,
544	DQ4_I => DQ4_I,
545
546	DQ5_T => DQ5_T,
547	DQ5_O => DQ5_O,
548	DQ5_I => DQ5_I,
549
550	DQ6_T => DQ6_T,
551	DQ6_O => DQ6_O,
552	DQ6_I => DQ6_I,
553
554	DQ7_T => DQ7_T,
555	DQ7_O => DQ7_O,
556	DQ7_I => DQ7_I,
557	-- MAP USER PORTS ABOVE THIS LINE ------------------
558
559	Bus2IP_Clk => iBus2IP_Clk,
560	Bus2IP_Reset => iBus2IP_Reset,
561	Bus2IP_Addr => iBus2IP_Addr,
562	Bus2IP_Data => uBus2IP_Data,
563	Bus2IP_BE => uBus2IP_BE,
564	Bus2IP_RNW => iBus2IP_RNW,
565	Bus2IP_CS => uBus2IP_CS,
566	Bus2IP_RdCE => uBus2IP_RdCE,
567	Bus2IP_WrCE => uBus2IP_WrCE,
568	IP2Bus_Data => uIP2Bus_Data,
569	IP2Bus_Ack => iIP2Bus_Ack,
570	IP2Bus_Retry => iIP2Bus_Retry,
571	IP2Bus_Error => iIP2Bus_Error,
572	IP2Bus_ToutSup => iIP2Bus_ToutSup,
573	IP2Bus_PostedWrInh => uIP2Bus_PostedWrInh
574	);
575
576	------------------------------------------
577	-- hooking up signal slicing
578	------------------------------------------
579	uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1);
580	uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1);
581	uBus2IP_CS <= iBus2IP_CS(USER00_CS_INDEX to USER00_CS_INDEX+USER_NUM_CS-1);
582	uBus2IP_RdCE <= iBus2IP_RdCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1);
583	uBus2IP_WrCE <= iBus2IP_WrCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1);
584	iIP2Bus_PostedWrInh <= (others => uIP2Bus_PostedWrInh);
585	iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data;
586
587	end IMP;

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