1 | TABLE OF CONTENTS |
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2 | 1) Peripheral Summary |
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3 | 2) Description of Generated Files |
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4 | 3) Description of Used IPIC Signals |
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5 | 4) Description of Top Level Generics |
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6 | |
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7 | |
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8 | ================================================================================ |
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9 | * 1) Peripheral Summary * |
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10 | ================================================================================ |
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11 | Peripheral Summary: |
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12 | |
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13 | XPS project / EDK repository : C:\work\eeprom\MyProcessorIPLib |
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14 | logical library name : eeprom_v1_04_a |
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15 | top name : eeprom |
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16 | version : 1.04.a |
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17 | type : PLB (v4.6) slave |
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18 | features : slave attachment |
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19 | user memory spaces |
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20 | |
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21 | Address Block for User Logic and IPIF Predefined Services |
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22 | |
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23 | User logic memory space 0 : C_MEM0_BASEADDR |
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24 | : C_MEM0_HIGHADDR |
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25 | |
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26 | |
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27 | ================================================================================ |
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28 | * 2) Description of Generated Files * |
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29 | ================================================================================ |
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30 | - HDL source file(s) |
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31 | |
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32 | hdl/vhdl/eeprom.vhd |
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33 | |
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34 | This is the template file for your peripheral's top design entity. It |
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35 | configures and instantiates the corresponding design units in the way you |
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36 | indicated in the wizard GUI and hooks it up to the stub user logic where |
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37 | the actual functionalites should get implemented. You are not expected to |
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38 | modify this template file except certain marked places for adding user |
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39 | specific generics and ports. |
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40 | |
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41 | verilog/user_logic.v |
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42 | |
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43 | This is the template file for the stub user logic design entity, either in |
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44 | VHDL or Verilog, where the actual functionalities should get implemented. |
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45 | Some sample code snippet may be provided for demonstration purpose. |
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46 | |
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47 | - XPS interface file(s) |
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48 | |
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49 | data/eeprom_v2_1_0.mpd |
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50 | |
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51 | This Microprocessor Peripheral Description file contains information of the |
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52 | interface of your peripheral, so that other EDK tools can recognize your |
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53 | peripheral. |
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54 | |
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55 | data/eeprom_v2_1_0.pao |
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56 | |
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57 | This Peripheral Analysis Order file defines the analysis order of all the HDL |
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58 | source files that are used to compile your peripheral. |
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59 | |
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60 | - Other misc file(s) |
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61 | |
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62 | devl/ipwiz.opt |
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63 | |
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64 | This is the option setting file for the wizard batch mode, which should |
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65 | generate the same result as the wizard GUI mode. |
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66 | |
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67 | devl/README.txt |
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68 | |
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69 | This README file for your peripheral. |
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70 | |
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71 | devl/ipwiz.log |
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72 | |
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73 | This is the log file by operating on this wizard. |
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74 | |
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75 | |
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76 | ================================================================================ |
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77 | * 3) Description of Used IPIC Signals * |
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78 | ================================================================================ |
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79 | For more information (usage, timing diagrams, etc.) regarding the IPIC signals |
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80 | used in the templates, please refer to the following specifications (under |
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81 | %XILINX_EDK%\doc for windows or $XILINX_EDK/doc for solaris and linux): |
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82 | proc_ip_ref_guide.pdf - Processor IP Reference Guide (chapter 4 IPIF) |
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83 | user_core_templates_ref_guide.pdf - User Core Templates Reference Guide |
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84 | |
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85 | Bus2IP_Clk |
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86 | Synchronization clock provided to the user logic. All IPIC signals are |
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87 | synchronous to this clock. It is identical to the input <bus>_Clk signal of |
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88 | the peripheral. No additional buffering is provided on the clock; it is |
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89 | passed through as is. |
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90 | |
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91 | Bus2IP_Reset |
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92 | Active high reset for used by the user logic; it is asserted whenever the |
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93 | <bus>_Rst signal asserts or whenever there is a software-programmed reset |
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94 | (if the soft reset block is included). |
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95 | |
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96 | Bus2IP_Addr |
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97 | Address bus to the user logic indicating the desired address of the |
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98 | requested read or write operation. It can be used for additional address |
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99 | decoding or as input to addressable memory devices. |
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100 | |
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101 | Bus2IP_CS |
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102 | Active high chip select bus. Assertion of a chip select indicates an active |
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103 | transaction request to the chip select's target address space. Typically |
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104 | used for user logic memory space selection. |
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105 | |
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106 | Bus2IP_RNW |
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107 | This is an input signal to the user logic; it indicates the sense of a |
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108 | requested operation with the user logic. High is a read and low is a write. |
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109 | It is valid whenever at least one of the Bus2IP_CS bits is active. |
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110 | |
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111 | Bus2IP_Data |
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112 | Write data bus to the user logic. Write data is accepted by the user logic |
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113 | during a write operation by assertion of the write acknowledgement signal |
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114 | and the rising edge of the Bus2IP_Clk. |
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115 | |
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116 | Bus2IP_BE |
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117 | Byte Enable qualifiers for the requested read or write operation to the user |
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118 | logic. A bit in the Bus2IP_BE set to '1' indicates that the associated byte |
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119 | lane contains valid data. For example, if Bus2IP_BE = 0011, this indicates |
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120 | that byte lanes 2 and 3 contains valid data. |
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121 | |
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122 | IP2Bus_Data |
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123 | Output read data bus from the user logic; data is qualified with the |
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124 | assertion of IP2Bus_RdAck signal and the rising edge of the Bus2IP_Clk. |
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125 | |
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126 | IP2Bus_RdAck |
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127 | Active high read data qualifier providing the read acknowledgement from the |
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128 | user logic. Read data on the IP2Bus_Data bus is deemed valid at the rising |
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129 | edge of the Bus2IP_Clk and IP2Bus_RdAck asserted high by the user logic. For |
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130 | immediate acknowledgement (such as for a register read), this signal can be |
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131 | tied to '1'. Wait states can be inserted in the transaction by delaying the |
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132 | assertion of the acknowledgement. |
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133 | |
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134 | IP2Bus_WrAck |
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135 | Active high write data qualifier providing the write acknowledgement from |
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136 | the user logic. Write data on the Bus2IP_Data bus is deemed accepted by the |
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137 | user logic at the rising edge of the Bus2IP_Clk and IP2Bus_WrAck asserted |
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138 | high by the user logic. For immediate acknowledgement (such as for a |
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139 | register write), this signal can be tied to '1'. Wait states can be inserted |
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140 | in the transaction by delaying the assertion of the acknowledgement. |
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141 | |
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142 | IP2Bus_Error |
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143 | Active high signal indicating the user logic has encountered an error with |
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144 | the requested operation. It is asserted in conjunction with the read/write |
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145 | acknowledgement signal(s). |
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146 | |
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147 | ================================================================================ |
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148 | * 4) Description of Top Level Generics * |
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149 | ================================================================================ |
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150 | C_BASEADDR/C_HIGHADDR |
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151 | These two generics are used to define the memory mapped address space for |
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152 | the peripheral registers, including Soft Reset register, Interrupt Source |
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153 | Controller registers, Read/Write FIFO control/data registers, user logic |
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154 | software accessible registers and etc., but excluding those user logic |
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155 | memory spaces if ever existed. When instantiation, the address space |
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156 | size determined by these two generics must be a power of 2 (e.g. 2^k = |
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157 | C_HIGHADDR - C_BASEADDR + 1), a factor of C_BASEADDR and larger than the |
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158 | minimum size as indicated in the template. |
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159 | |
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160 | C_SPLB_AWIDTH |
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161 | This is the slave interface address bus width for Processor Local Bus |
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162 | version 4.6 (PLBv46). Value can be assigned automatically by EDK |
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163 | tooling during system creation. |
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164 | |
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165 | C_SPLB_DWIDTH |
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166 | This is the slave interface data bus width for Processor Local Bus |
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167 | version 4.6 (PLBv46). Value can be assigned automatically by EDK |
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168 | tooling during system creation. |
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169 | |
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170 | C_SPLB_NUM_MASTERS |
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171 | This indicates to the slave interface the number of PLBv46 masters |
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172 | present. Value can be assigned automatically by EDK tooling during |
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173 | system creation. |
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174 | |
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175 | C_SPLB_MID_WIDTH |
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176 | This indicates to the slave interface the number of bits required |
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177 | for the PLB_masterID input bus. It is an integer value equal to |
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178 | log2(C_SPLB_NUM_MASTERS). Value will be assigned automatically by |
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179 | EDK tooling during system creation. |
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180 | |
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181 | C_SPLB_NATIVE_DWIDTH |
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182 | This indicates to the slave interface the native bit width of the |
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183 | internal data bus of the peripheral. Some peripheral will require |
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184 | the value of this parameter to be fixed, while others might have |
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185 | selectable native data widths. |
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186 | |
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187 | C_SPLB_P2P |
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188 | This indicates to the slave interface when it is exclusively attached |
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189 | to a PLBv46 bus via a Point to Point interconnect scheme. In this |
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190 | scenario, the slave interface may be able to reduce resource utilization |
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191 | by eliminating address decode function and modifying interface behavior |
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192 | to allow for a reduction in latency. |
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193 | |
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194 | C_SPLB_SUPPORT_BURSTS |
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195 | This indicates to the associated PLBv46 bus that this slave interface |
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196 | support burst transfers to improve performance. |
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197 | |
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198 | C_SPLB_SMALLEST_MASTER |
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199 | This indicates the smallest native data width of any master on the |
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200 | corresponding PLBv46 bus that may access the slave interface. It allows |
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201 | optimizations within the slave interface logic if narrower masters don't |
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202 | have to be supported for that application. |
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203 | |
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204 | C_SPLB_CLK_PERIOD_PS |
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205 | This is the period of the PLBv46 bus clock (in picoseconds) for the |
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206 | corresponding PLBv46 slave interface attachment. It has been defined |
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207 | for use by peripheral that needs to know the bus clock rate to improve |
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208 | certain functions such as internal timers. |
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209 | |
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210 | C_INCLUDE_DPHASE_TIMER |
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211 | This indicates if the data phase timer is used or not. The value of |
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212 | 0 will exclude the timer. The value of 1 includes the timer. |
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213 | If C_INCLUDE_DPHASE_TIMER = 1 and after 128 SPLB_Clk cycles, as |
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214 | measured from the assertion of Sl_AddrAck, the User IP does not |
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215 | respond with either an IP2Bus_RdAck or IP2Bus_WrAck the |
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216 | plbv46_slave_single will de-assert the User IP cycle request |
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217 | signals, Bus2IP_CS and Bus2IP_RdCE or Bus2IP_WrCE, and will assert |
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218 | Sl_rdDAck with Sl_rdDBus=zero for a read cycle or Sl_wrDAck for |
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219 | a write cycle. This will gracefully terminate the cycle. Note |
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220 | that the requesting master will have no knowledge that the data |
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221 | phase of the PLB request was terminated in this manner. |
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222 | |
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223 | C_FAMILY |
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224 | This is to set the target FPGA architecture, s.t. virtex5, etc. |
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225 | |
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226 | C_MEMn_BASEADDR/C_MEMn_HIGHADDR (n = 0, 1, 2, etc.) |
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227 | These two generics are used to define the memory mapped address space for |
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228 | user logic memory space n, which are typically used in peripherals like |
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229 | memory controllers, bridges, that need to access memory blocks other |
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230 | than local register space. When instantiation, the address space size |
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231 | determined by these two generics should be a power of 2 (e.g. 2^k = |
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232 | C_MEMn_HIGHADDR - C_MEMn_BASEADDR + 1) and a factor of C_MEMn_BASEADDR. |
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233 | |
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234 | ================================================================================ |
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235 | * 5) Location to documentation of dependent libraries * |
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236 | * * |
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237 | * In general, the documentation is located under: * |
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238 | * $XILINX_EDK/hw/XilinxProcessorIPLib/pcores/$libName/doc * |
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239 | * * |
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240 | ================================================================================ |
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241 | proc_common_v2_00_a |
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242 | No documentation for this library |
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243 | |
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244 | plbv46_slave_single_v1_00_a |
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245 | C:\Xilinx_10.1\EDK\bin\nt\C:\Xilinx_10.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_single_v1_00_a\doc\plbv46_slave_single.pdf |
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246 | |
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