| 1 | |
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| 2 | ---------------------------------------------------------------------------- |
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| 3 | -- Design Analysis -- |
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| 4 | ---------------------------------------------------------------------------- |
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| 5 | Analyze pcore eeprom ... |
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| 6 | |
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| 7 | INFO:MDT - Generic parameter C_BASEADDR/C_HIGHADDR will not be used since user |
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| 8 | does not have any register space ... |
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| 9 | |
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| 10 | ---------------------------------------------------------------------------- |
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| 11 | -- Design Analysis -- |
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| 12 | ---------------------------------------------------------------------------- |
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| 13 | Analyze pcore eeprom ... |
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| 14 | |
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| 15 | INFO:MDT - Generic parameter C_BASEADDR/C_HIGHADDR will not be used since user |
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| 16 | does not have any register space ... |
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| 17 | |
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| 18 | ---------------------------------------------------------------------------- |
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| 19 | -- File Generation -- |
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| 20 | ---------------------------------------------------------------------------- |
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| 21 | Creating HDL source directory ... |
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| 22 | Generating top peripheral VHDL template ... |
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| 23 | Generating stub user logic Verilog template ... |
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| 24 | HDL templates successfully generated ... |
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| 25 | Creating data directory ... |
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| 26 | Generating XPS inteface files ... |
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| 27 | WARNING:HDLParsers:3497 - Ignoring Verilog File |
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| 28 | "C:/work/eeprom/MyProcessorIPLib/pcores/eeprom_v1_04_a/data/../hdl/verilog/us |
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| 29 | er_logic.v" |
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| 30 | Compiling vhdl file |
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| 31 | "C:/Xilinx_10.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ |
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| 32 | proc_common_pkg.vhd" in Library proc_common_v2_00_a. |
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| 33 | Package <proc_common_pkg> compiled. |
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| 34 | Package body <proc_common_pkg> compiled. |
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| 35 | Compiling vhdl file |
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| 36 | "C:/Xilinx_10.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ |
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| 37 | or_muxcy.vhd" in Library proc_common_v2_00_a. |
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| 38 | Entity <or_muxcy> compiled. |
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| 39 | Entity <or_muxcy> (Architecture <implementation>) compiled. |
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| 40 | Compiling vhdl file |
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| 41 | "C:/Xilinx_10.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ |
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| 42 | family_support.vhd" in Library proc_common_v2_00_a. |
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| 43 | Package <family_support> compiled. |
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| 44 | Package body <family_support> compiled. |
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| 45 | Compiling vhdl file |
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| 46 | "C:/Xilinx_10.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ |
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| 47 | counter_f.vhd" in Library proc_common_v2_00_a. |
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| 48 | Entity <counter_f> compiled. |
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| 49 | Entity <counter_f> (Architecture <imp>) compiled. |
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| 50 | Compiling vhdl file |
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| 51 | "C:/Xilinx_10.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ |
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| 52 | pselect_f.vhd" in Library proc_common_v2_00_a. |
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| 53 | Entity <pselect_f> compiled. |
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| 54 | Entity <pselect_f> (Architecture <imp>) compiled. |
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| 55 | Compiling vhdl file |
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| 56 | "C:/Xilinx_10.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ |
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| 57 | or_gate128.vhd" in Library proc_common_v2_00_a. |
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| 58 | Entity <or_gate128> compiled. |
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| 59 | Entity <or_gate128> (Architecture <imp>) compiled. |
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| 60 | Compiling vhdl file |
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| 61 | "C:/Xilinx_10.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ |
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| 62 | ipif_pkg.vhd" in Library proc_common_v2_00_a. |
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| 63 | Package <ipif_pkg> compiled. |
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| 64 | Package body <ipif_pkg> compiled. |
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| 65 | Compiling vhdl file |
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| 66 | "C:/Xilinx_10.1/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_00_a/h |
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| 67 | dl/vhdl/plb_address_decoder.vhd" in Library plbv46_slave_single_v1_00_a. |
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| 68 | Entity <plb_address_decoder> compiled. |
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| 69 | Entity <plb_address_decoder> (Architecture <IMP>) compiled. |
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| 70 | Compiling vhdl file |
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| 71 | "C:/Xilinx_10.1/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_00_a/h |
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| 72 | dl/vhdl/plb_slave_attachment.vhd" in Library plbv46_slave_single_v1_00_a. |
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| 73 | Entity <plb_slave_attachment> compiled. |
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| 74 | Entity <plb_slave_attachment> (Architecture <implementation>) compiled. |
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| 75 | Compiling vhdl file |
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| 76 | "C:/Xilinx_10.1/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_00_a/h |
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| 77 | dl/vhdl/plbv46_slave_single.vhd" in Library plbv46_slave_single_v1_00_a. |
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| 78 | Entity <plbv46_slave_single> compiled. |
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| 79 | Entity <plbv46_slave_single> (Architecture <implementation>) compiled. |
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| 80 | Compiling vhdl file |
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| 81 | "C:/work/eeprom/MyProcessorIPLib/pcores/eeprom_v1_04_a/data/../hdl/vhdl/eeprom.v |
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| 82 | hd" in Library eeprom_v1_04_a. |
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| 83 | Entity <eeprom> compiled. |
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| 84 | Entity <eeprom> (Architecture <IMP>) compiled. |
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| 85 | |
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| 86 | |
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| 87 | Analyzing HDL attributes ... |
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| 88 | INFO:MDT - IPTYPE set to value : PERIPHERAL |
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| 89 | INFO:MDT - IMP_NETLIST set to value : TRUE |
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| 90 | INFO:MDT - HDL set to value : VHDL |
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| 91 | WARNING:MDT - Unable to delete temparary XST project file |
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| 92 | C:\work\eeprom\MyProcessorIPLib\pcores\eeprom_v1_04_a\data\_eeprom_xst.prj : |
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| 93 | 13 |
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| 94 | XPS interface files successfully generated ... |
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| 95 | Creating development directory ... |
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| 96 | Generating command option file ... |
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| 97 | Generating readme file ... |
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| 98 | Development misc files successfully generated ... |
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| 99 | No ProjNavigator support files will be generated at this time ... |
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| 100 | No XST synthesis support files will be generated at this time ... |
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| 101 | No BFM simulation files will be generated at this time ... |
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| 102 | No software driver files will be generated at this time ... |
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| 103 | |
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| 104 | ---------------------------------------------------------------------------- |
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| 105 | -- Final Report -- |
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| 106 | ---------------------------------------------------------------------------- |
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| 107 | Thank you for using Create and Import Peripheral Wizard! Please find your |
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| 108 | peripheral hardware templates under |
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| 109 | C:\work\eeprom\MyProcessorIPLib/pcores/eeprom_v1_04_a. |
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| 110 | |
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| 111 | Peripheral Summary: |
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| 112 | |
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| 113 | top name : eeprom |
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| 114 | version : 1.04.a |
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| 115 | type : PLB (v4.6) slave |
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| 116 | features : slave attachment |
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| 117 | user memory spaces |
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| 118 | |
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| 119 | Address Block Summary: |
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| 120 | |
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| 121 | user memory 0 : C_MEM0_BASEADDR |
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| 122 | : C_MEM0_HIGHADDR |
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| 123 | |
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| 124 | File Summary |
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| 125 | |
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| 126 | - HDL source - |
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| 127 | C:\work\eeprom\MyProcessorIPLib/pcores/eeprom_v1_04_a/hdl |
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| 128 | top entity : vhdl/eeprom.vhd |
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| 129 | user logic : verilog/user_logic.v |
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| 130 | |
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| 131 | - XPS interface - |
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| 132 | C:\work\eeprom\MyProcessorIPLib/pcores/eeprom_v1_04_a/data |
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| 133 | mpd : eeprom_v2_1_0.mpd |
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| 134 | pao : eeprom_v2_1_0.pao |
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| 135 | |
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| 136 | - Misc file - |
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| 137 | C:\work\eeprom\MyProcessorIPLib/pcores/eeprom_v1_04_a/devl |
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| 138 | help : README.txt |
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| 139 | option : ipwiz.opt |
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| 140 | log : ipwiz.log |
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| 141 | |
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| 142 | |
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