1 | ################################################################### |
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2 | ## |
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3 | ## Name : linkport |
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4 | ## Desc : Microprocessor Peripheral Description |
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5 | ## : Automatically generated by PsfUtility |
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6 | ## |
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7 | ################################################################### |
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8 | |
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9 | BEGIN linkport |
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10 | |
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11 | ## Peripheral Options |
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12 | OPTION IPTYPE = PERIPHERAL |
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13 | OPTION IMP_NETLIST = TRUE |
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14 | OPTION HDL = VHDL |
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15 | OPTION USAGE_LEVEL = BASE_USER |
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16 | OPTION ARCH_SUPPORT_MAP = (virtex2p=PREFERRED, virtex4=PREFERRED, others=AVAILABLE) |
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17 | OPTION IP_GROUP = USER |
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18 | OPTION STYLE = MIX |
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19 | OPTION RUN_NGCBUILD = TRUE |
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20 | |
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21 | IO_INTERFACE IO_IF = mgt_linkport1_0, IO_TYPE = WARP_MGTLINKPORT1_V1 |
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22 | |
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23 | ## Bus Interfaces |
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24 | |
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25 | ## Generics for VHDL or Parameters for Verilog |
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26 | |
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27 | ## Ports |
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28 | PORT tx_data = "", DIR = I, VEC = [15:0] |
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29 | PORT tx_clk = "", DIR = I |
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30 | PORT tx_wr = "", DIR = I |
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31 | PORT tx_first = "", DIR = I |
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32 | PORT tx_last = "", DIR = I |
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33 | PORT tx_rdy = "", DIR = O |
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34 | PORT link_en = "", DIR = I |
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35 | PORT rx_clk = "", DIR = I |
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36 | PORT rx_drdy = "", DIR = O |
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37 | PORT rx_first = "", DIR = O |
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38 | PORT rx_last = "", DIR = O |
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39 | PORT rx_data = "", DIR = O, VEC = [15:0] |
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40 | PORT fc_req = "", DIR = I |
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41 | PORT fc_nb = "", DIR = I, VEC = [3:0] |
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42 | PORT fc_ack = "", DIR = O |
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43 | PORT top_ref_clk_i = mgt_top_ref_clk, DIR = I |
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44 | PORT user_clk_i = mgt_usr_clk, DIR = I |
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45 | PORT mgt_rxp = "", DIR = I , IO_IS = rec_pos |
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46 | PORT mgt_rxn = "", DIR = I , IO_IS = rec_neg |
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47 | PORT mgt_txn = "", DIR = O , IO_IS = trans_neg |
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48 | PORT mgt_txp = "", DIR = O , IO_IS = trans_pos |
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49 | PORT grst = "", DIR = I |
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50 | PORT mgt_pwdn = "", DIR = I |
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51 | |
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52 | END |
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