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source: PlatformSupport/Deprecated/pcores/linkport_v1_00_a/hdl/vhdl/aurora_16b.vhd

Last change on this file was 408, checked in by haijiang, 18 years ago

File size: 37.1 KB

Line
1	--
2	-- Project: Aurora Module Generator version 2.4
3	--
4	-- Date: $Date: 2005/11/21 23:26:37 $
5	-- Tag: $Name: i+IP+98818 $
6	-- File: $RCSfile: aurora_vhd.ejava,v $
7	-- Rev: $Revision: 1.1.2.3 $
8	--
9	-- Company: Xilinx
10	-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
11	--
12	-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
13	-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
14	-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
15	-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
16	-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
17	-- APPLICATION OR STANDARD, XILINX IS MAKING NO
18	-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
19	-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
20	-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
21	-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
22	-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
23	-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
24	-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
25	-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
26	-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
27	-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28	-- PURPOSE.
29	--
30	-- (c) Copyright 2004 Xilinx, Inc.
31	-- All rights reserved.
32	--
33
34	--
35	-- aurora_16b
36	--
37	-- Author: Nigel Gulstone
38	-- Xilinx - Embedded Networking System Engineering Group
39	--
40	-- VHDL Translation: Brian Woodard
41	-- Xilinx - Garden Valley Design Team
42	--
43	-- Description: This is the top level module for a 1 2-byte lane Aurora
44	-- reference design module. This module supports the following features:
45	--
46	-- * Immediate Mode Native Flow Control
47	-- * Supports Virtex 2 Pro
48	--
49
50	library IEEE;
51	use IEEE.STD_LOGIC_1164.all;
52
53	-- synthesis translate_off
54	library UNISIM;
55	use UNISIM.all;
56	-- synthesis translate_on
57
58	entity aurora_16b is
59	generic (
60	EXTEND_WATCHDOGS : boolean := FALSE
61	);
62	port (
63
64	-- LocalLink TX Interface
65
66	TX_D : in std_logic_vector(0 to 15);
67	TX_REM : in std_logic;
68	TX_SRC_RDY_N : in std_logic;
69	TX_SOF_N : in std_logic;
70	TX_EOF_N : in std_logic;
71	TX_DST_RDY_N : out std_logic;
72
73	-- LocalLink RX Interface
74
75	RX_D : out std_logic_vector(0 to 15);
76	RX_REM : out std_logic;
77	RX_SRC_RDY_N : out std_logic;
78	RX_SOF_N : out std_logic;
79	RX_EOF_N : out std_logic;
80
81	-- Native Flow Control Interface
82
83	NFC_REQ_N : in std_logic;
84	NFC_NB : in std_logic_vector(0 to 3);
85	NFC_ACK_N : out std_logic;
86
87	-- MGT Serial I/O
88
89	RXP : in std_logic;
90	RXN : in std_logic;
91
92	TXP : out std_logic;
93	TXN : out std_logic;
94
95	-- MGT Reference Clock Interface
96
97	TOP_BREF_CLK : in std_logic;
98
99	-- Error Detection Interface
100
101	HARD_ERROR : out std_logic;
102	SOFT_ERROR : out std_logic;
103	FRAME_ERROR : out std_logic;
104
105	-- Status
106
107	CHANNEL_UP : out std_logic;
108	LANE_UP : out std_logic;
109
110	-- Clock Compensation Control Interface
111
112	WARN_CC : in std_logic;
113	DO_CC : in std_logic;
114
115	-- System Interface
116
117	DCM_NOT_LOCKED : in std_logic;
118	USER_CLK : in std_logic;
119	RESET : in std_logic;
120	POWER_DOWN : in std_logic;
121	LOOPBACK : in std_logic_vector(1 downto 0)
122
123	);
124
125	end aurora_16b;
126
127	architecture MAPPED of aurora_16b is
128
129	-- External Register Declarations --
130
131	signal TX_DST_RDY_N_Buffer : std_logic;
132	signal RX_D_Buffer : std_logic_vector(0 to 15);
133	signal RX_REM_Buffer : std_logic;
134	signal RX_SRC_RDY_N_Buffer : std_logic;
135	signal RX_SOF_N_Buffer : std_logic;
136	signal RX_EOF_N_Buffer : std_logic;
137	signal NFC_ACK_N_Buffer : std_logic;
138	signal TXP_Buffer : std_logic;
139	signal TXN_Buffer : std_logic;
140	signal HARD_ERROR_Buffer : std_logic;
141	signal SOFT_ERROR_Buffer : std_logic;
142	signal FRAME_ERROR_Buffer : std_logic;
143	signal CHANNEL_UP_Buffer : std_logic;
144	signal LANE_UP_Buffer : std_logic;
145
146	-- Wire Declarations --
147
148	signal rx_data_i : std_logic_vector(15 downto 0);
149	signal rx_not_in_table_i : std_logic_vector(1 downto 0);
150	signal rx_disp_err_i : std_logic_vector(1 downto 0);
151	signal rx_char_is_k_i : std_logic_vector(1 downto 0);
152	signal rx_char_is_comma_i : std_logic_vector(1 downto 0);
153	signal rx_buf_status_i : std_logic;
154	signal tx_buf_err_i : std_logic;
155	signal tx_k_err_i : std_logic_vector(1 downto 0);
156	signal rx_clk_cor_cnt_i : std_logic_vector(2 downto 0);
157	signal rx_realign_i : std_logic;
158
159	signal rx_polarity_i : std_logic;
160	signal rx_reset_i : std_logic;
161	signal tx_char_is_k_i : std_logic_vector(1 downto 0);
162	signal tx_data_i : std_logic_vector(15 downto 0);
163	signal tx_reset_i : std_logic;
164
165	signal ena_comma_align_i : std_logic;
166
167	signal gen_scp_i : std_logic;
168	signal gen_snf_i : std_logic;
169	signal fc_nb_i : std_logic_vector(0 to 3);
170
171	signal gen_ecp_i : std_logic;
172	signal gen_pad_i : std_logic;
173	signal tx_pe_data_i : std_logic_vector(0 to 15);
174	signal tx_pe_data_v_i : std_logic;
175	signal gen_cc_i : std_logic;
176
177	signal rx_pad_i : std_logic;
178	signal rx_pe_data_i : std_logic_vector(0 to 15);
179	signal rx_pe_data_v_i : std_logic;
180	signal rx_scp_i : std_logic;
181	signal rx_ecp_i : std_logic;
182	signal rx_snf_i : std_logic;
183	signal rx_fc_nb_i : std_logic_vector(0 to 3);
184
185	signal gen_a_i : std_logic;
186	signal gen_k_i : std_logic_vector(0 to 1);
187	signal gen_r_i : std_logic_vector(0 to 1);
188	signal gen_v_i : std_logic_vector(0 to 1);
189
190	signal lane_up_i : std_logic;
191	signal soft_error_i : std_logic;
192	signal hard_error_i : std_logic;
193	signal channel_bond_load_i : std_logic;
194	signal got_a_i : std_logic_vector(0 to 1);
195	signal got_v_i : std_logic;
196
197	signal reset_lanes_i : std_logic;
198
199	signal rx_rec_clk_i : std_logic;
200	signal ena_calign_rec_i : std_logic;
201
202	signal txcharisk_lane_0_i : std_logic_vector(3 downto 0);
203	signal txdata_lane_0_i : std_logic_vector(31 downto 0);
204	signal refclksel_lane_0_i : std_logic;
205	signal txbypass8b10b_lane_0_i : std_logic_vector(3 downto 0);
206	signal txchardispmode_lane_0_i : std_logic_vector(3 downto 0);
207	signal txchardispval_lane_0_i : std_logic_vector(3 downto 0);
208	signal configenable_lane_0_i : std_logic;
209	signal configin_lane_0_i : std_logic;
210	signal txforcecrcerr_lane_0_i : std_logic;
211	signal txinhibit_lane_0_i : std_logic;
212	signal txpolarity_lane_0_i : std_logic;
213
214	signal rxdata_lane_0_i : std_logic_vector(31 downto 0);
215	signal rxnotintable_lane_0_i : std_logic_vector(3 downto 0);
216	signal rxdisperr_lane_0_i : std_logic_vector(3 downto 0);
217	signal rxcharisk_lane_0_i : std_logic_vector(3 downto 0);
218	signal rxchariscomma_lane_0_i : std_logic_vector(3 downto 0);
219	signal rxbufstatus_lane_0_i : std_logic_vector(1 downto 0);
220	signal txkerr_lane_0_i : std_logic_vector(3 downto 0);
221
222	signal ch_bond_done_i : std_logic;
223	signal en_chan_sync_i : std_logic;
224	signal channel_up_i : std_logic;
225	signal start_rx_i : std_logic;
226	signal tx_wait_i : std_logic;
227	signal decrement_nfc_i : std_logic;
228
229	signal chbondi_not_used_i : std_logic_vector(3 downto 0);
230	signal chbondo_not_used_i : std_logic_vector(3 downto 0);
231
232	signal tied_to_ground_i : std_logic;
233	signal tied_to_vcc_i : std_logic;
234	signal system_reset_c : std_logic;
235	signal fc_nb_not_used_i : std_logic_vector(0 to 3);
236
237
238	-- Component Declarations --
239
240
241	component FD
242
243	generic (INIT : bit := '0');
244
245	port (
246
247	Q : out std_ulogic;
248	C : in std_ulogic;
249	D : in std_ulogic
250
251	);
252
253	end component;
254
255
256	component AURORA_LANE
257	generic (
258	EXTEND_WATCHDOGS : boolean := FALSE
259	);
260	port (
261
262	-- MGT Interface
263
264	RX_DATA : in std_logic_vector(15 downto 0); -- 2-byte data bus from the MGT.
265	RX_NOT_IN_TABLE : in std_logic_vector(1 downto 0); -- Invalid 10-bit code was recieved.
266	RX_DISP_ERR : in std_logic_vector(1 downto 0); -- Disparity error detected on RX interface.
267	RX_CHAR_IS_K : in std_logic_vector(1 downto 0); -- Indicates which bytes of RX_DATA are control.
268	RX_CHAR_IS_COMMA : in std_logic_vector(1 downto 0); -- Comma received on given byte.
269	RX_BUF_STATUS : in std_logic; -- Overflow/Underflow of RX buffer detected.
270	TX_BUF_ERR : in std_logic; -- Overflow/Underflow of TX buffer detected.
271	TX_K_ERR : in std_logic_vector(1 downto 0); -- Attempt to send bad control byte detected.
272	RX_CLK_COR_CNT : in std_logic_vector(2 downto 0); -- Value used to determine channel bonding status.
273	RX_REALIGN : in std_logic; -- SERDES was realigned because of a new comma.
274	RX_POLARITY : out std_logic; -- Controls interpreted polarity of serial data inputs.
275	RX_RESET : out std_logic; -- Reset RX side of MGT logic.
276	TX_CHAR_IS_K : out std_logic_vector(1 downto 0); -- TX_DATA byte is a control character.
277	TX_DATA : out std_logic_vector(15 downto 0); -- 2-byte data bus to the MGT.
278	TX_RESET : out std_logic; -- Reset TX side of MGT logic.
279
280	-- Comma Detect Phase Align Interface
281
282	ENA_COMMA_ALIGN : out std_logic; -- Request comma alignment.
283
284	-- TX_LL Interface
285
286	GEN_SCP : in std_logic; -- SCP generation request from TX_LL.
287	GEN_ECP : in std_logic; -- ECP generation request from TX_LL.
288	GEN_SNF : in std_logic; -- SNF generation request from TX_LL.
289	GEN_PAD : in std_logic; -- PAD generation request from TX_LL.
290	FC_NB : in std_logic_vector(0 to 3); -- Size code for SUF and SNF messages.
291	TX_PE_DATA : in std_logic_vector(0 to 15); -- Data from TX_LL to send over lane.
292	TX_PE_DATA_V : in std_logic; -- Indicates TX_PE_DATA is Valid.
293	GEN_CC : in std_logic; -- CC generation request from TX_LL.
294
295	-- RX_LL Interface
296
297	RX_PAD : out std_logic; -- Indicates lane received PAD.
298	RX_PE_DATA : out std_logic_vector(0 to 15); -- RX data from lane to RX_LL.
299	RX_PE_DATA_V : out std_logic; -- RX_PE_DATA is data, not control symbol.
300	RX_SCP : out std_logic; -- Indicates lane received SCP.
301	RX_ECP : out std_logic; -- Indicates lane received ECP.
302	RX_SNF : out std_logic; -- Indicates lane received SNF.
303	RX_FC_NB : out std_logic_vector(0 to 3); -- Size code for SNF or SUF.
304
305	-- Global Logic Interface
306
307	GEN_A : in std_logic; -- 'A character' generation request from Global Logic.
308	GEN_K : in std_logic_vector(0 to 1); -- 'K character' generation request from Global Logic.
309	GEN_R : in std_logic_vector(0 to 1); -- 'R character' generation request from Global Logic.
310	GEN_V : in std_logic_vector(0 to 1); -- Verification data generation request.
311	LANE_UP : out std_logic; -- Lane is ready for bonding and verification.
312	SOFT_ERROR : out std_logic; -- Soft error detected.
313	HARD_ERROR : out std_logic; -- Hard error detected.
314	CHANNEL_BOND_LOAD : out std_logic; -- Channel Bonding done code received.
315	GOT_A : out std_logic_vector(0 to 1); -- Indicates lane recieved 'A character' bytes.
316	GOT_V : out std_logic; -- Verification symbols received.
317
318	-- System Interface
319
320	USER_CLK : in std_logic; -- System clock for all non-MGT Aurora Logic.
321	RESET : in std_logic -- Reset the lane.
322
323	);
324
325	end component;
326
327
328	component PHASE_ALIGN
329
330	port (
331
332	-- Aurora Lane Interface
333
334	ENA_COMMA_ALIGN : in std_logic;
335
336	-- MGT Interface
337
338	RX_REC_CLK : in std_logic;
339	ENA_CALIGN_REC : out std_logic
340
341	);
342
343	end component;
344
345
346	component GT_CUSTOM
347
348	generic (ALIGN_COMMA_MSB : boolean;
349	CHAN_BOND_MODE : string;
350	CHAN_BOND_ONE_SHOT : boolean;
351	CHAN_BOND_SEQ_1_1 : bit_vector;
352	REF_CLK_V_SEL : integer;
353	CLK_COR_INSERT_IDLE_FLAG : boolean;
354	CLK_COR_KEEP_IDLE : boolean;
355	CLK_COR_REPEAT_WAIT : integer;
356	CLK_COR_SEQ_1_1 : bit_vector;
357	CLK_COR_SEQ_1_2 : bit_vector;
358	CLK_COR_SEQ_2_USE : boolean;
359	CLK_COR_SEQ_LEN : integer;
360	CLK_CORRECT_USE : boolean;
361	COMMA_10B_MASK : bit_vector;
362	MCOMMA_10B_VALUE : bit_vector;
363	PCOMMA_10B_VALUE : bit_vector;
364	RX_CRC_USE : boolean;
365	RX_DATA_WIDTH : integer;
366	RX_LOSS_OF_SYNC_FSM : boolean;
367	RX_LOS_INVALID_INCR : integer;
368	RX_LOS_THRESHOLD : integer;
369	SERDES_10B : boolean;
370	TERMINATION_IMP : integer;
371	TX_CRC_USE : boolean;
372	TX_DATA_WIDTH : integer;
373	TX_DIFF_CTRL : integer;
374	TX_PREEMPHASIS : integer);
375
376	port (
377
378	CHBONDDONE : out std_logic;
379	CHBONDO : out std_logic_vector(3 downto 0);
380	CONFIGOUT : out std_logic;
381	RXBUFSTATUS : out std_logic_vector(1 downto 0);
382	RXCHARISCOMMA : out std_logic_vector(3 downto 0);
383	RXCHARISK : out std_logic_vector(3 downto 0);
384	RXCHECKINGCRC : out std_logic;
385	RXCLKCORCNT : out std_logic_vector(2 downto 0);
386	RXCOMMADET : out std_logic;
387	RXCRCERR : out std_logic;
388	RXDATA : out std_logic_vector(31 downto 0);
389	RXDISPERR : out std_logic_vector(3 downto 0);
390	RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
391	RXNOTINTABLE : out std_logic_vector(3 downto 0);
392	RXREALIGN : out std_logic;
393	RXRECCLK : out std_logic;
394	RXRUNDISP : out std_logic_vector(3 downto 0);
395	TXBUFERR : out std_logic;
396	TXKERR : out std_logic_vector(3 downto 0);
397	TXN : out std_logic;
398	TXP : out std_logic;
399	TXRUNDISP : out std_logic_vector(3 downto 0);
400	BREFCLK : in std_logic;
401	BREFCLK2 : in std_logic;
402	CHBONDI : in std_logic_vector(3 downto 0);
403	CONFIGENABLE : in std_logic;
404	CONFIGIN : in std_logic;
405	ENCHANSYNC : in std_logic;
406	ENMCOMMAALIGN : in std_logic;
407	ENPCOMMAALIGN : in std_logic;
408	LOOPBACK : in std_logic_vector(1 downto 0);
409	POWERDOWN : in std_logic;
410	REFCLK : in std_logic;
411	REFCLK2 : in std_logic;
412	REFCLKSEL : in std_logic;
413	RXN : in std_logic;
414	RXP : in std_logic;
415	RXPOLARITY : in std_logic;
416	RXRESET : in std_logic;
417	RXUSRCLK : in std_logic;
418	RXUSRCLK2 : in std_logic;
419	TXBYPASS8B10B : in std_logic_vector(3 downto 0);
420	TXCHARDISPMODE : in std_logic_vector(3 downto 0);
421	TXCHARDISPVAL : in std_logic_vector(3 downto 0);
422	TXCHARISK : in std_logic_vector(3 downto 0);
423	TXDATA : in std_logic_vector(31 downto 0);
424	TXFORCECRCERR : in std_logic;
425	TXINHIBIT : in std_logic;
426	TXPOLARITY : in std_logic;
427	TXRESET : in std_logic;
428	TXUSRCLK : in std_logic;
429	TXUSRCLK2 : in std_logic
430
431	);
432
433	end component;
434
435	-- attribute syn_black_box of GT_CUSTOM : component is true;
436
437
438	component GLOBAL_LOGIC
439	generic (
440	EXTEND_WATCHDOGS : boolean := FALSE
441	);
442	port (
443
444	-- MGT Interface
445
446	CH_BOND_DONE : in std_logic;
447	EN_CHAN_SYNC : out std_logic;
448
449	-- Aurora Lane Interface
450
451	LANE_UP : in std_logic;
452	SOFT_ERROR : in std_logic;
453	HARD_ERROR : in std_logic;
454	CHANNEL_BOND_LOAD : in std_logic;
455	GOT_A : in std_logic_vector(0 to 1);
456	GOT_V : in std_logic;
457	GEN_A : out std_logic;
458	GEN_K : out std_logic_vector(0 to 1);
459	GEN_R : out std_logic_vector(0 to 1);
460	GEN_V : out std_logic_vector(0 to 1);
461	RESET_LANES : out std_logic;
462
463	-- System Interface
464
465	USER_CLK : in std_logic;
466	RESET : in std_logic;
467	POWER_DOWN : in std_logic;
468	CHANNEL_UP : out std_logic;
469	START_RX : out std_logic;
470	CHANNEL_SOFT_ERROR : out std_logic;
471	CHANNEL_HARD_ERROR : out std_logic
472
473	);
474
475	end component;
476
477
478	component TX_LL
479
480	port (
481
482	-- LocalLink PDU Interface
483
484	TX_D : in std_logic_vector(0 to 15);
485	TX_REM : in std_logic;
486	TX_SRC_RDY_N : in std_logic;
487	TX_SOF_N : in std_logic;
488	TX_EOF_N : in std_logic;
489	TX_DST_RDY_N : out std_logic;
490
491	-- NFC Interface
492
493	NFC_REQ_N : in std_logic;
494	NFC_NB : in std_logic_vector(0 to 3);
495	NFC_ACK_N : out std_logic;
496
497	-- Clock Compensation Interface
498
499	WARN_CC : in std_logic;
500	DO_CC : in std_logic;
501
502	-- Global Logic Interface
503
504	CHANNEL_UP : in std_logic;
505
506	-- Aurora Lane Interface
507
508	GEN_SCP : out std_logic;
509	GEN_ECP : out std_logic;
510	GEN_SNF : out std_logic;
511	FC_NB : out std_logic_vector(0 to 3);
512	TX_PE_DATA_V : out std_logic;
513	GEN_PAD : out std_logic;
514	TX_PE_DATA : out std_logic_vector(0 to 15);
515	GEN_CC : out std_logic;
516
517	-- RX_LL Interface
518
519	TX_WAIT : in std_logic;
520	DECREMENT_NFC : out std_logic;
521
522	-- System Interface
523
524	USER_CLK : in std_logic
525
526	);
527
528	end component;
529
530
531	component RX_LL
532
533	port (
534
535	-- LocalLink PDU Interface
536
537	RX_D : out std_logic_vector(0 to 15);
538	RX_REM : out std_logic;
539	RX_SRC_RDY_N : out std_logic;
540	RX_SOF_N : out std_logic;
541	RX_EOF_N : out std_logic;
542
543	-- Global Logic Interface
544
545	START_RX : in std_logic;
546
547	-- Aurora Lane Interface
548
549	RX_PAD : in std_logic;
550	RX_PE_DATA : in std_logic_vector(0 to 15);
551	RX_PE_DATA_V : in std_logic;
552	RX_SCP : in std_logic;
553	RX_ECP : in std_logic;
554	RX_SNF : in std_logic;
555	RX_FC_NB : in std_logic_vector(0 to 3);
556
557	-- TX_LL Interface
558
559	DECREMENT_NFC : in std_logic;
560	TX_WAIT : out std_logic;
561
562	-- Error Interface
563
564	FRAME_ERROR : out std_logic;
565
566	-- System Interface
567
568	USER_CLK : in std_logic
569
570	);
571
572	end component;
573
574	begin
575
576	TX_DST_RDY_N <= TX_DST_RDY_N_Buffer;
577	RX_D <= RX_D_Buffer;
578	RX_REM <= RX_REM_Buffer;
579	RX_SRC_RDY_N <= RX_SRC_RDY_N_Buffer;
580	RX_SOF_N <= RX_SOF_N_Buffer;
581	RX_EOF_N <= RX_EOF_N_Buffer;
582	NFC_ACK_N <= NFC_ACK_N_Buffer;
583	TXP <= TXP_Buffer;
584	TXN <= TXN_Buffer;
585	HARD_ERROR <= HARD_ERROR_Buffer;
586	SOFT_ERROR <= SOFT_ERROR_Buffer;
587	FRAME_ERROR <= FRAME_ERROR_Buffer;
588	CHANNEL_UP <= CHANNEL_UP_Buffer;
589	LANE_UP <= LANE_UP_Buffer;
590
591	-- Main Body of Code --
592
593	tied_to_ground_i <= '0';
594	tied_to_vcc_i <= '1';
595	chbondi_not_used_i <= "0000";
596	fc_nb_not_used_i <= "0000";
597
598	CHANNEL_UP_Buffer <= channel_up_i;
599	system_reset_c <= RESET or DCM_NOT_LOCKED;
600
601
602	-- Instantiate Lane 0 --
603
604	LANE_UP_Buffer <= lane_up_i;
605
606
607	aurora_lane_0_i : AURORA_LANE
608	generic map (
609	EXTEND_WATCHDOGS => EXTEND_WATCHDOGS
610	)
611	port map (
612
613	-- MGT Interface
614
615	RX_DATA => rx_data_i(15 downto 0),
616	RX_NOT_IN_TABLE => rx_not_in_table_i(1 downto 0),
617	RX_DISP_ERR => rx_disp_err_i(1 downto 0),
618	RX_CHAR_IS_K => rx_char_is_k_i(1 downto 0),
619	RX_CHAR_IS_COMMA => rx_char_is_comma_i(1 downto 0),
620	RX_BUF_STATUS => rx_buf_status_i,
621	TX_BUF_ERR => tx_buf_err_i,
622	TX_K_ERR => tx_k_err_i(1 downto 0),
623	RX_CLK_COR_CNT => rx_clk_cor_cnt_i(2 downto 0),
624	RX_REALIGN => rx_realign_i,
625	RX_POLARITY => rx_polarity_i,
626	RX_RESET => rx_reset_i,
627	TX_CHAR_IS_K => tx_char_is_k_i(1 downto 0),
628	TX_DATA => tx_data_i(15 downto 0),
629	TX_RESET => tx_reset_i,
630
631	-- Comma Detect Phase Align Interface
632
633	ENA_COMMA_ALIGN => ena_comma_align_i,
634
635	-- TX_LL Interface
636
637	GEN_SCP => gen_scp_i,
638	GEN_SNF => gen_snf_i,
639	FC_NB => fc_nb_i,
640	GEN_ECP => gen_ecp_i,
641	GEN_PAD => gen_pad_i,
642	TX_PE_DATA => tx_pe_data_i(0 to 15),
643	TX_PE_DATA_V => tx_pe_data_v_i,
644	GEN_CC => gen_cc_i,
645
646	-- RX_LL Interface
647
648	RX_PAD => rx_pad_i,
649	RX_PE_DATA => rx_pe_data_i(0 to 15),
650	RX_PE_DATA_V => rx_pe_data_v_i,
651	RX_SCP => rx_scp_i,
652	RX_ECP => rx_ecp_i,
653	RX_SNF => rx_snf_i,
654	RX_FC_NB => rx_fc_nb_i(0 to 3),
655
656	-- Global Logic Interface
657
658	GEN_A => gen_a_i,
659	GEN_K => gen_k_i(0 to 1),
660	GEN_R => gen_r_i(0 to 1),
661	GEN_V => gen_v_i(0 to 1),
662	LANE_UP => lane_up_i,
663	SOFT_ERROR => soft_error_i,
664	HARD_ERROR => hard_error_i,
665	CHANNEL_BOND_LOAD => channel_bond_load_i,
666	GOT_A => got_a_i(0 to 1),
667	GOT_V => got_v_i,
668
669	-- System Interface
670
671	USER_CLK => USER_CLK,
672	RESET => reset_lanes_i
673
674	);
675
676
677	lane_0_phase_align_i : PHASE_ALIGN
678
679	port map (
680
681	-- Aurora Lane Interface
682
683	ENA_COMMA_ALIGN => ena_comma_align_i,
684
685	-- MGT Interface
686
687	RX_REC_CLK => rx_rec_clk_i,
688	ENA_CALIGN_REC => ena_calign_rec_i
689
690	);
691
692
693	txcharisk_lane_0_i <= "00" & tx_char_is_k_i(1 downto 0);
694	txdata_lane_0_i <= "0000000000000000" & tx_data_i(15 downto 0);
695	refclksel_lane_0_i <= '0';
696	txbypass8b10b_lane_0_i <= "0000";
697	txchardispmode_lane_0_i <= "0000";
698	txchardispval_lane_0_i <= "0000";
699	configenable_lane_0_i <= '0';
700	configin_lane_0_i <= '0';
701	txforcecrcerr_lane_0_i <= '0';
702	txinhibit_lane_0_i <= '0';
703	txpolarity_lane_0_i <= '0';
704
705	rx_data_i(15 downto 0) <= rxdata_lane_0_i(15 downto 0);
706	rx_not_in_table_i(1 downto 0) <= rxnotintable_lane_0_i(1 downto 0);
707	rx_disp_err_i(1 downto 0) <= rxdisperr_lane_0_i(1 downto 0);
708	rx_char_is_k_i(1 downto 0) <= rxcharisk_lane_0_i(1 downto 0);
709	rx_char_is_comma_i(1 downto 0) <= rxchariscomma_lane_0_i(1 downto 0);
710	rx_buf_status_i <= rxbufstatus_lane_0_i(1);
711	tx_k_err_i(1 downto 0) <= txkerr_lane_0_i(1 downto 0);
712
713
714	lane_0_mgt_i : GT_CUSTOM
715
716	-- Lane 0 MGT attributes
717
718	generic map (
719
720	ALIGN_COMMA_MSB => TRUE,
721	CHAN_BOND_MODE => "OFF",
722	CHAN_BOND_ONE_SHOT => FALSE,
723	CHAN_BOND_SEQ_1_1 => "00101111100",
724	REF_CLK_V_SEL => 1,
725	CLK_COR_INSERT_IDLE_FLAG => FALSE,
726	CLK_COR_KEEP_IDLE => FALSE,
727	CLK_COR_REPEAT_WAIT => 8,
728	CLK_COR_SEQ_1_1 => "00111110111",
729	CLK_COR_SEQ_1_2 => "00111110111",
730	CLK_COR_SEQ_2_USE => FALSE,
731	CLK_COR_SEQ_LEN => 2,
732	CLK_CORRECT_USE => TRUE,
733	COMMA_10B_MASK => "1111111111",
734	MCOMMA_10B_VALUE => "1100000101",
735	PCOMMA_10B_VALUE => "0011111010",
736	RX_CRC_USE => FALSE,
737	RX_DATA_WIDTH => 2,
738	RX_LOSS_OF_SYNC_FSM => FALSE,
739	RX_LOS_INVALID_INCR => 1,
740	RX_LOS_THRESHOLD => 4,
741	SERDES_10B => FALSE,
742	TERMINATION_IMP => 50,
743	TX_CRC_USE => FALSE,
744	TX_DATA_WIDTH => 2,
745	TX_DIFF_CTRL => 600,
746	TX_PREEMPHASIS => 1
747
748	)
749
750	port map (
751
752	-- Aurora Lane Interface
753
754	RXPOLARITY => rx_polarity_i,
755	RXRESET => rx_reset_i,
756	TXCHARISK => txcharisk_lane_0_i,
757	TXDATA => txdata_lane_0_i,
758	TXRESET => tx_reset_i,
759	RXDATA => rxdata_lane_0_i,
760	RXNOTINTABLE => rxnotintable_lane_0_i,
761	RXDISPERR => rxdisperr_lane_0_i,
762	RXCHARISK => rxcharisk_lane_0_i,
763	RXCHARISCOMMA => rxchariscomma_lane_0_i,
764	RXBUFSTATUS => rxbufstatus_lane_0_i,
765	TXBUFERR => tx_buf_err_i,
766	TXKERR => txkerr_lane_0_i,
767	RXCLKCORCNT => rx_clk_cor_cnt_i(2 downto 0),
768	RXREALIGN => rx_realign_i,
769
770	-- Phase Align Interface
771
772	ENMCOMMAALIGN => ena_calign_rec_i,
773	ENPCOMMAALIGN => ena_calign_rec_i,
774	RXRECCLK => rx_rec_clk_i,
775
776	-- Global Logic Interface
777
778	ENCHANSYNC => tied_to_ground_i,
779	CHBONDDONE => ch_bond_done_i,
780
781	-- Peer Channel Bonding Interface
782
783	CHBONDI => chbondi_not_used_i,
784	CHBONDO => chbondo_not_used_i(3 downto 0),
785
786	-- Unused MGT Ports
787
788	CONFIGOUT => open,
789	RXCHECKINGCRC => open,
790	RXCOMMADET => open,
791	RXCRCERR => open,
792	RXLOSSOFSYNC => open,
793	RXRUNDISP => open,
794	TXRUNDISP => open,
795
796	-- Fixed MGT settings for Aurora
797
798	TXBYPASS8B10B => txbypass8b10b_lane_0_i,
799	TXCHARDISPMODE => txchardispmode_lane_0_i,
800	TXCHARDISPVAL => txchardispval_lane_0_i,
801	CONFIGENABLE => configenable_lane_0_i,
802	CONFIGIN => configin_lane_0_i,
803	TXFORCECRCERR => txforcecrcerr_lane_0_i,
804	TXINHIBIT => txinhibit_lane_0_i,
805	TXPOLARITY => txpolarity_lane_0_i,
806
807	-- Serial IO
808
809	RXN => RXN,
810	RXP => RXP,
811	TXN => TXN_Buffer,
812	TXP => TXP_Buffer,
813
814	-- Reference Clocks and User Clock
815
816	RXUSRCLK => USER_CLK,
817	RXUSRCLK2 => USER_CLK,
818	TXUSRCLK => USER_CLK,
819	TXUSRCLK2 => USER_CLK,
820	BREFCLK => TOP_BREF_CLK,
821	BREFCLK2 => tied_to_ground_i,
822	REFCLK => tied_to_ground_i,
823	REFCLK2 => tied_to_ground_i,
824	REFCLKSEL => refclksel_lane_0_i,
825
826	-- System Interface
827
828	LOOPBACK => LOOPBACK,
829	POWERDOWN => POWER_DOWN
830
831	);
832
833
834
835
836	-- Instantiate Global Logic to combine Lanes into a Channel --
837
838	global_logic_i : GLOBAL_LOGIC
839	generic map (
840	EXTEND_WATCHDOGS => EXTEND_WATCHDOGS
841	)
842	port map (
843
844	-- MGT Interface
845
846	CH_BOND_DONE => ch_bond_done_i,
847	EN_CHAN_SYNC => en_chan_sync_i,
848
849	-- Aurora Lane Interface
850
851	LANE_UP => lane_up_i,
852	SOFT_ERROR => soft_error_i,
853	HARD_ERROR => hard_error_i,
854	CHANNEL_BOND_LOAD => channel_bond_load_i,
855	GOT_A => got_a_i,
856	GOT_V => got_v_i,
857	GEN_A => gen_a_i,
858	GEN_K => gen_k_i,
859	GEN_R => gen_r_i,
860	GEN_V => gen_v_i,
861	RESET_LANES => reset_lanes_i,
862
863	-- System Interface
864
865	USER_CLK => USER_CLK,
866	RESET => system_reset_c,
867	POWER_DOWN => POWER_DOWN,
868	CHANNEL_UP => channel_up_i,
869	START_RX => start_rx_i,
870	CHANNEL_SOFT_ERROR => SOFT_ERROR_Buffer,
871	CHANNEL_HARD_ERROR => HARD_ERROR_Buffer
872
873	);
874
875
876	-- Instantiate TX_LL --
877
878	tx_ll_i : TX_LL
879
880	port map (
881
882	-- LocalLink PDU Interface
883
884	TX_D => TX_D,
885	TX_REM => TX_REM,
886	TX_SRC_RDY_N => TX_SRC_RDY_N,
887	TX_SOF_N => TX_SOF_N,
888	TX_EOF_N => TX_EOF_N,
889	TX_DST_RDY_N => TX_DST_RDY_N_Buffer,
890
891	-- NFC Interface
892
893	NFC_REQ_N => NFC_REQ_N,
894	NFC_NB => NFC_NB,
895	NFC_ACK_N => NFC_ACK_N_Buffer,
896
897	-- Clock Compenstaion Interface
898
899	WARN_CC => WARN_CC,
900	DO_CC => DO_CC,
901
902	-- Global Logic Interface
903
904	CHANNEL_UP => channel_up_i,
905
906	-- Aurora Lane Interface
907
908	GEN_SCP => gen_scp_i,
909	GEN_ECP => gen_ecp_i,
910	GEN_SNF => gen_snf_i,
911	FC_NB => fc_nb_i,
912	TX_PE_DATA_V => tx_pe_data_v_i,
913	GEN_PAD => gen_pad_i,
914	TX_PE_DATA => tx_pe_data_i,
915	GEN_CC => gen_cc_i,
916
917	-- RX_LL Interface
918
919	TX_WAIT => tx_wait_i,
920	DECREMENT_NFC => decrement_nfc_i,
921
922	-- System Interface
923
924	USER_CLK => USER_CLK
925
926	);
927
928
929	-- Instantiate RX_LL --
930
931	rx_ll_i : RX_LL
932
933	port map (
934
935	-- LocalLink PDU Interface
936
937	RX_D => RX_D_Buffer,
938	RX_REM => RX_REM_Buffer,
939	RX_SRC_RDY_N => RX_SRC_RDY_N_Buffer,
940	RX_SOF_N => RX_SOF_N_Buffer,
941	RX_EOF_N => RX_EOF_N_Buffer,
942
943	-- Global Logic Interface
944
945	START_RX => start_rx_i,
946
947	-- Aurora Lane Interface
948
949	RX_PAD => rx_pad_i,
950	RX_PE_DATA => rx_pe_data_i,
951	RX_PE_DATA_V => rx_pe_data_v_i,
952	RX_SCP => rx_scp_i,
953	RX_ECP => rx_ecp_i,
954	RX_SNF => rx_snf_i,
955	RX_FC_NB => rx_fc_nb_i,
956
957	-- TX_LL Interface
958
959	DECREMENT_NFC => decrement_nfc_i,
960	TX_WAIT => tx_wait_i,
961
962	-- Error Interface
963
964	FRAME_ERROR => FRAME_ERROR_Buffer,
965
966	-- System Interface
967
968	USER_CLK => USER_CLK
969
970	);
971
972	end MAPPED;

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