1 | -- |
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2 | -- Project: Aurora Module Generator version 2.4 |
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3 | -- |
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4 | -- Date: $Date: 2005/11/07 21:30:52 $ |
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5 | -- Tag: $Name: i+IP+98818 $ |
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6 | -- File: $RCSfile: error_detect_vhd.ejava,v $ |
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7 | -- Rev: $Revision: 1.1.2.1 $ |
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8 | -- |
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9 | -- Company: Xilinx |
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10 | -- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone |
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11 | -- |
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12 | -- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR |
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13 | -- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING |
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14 | -- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY |
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15 | -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS |
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16 | -- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, |
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17 | -- APPLICATION OR STANDARD, XILINX IS MAKING NO |
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18 | -- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE |
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19 | -- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE |
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20 | -- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY |
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21 | -- REQUIRE FOR YOUR IMPLEMENTATION. XILINX |
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22 | -- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH |
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23 | -- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, |
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24 | -- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR |
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25 | -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE |
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26 | -- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES |
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27 | -- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
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28 | -- PURPOSE. |
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29 | -- |
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30 | -- (c) Copyright 2004 Xilinx, Inc. |
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31 | -- All rights reserved. |
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32 | -- |
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33 | |
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34 | -- |
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35 | -- ERROR_DETECT |
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36 | -- |
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37 | -- Author: Nigel Gulstone |
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38 | -- Xilinx - Embedded Networking System Engineering Group |
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39 | -- |
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40 | -- VHDL Translation: Brian Woodard |
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41 | -- Xilinx - Garden Valley Design Team |
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42 | -- |
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43 | -- Description : The ERROR_DETECT module monitors the MGT to detect hard |
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44 | -- errors. It accumulates the Soft errors according to the |
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45 | -- leaky bucket algorithm described in the Aurora |
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46 | -- Specification to detect Hard errors. All errors are |
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47 | -- reported to the Global Logic Interface. |
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48 | -- |
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49 | |
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50 | library IEEE; |
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51 | use IEEE.STD_LOGIC_1164.all; |
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52 | use WORK.AURORA.all; |
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53 | |
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54 | entity ERROR_DETECT is |
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55 | |
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56 | port ( |
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57 | |
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58 | -- Lane Init SM Interface |
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59 | |
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60 | ENABLE_ERROR_DETECT : in std_logic; |
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61 | HARD_ERROR_RESET : out std_logic; |
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62 | |
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63 | -- Global Logic Interface |
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64 | |
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65 | SOFT_ERROR : out std_logic; |
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66 | HARD_ERROR : out std_logic; |
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67 | |
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68 | -- MGT Interface |
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69 | |
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70 | RX_DISP_ERR : in std_logic_vector(1 downto 0); |
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71 | TX_K_ERR : in std_logic_vector(1 downto 0); |
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72 | RX_NOT_IN_TABLE : in std_logic_vector(1 downto 0); |
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73 | RX_BUF_STATUS : in std_logic; |
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74 | TX_BUF_ERR : in std_logic; |
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75 | RX_REALIGN : in std_logic; |
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76 | |
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77 | -- System Interface |
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78 | |
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79 | USER_CLK : in std_logic |
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80 | |
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81 | ); |
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82 | |
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83 | end ERROR_DETECT; |
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84 | |
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85 | architecture RTL of ERROR_DETECT is |
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86 | |
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87 | -- Parameter Declarations -- |
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88 | |
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89 | constant DLY : time := 1 ns; |
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90 | |
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91 | -- External Register Declarations -- |
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92 | |
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93 | signal HARD_ERROR_RESET_Buffer : std_logic; |
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94 | signal SOFT_ERROR_Buffer : std_logic; |
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95 | signal HARD_ERROR_Buffer : std_logic; |
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96 | |
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97 | -- Internal Register Declarations -- |
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98 | |
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99 | signal count_r : std_logic_vector(0 to 1); |
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100 | signal bucket_full_r : std_logic; |
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101 | signal soft_error_r : std_logic_vector(0 to 1); |
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102 | signal good_count_r : std_logic_vector(0 to 1); |
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103 | signal soft_error_flop_r : std_logic; -- Traveling flop for timing. |
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104 | signal hard_error_flop_r : std_logic; -- Traveling flop for timing. |
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105 | |
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106 | begin |
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107 | |
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108 | HARD_ERROR_RESET <= HARD_ERROR_RESET_Buffer; |
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109 | SOFT_ERROR <= SOFT_ERROR_Buffer; |
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110 | HARD_ERROR <= HARD_ERROR_Buffer; |
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111 | |
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112 | -- Main Body of Code -- |
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113 | |
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114 | -- Detect Soft Errors |
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115 | |
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116 | process (USER_CLK) |
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117 | |
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118 | begin |
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119 | |
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120 | if (USER_CLK 'event and USER_CLK = '1') then |
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121 | |
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122 | if (ENABLE_ERROR_DETECT = '1') then |
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123 | |
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124 | soft_error_r(0) <= RX_DISP_ERR(1) or RX_NOT_IN_TABLE(1) after DLY; |
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125 | soft_error_r(1) <= RX_DISP_ERR(0) or RX_NOT_IN_TABLE(0) after DLY; |
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126 | |
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127 | else |
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128 | |
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129 | soft_error_r(0) <= '0' after DLY; |
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130 | soft_error_r(1) <= '0' after DLY; |
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131 | |
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132 | end if; |
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133 | |
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134 | end if; |
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135 | |
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136 | end process; |
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137 | |
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138 | |
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139 | process (USER_CLK) |
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140 | |
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141 | begin |
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142 | |
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143 | if (USER_CLK 'event and USER_CLK = '1') then |
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144 | |
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145 | soft_error_flop_r <= soft_error_r(0) or |
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146 | soft_error_r(1) after DLY; |
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147 | |
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148 | SOFT_ERROR_Buffer <= soft_error_flop_r after DLY; |
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149 | |
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150 | end if; |
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151 | |
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152 | end process; |
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153 | |
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154 | |
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155 | -- Detect Hard Errors |
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156 | |
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157 | process (USER_CLK) |
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158 | |
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159 | begin |
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160 | |
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161 | if (USER_CLK 'event and USER_CLK = '1') then |
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162 | |
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163 | if (ENABLE_ERROR_DETECT = '1') then |
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164 | |
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165 | hard_error_flop_r <= std_bool(TX_K_ERR /= "00") or |
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166 | RX_BUF_STATUS or |
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167 | TX_BUF_ERR or |
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168 | RX_REALIGN or |
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169 | bucket_full_r after DLY; |
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170 | |
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171 | HARD_ERROR_Buffer <= hard_error_flop_r after DLY; |
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172 | |
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173 | else |
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174 | |
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175 | hard_error_flop_r <= '0' after DLY; |
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176 | HARD_ERROR_Buffer <= '0' after DLY; |
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177 | |
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178 | end if; |
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179 | |
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180 | end if; |
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181 | |
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182 | end process; |
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183 | |
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184 | |
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185 | -- Assert hard error reset when there is a hard error. This assignment |
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186 | -- just renames the two fanout branches of the hard error signal. |
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187 | |
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188 | HARD_ERROR_RESET_Buffer <= hard_error_flop_r; |
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189 | |
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190 | |
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191 | -- Leaky Bucket -- |
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192 | |
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193 | -- Good cycle counter: it takes 2 consecutive good cycles to remove a demerit from |
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194 | -- the leaky bucket |
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195 | |
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196 | process (USER_CLK) |
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197 | |
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198 | variable err_vec : std_logic_vector(3 downto 0); |
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199 | |
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200 | begin |
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201 | |
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202 | if (USER_CLK 'event and USER_CLK = '1') then |
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203 | |
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204 | if (ENABLE_ERROR_DETECT = '0') then |
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205 | |
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206 | good_count_r <= "01" after DLY; |
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207 | |
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208 | else |
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209 | |
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210 | err_vec := soft_error_r & good_count_r; |
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211 | |
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212 | case err_vec is |
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213 | |
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214 | when "0000" => good_count_r <= "01" after DLY; |
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215 | when "0001" => good_count_r <= "10" after DLY; |
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216 | when "0010" => good_count_r <= "01" after DLY; |
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217 | when "0011" => good_count_r <= "01" after DLY; |
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218 | when others => good_count_r <= "00" after DLY; |
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219 | |
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220 | end case; |
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221 | |
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222 | end if; |
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223 | |
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224 | end if; |
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225 | |
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226 | end process; |
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227 | |
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228 | |
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229 | -- Perform the leaky bucket algorithm using an up/down counter. A drop is |
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230 | -- added to the bucket whenever a soft error occurs and is allowed to leak |
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231 | -- out whenever the good cycles counter reaches 2. Once the bucket fills |
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232 | -- (3 drops) it stays full until it is reset by disabling and then enabling |
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233 | -- the error detection circuit. |
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234 | |
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235 | process (USER_CLK) |
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236 | |
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237 | variable leaky_bucket : std_logic_vector(4 downto 0); |
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238 | |
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239 | begin |
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240 | |
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241 | if (USER_CLK 'event and USER_CLK = '1') then |
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242 | |
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243 | if (ENABLE_ERROR_DETECT = '0') then |
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244 | |
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245 | count_r <= "00" after DLY; |
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246 | |
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247 | else |
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248 | |
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249 | leaky_bucket := soft_error_r & good_count_r(0) & count_r; |
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250 | |
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251 | case leaky_bucket is |
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252 | |
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253 | when "00000" => count_r <= count_r after DLY; |
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254 | when "00001" => count_r <= count_r after DLY; |
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255 | when "00010" => count_r <= count_r after DLY; |
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256 | when "00011" => count_r <= count_r after DLY; |
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257 | |
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258 | when "00100" => count_r <= "00" after DLY; |
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259 | when "00101" => count_r <= "00" after DLY; |
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260 | when "00110" => count_r <= "01" after DLY; |
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261 | when "00111" => count_r <= "11" after DLY; |
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262 | |
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263 | when "01000" => count_r <= "01" after DLY; |
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264 | when "01001" => count_r <= "10" after DLY; |
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265 | when "01010" => count_r <= "11" after DLY; |
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266 | when "01011" => count_r <= "11" after DLY; |
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267 | |
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268 | when "01100" => count_r <= "01" after DLY; |
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269 | when "01101" => count_r <= "10" after DLY; |
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270 | when "01110" => count_r <= "11" after DLY; |
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271 | when "01111" => count_r <= "11" after DLY; |
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272 | |
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273 | when "10000" => count_r <= "01" after DLY; |
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274 | when "10001" => count_r <= "10" after DLY; |
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275 | when "10010" => count_r <= "11" after DLY; |
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276 | when "10011" => count_r <= "11" after DLY; |
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277 | |
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278 | when "10100" => count_r <= "01" after DLY; |
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279 | when "10101" => count_r <= "10" after DLY; |
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280 | when "10110" => count_r <= "11" after DLY; |
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281 | when "10111" => count_r <= "11" after DLY; |
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282 | |
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283 | when "11000" => count_r <= "10" after DLY; |
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284 | when "11001" => count_r <= "11" after DLY; |
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285 | when "11010" => count_r <= "11" after DLY; |
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286 | when "11011" => count_r <= "11" after DLY; |
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287 | |
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288 | when "11100" => count_r <= "10" after DLY; |
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289 | when "11101" => count_r <= "11" after DLY; |
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290 | when "11110" => count_r <= "11" after DLY; |
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291 | when "11111" => count_r <= "11" after DLY; |
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292 | |
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293 | when others => count_r <= "XX" after DLY; |
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294 | |
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295 | end case; |
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296 | |
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297 | end if; |
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298 | |
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299 | end if; |
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300 | |
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301 | end process; |
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302 | |
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303 | |
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304 | -- Detect when the bucket is full and register the signal. |
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305 | |
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306 | process (USER_CLK) |
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307 | |
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308 | begin |
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309 | |
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310 | if (USER_CLK 'event and USER_CLK = '1') then |
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311 | |
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312 | bucket_full_r <= std_bool(count_r = "11") after DLY; |
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313 | |
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314 | end if; |
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315 | |
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316 | end process; |
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317 | |
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318 | end RTL; |
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