source: PlatformSupport/Deprecated/pcores/linkport_v1_00_a/hdl/vhdl/fifo_64x18.vhd

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-- You must compile the wrapper file fifo_64x18.vhd when simulating
-- the core, fifo_64x18. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on
ENTITY fifo_64x18 IS
    port (
    din: IN std_logic_VECTOR(17 downto 0);
    rd_clk: IN std_logic;
    rd_en: IN std_logic;
    rst: IN std_logic;
    wr_clk: IN std_logic;
    wr_en: IN std_logic;
    almost_empty: OUT std_logic;
    almost_full: OUT std_logic;
    dout: OUT std_logic_VECTOR(17 downto 0);
    empty: OUT std_logic;
    full: OUT std_logic);
END fifo_64x18;

ARCHITECTURE fifo_64x18_a OF fifo_64x18 IS
-- synopsys translate_off
component wrapped_fifo_64x18
    port (
    din: IN std_logic_VECTOR(17 downto 0);
    rd_clk: IN std_logic;
    rd_en: IN std_logic;
    rst: IN std_logic;
    wr_clk: IN std_logic;
    wr_en: IN std_logic;
    almost_empty: OUT std_logic;
    almost_full: OUT std_logic;
    dout: OUT std_logic_VECTOR(17 downto 0);
    empty: OUT std_logic;
    full: OUT std_logic);
end component;

-- Configuration specification 
    for all : wrapped_fifo_64x18 use entity XilinxCoreLib.fifo_generator_v2_3(behavioral)
        generic map(
            c_wr_response_latency => 1,
            c_has_rd_data_count => 0,
            c_din_width => 18,
            c_has_wr_data_count => 0,
            c_implementation_type => 2,
            c_family => "virtex2p",
            c_has_wr_rst => 0,
            c_underflow_low => 0,
            c_has_meminit_file => 0,
            c_has_overflow => 0,
            c_preload_latency => 0,
            c_dout_width => 18,
            c_rd_depth => 64,
            c_default_value => "BlankString",
            c_mif_file_name => "BlankString",
            c_has_underflow => 0,
            c_has_rd_rst => 0,
            c_has_almost_full => 1,
            c_has_rst => 1,
            c_data_count_width => 2,
            c_has_wr_ack => 0,
            c_wr_ack_low => 0,
            c_common_clock => 0,
            c_rd_pntr_width => 6,
            c_has_almost_empty => 1,
            c_rd_data_count_width => 2,
            c_enable_rlocs => 0,
            c_wr_pntr_width => 6,
            c_overflow_low => 0,
            c_prog_empty_type => 0,
            c_optimization_mode => 0,
            c_wr_data_count_width => 2,
            c_preload_regs => 1,
            c_dout_rst_val => "0",
            c_has_data_count => 0,
            c_prog_full_thresh_negate_val => 62,
            c_wr_depth => 64,
            c_prog_empty_thresh_negate_val => 62,
            c_prog_empty_thresh_assert_val => 62,
            c_has_valid => 0,
            c_init_wr_pntr_val => 0,
            c_prog_full_thresh_assert_val => 62,
            c_use_fifo16_flags => 0,
            c_has_backup => 0,
            c_valid_low => 0,
            c_prim_fifo_type => 512,
            c_count_type => 0,
            c_prog_full_type => 0,
            c_memory_type => 2);
-- synopsys translate_on
BEGIN
-- synopsys translate_off
U0 : wrapped_fifo_64x18
        port map (
            din => din,
            rd_clk => rd_clk,
            rd_en => rd_en,
            rst => rst,
            wr_clk => wr_clk,
            wr_en => wr_en,
            almost_empty => almost_empty,
            almost_full => almost_full,
            dout => dout,
            empty => empty,
            full => full);
-- synopsys translate_on

END fifo_64x18_a;