1 | -- |
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2 | -- Project: Aurora Module Generator version 2.4 |
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3 | -- |
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4 | -- Date: $Date: 2005/11/16 00:32:43 $ |
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5 | -- Tag: $Name: i+IP+98818 $ |
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6 | -- File: $RCSfile: global_logic_vhd.ejava,v $ |
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7 | -- Rev: $Revision: 1.1.2.5 $ |
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8 | -- |
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9 | -- Company: Xilinx |
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10 | -- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone |
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11 | -- |
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12 | -- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR |
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13 | -- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING |
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14 | -- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY |
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15 | -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS |
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16 | -- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, |
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17 | -- APPLICATION OR STANDARD, XILINX IS MAKING NO |
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18 | -- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE |
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19 | -- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE |
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20 | -- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY |
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21 | -- REQUIRE FOR YOUR IMPLEMENTATION. XILINX |
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22 | -- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH |
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23 | -- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, |
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24 | -- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR |
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25 | -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE |
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26 | -- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES |
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27 | -- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
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28 | -- PURPOSE. |
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29 | -- |
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30 | -- (c) Copyright 2004 Xilinx, Inc. |
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31 | -- All rights reserved. |
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32 | -- |
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33 | |
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34 | -- |
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35 | -- GLOBAL_LOGIC |
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36 | -- |
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37 | -- Author: Nigel Gulstone |
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38 | -- Xilinx - Embedded Networking System Engineering Group |
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39 | -- |
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40 | -- VHDL Translation: Brian Woodard |
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41 | -- Xilinx - Garden Valley Design Team |
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42 | -- |
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43 | -- Description: The GLOBAL_LOGIC module handles channel bonding, channel |
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44 | -- verification, channel error manangement and idle generation. |
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45 | -- |
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46 | -- This module supports 1 2-byte lane designs |
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47 | -- |
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48 | |
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49 | library IEEE; |
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50 | use IEEE.STD_LOGIC_1164.all; |
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51 | |
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52 | entity GLOBAL_LOGIC is |
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53 | generic ( |
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54 | EXTEND_WATCHDOGS : boolean := FALSE |
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55 | ); |
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56 | port ( |
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57 | |
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58 | -- MGT Interface |
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59 | |
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60 | CH_BOND_DONE : in std_logic; |
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61 | EN_CHAN_SYNC : out std_logic; |
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62 | |
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63 | -- Aurora Lane Interface |
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64 | |
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65 | LANE_UP : in std_logic; |
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66 | SOFT_ERROR : in std_logic; |
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67 | HARD_ERROR : in std_logic; |
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68 | CHANNEL_BOND_LOAD : in std_logic; |
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69 | GOT_A : in std_logic_vector(0 to 1); |
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70 | GOT_V : in std_logic; |
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71 | GEN_A : out std_logic; |
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72 | GEN_K : out std_logic_vector(0 to 1); |
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73 | GEN_R : out std_logic_vector(0 to 1); |
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74 | GEN_V : out std_logic_vector(0 to 1); |
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75 | RESET_LANES : out std_logic; |
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76 | |
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77 | -- System Interface |
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78 | |
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79 | USER_CLK : in std_logic; |
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80 | RESET : in std_logic; |
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81 | POWER_DOWN : in std_logic; |
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82 | CHANNEL_UP : out std_logic; |
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83 | START_RX : out std_logic; |
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84 | CHANNEL_SOFT_ERROR : out std_logic; |
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85 | CHANNEL_HARD_ERROR : out std_logic |
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86 | |
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87 | ); |
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88 | |
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89 | end GLOBAL_LOGIC; |
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90 | |
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91 | architecture MAPPED of GLOBAL_LOGIC is |
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92 | |
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93 | -- External Register Declarations -- |
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94 | |
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95 | signal EN_CHAN_SYNC_Buffer : std_logic; |
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96 | signal GEN_A_Buffer : std_logic; |
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97 | signal GEN_K_Buffer : std_logic_vector(0 to 1); |
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98 | signal GEN_R_Buffer : std_logic_vector(0 to 1); |
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99 | signal GEN_V_Buffer : std_logic_vector(0 to 1); |
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100 | signal RESET_LANES_Buffer : std_logic; |
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101 | signal CHANNEL_UP_Buffer : std_logic; |
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102 | signal START_RX_Buffer : std_logic; |
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103 | signal CHANNEL_SOFT_ERROR_Buffer : std_logic; |
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104 | signal CHANNEL_HARD_ERROR_Buffer : std_logic; |
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105 | |
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106 | -- Wire Declarations -- |
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107 | |
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108 | signal gen_ver_i : std_logic; |
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109 | signal reset_channel_i : std_logic; |
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110 | signal did_ver_i : std_logic; |
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111 | |
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112 | -- Component Declarations -- |
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113 | |
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114 | component CHANNEL_INIT_SM |
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115 | generic ( |
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116 | EXTEND_WATCHDOGS : boolean := FALSE |
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117 | ); |
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118 | port ( |
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119 | |
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120 | -- MGT Interface |
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121 | |
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122 | CH_BOND_DONE : in std_logic; |
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123 | EN_CHAN_SYNC : out std_logic; |
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124 | |
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125 | -- Aurora Lane Interface |
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126 | |
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127 | CHANNEL_BOND_LOAD : in std_logic; |
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128 | GOT_A : in std_logic_vector(0 to 1); |
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129 | GOT_V : in std_logic; |
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130 | RESET_LANES : out std_logic; |
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131 | |
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132 | -- System Interface |
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133 | |
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134 | USER_CLK : in std_logic; |
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135 | RESET : in std_logic; |
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136 | CHANNEL_UP : out std_logic; |
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137 | START_RX : out std_logic; |
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138 | |
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139 | -- Idle and Verification Sequence Generator Interface |
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140 | |
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141 | DID_VER : in std_logic; |
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142 | GEN_VER : out std_logic; |
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143 | |
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144 | -- Channel Init State Machine Interface |
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145 | |
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146 | RESET_CHANNEL : in std_logic |
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147 | |
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148 | ); |
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149 | |
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150 | end component; |
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151 | |
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152 | |
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153 | component IDLE_AND_VER_GEN |
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154 | |
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155 | port ( |
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156 | |
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157 | -- Channel Init SM Interface |
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158 | |
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159 | GEN_VER : in std_logic; |
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160 | DID_VER : out std_logic; |
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161 | |
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162 | -- Aurora Lane Interface |
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163 | |
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164 | GEN_A : out std_logic; |
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165 | GEN_K : out std_logic_vector(0 to 1); |
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166 | GEN_R : out std_logic_vector(0 to 1); |
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167 | GEN_V : out std_logic_vector(0 to 1); |
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168 | |
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169 | -- System Interface |
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170 | |
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171 | RESET : in std_logic; |
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172 | USER_CLK : in std_logic |
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173 | |
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174 | ); |
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175 | |
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176 | end component; |
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177 | |
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178 | |
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179 | component CHANNEL_ERROR_DETECT |
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180 | |
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181 | port ( |
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182 | |
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183 | -- Aurora Lane Interface |
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184 | |
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185 | SOFT_ERROR : in std_logic; |
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186 | HARD_ERROR : in std_logic; |
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187 | LANE_UP : in std_logic; |
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188 | |
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189 | -- System Interface |
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190 | |
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191 | USER_CLK : in std_logic; |
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192 | POWER_DOWN : in std_logic; |
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193 | |
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194 | CHANNEL_SOFT_ERROR : out std_logic; |
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195 | CHANNEL_HARD_ERROR : out std_logic; |
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196 | |
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197 | -- Channel Init SM Interface |
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198 | |
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199 | RESET_CHANNEL : out std_logic |
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200 | |
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201 | ); |
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202 | |
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203 | end component; |
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204 | |
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205 | begin |
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206 | |
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207 | EN_CHAN_SYNC <= EN_CHAN_SYNC_Buffer; |
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208 | GEN_A <= GEN_A_Buffer; |
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209 | GEN_K <= GEN_K_Buffer; |
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210 | GEN_R <= GEN_R_Buffer; |
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211 | GEN_V <= GEN_V_Buffer; |
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212 | RESET_LANES <= RESET_LANES_Buffer; |
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213 | CHANNEL_UP <= CHANNEL_UP_Buffer; |
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214 | START_RX <= START_RX_Buffer; |
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215 | CHANNEL_SOFT_ERROR <= CHANNEL_SOFT_ERROR_Buffer; |
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216 | CHANNEL_HARD_ERROR <= CHANNEL_HARD_ERROR_Buffer; |
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217 | |
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218 | -- Main Body of Code -- |
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219 | |
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220 | -- State Machine for channel bonding and verification. |
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221 | |
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222 | channel_init_sm_i : CHANNEL_INIT_SM |
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223 | generic map ( |
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224 | EXTEND_WATCHDOGS => EXTEND_WATCHDOGS |
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225 | ) |
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226 | port map ( |
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227 | |
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228 | -- MGT Interface |
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229 | |
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230 | CH_BOND_DONE => CH_BOND_DONE, |
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231 | EN_CHAN_SYNC => EN_CHAN_SYNC_Buffer, |
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232 | |
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233 | -- Aurora Lane Interface |
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234 | |
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235 | CHANNEL_BOND_LOAD => CHANNEL_BOND_LOAD, |
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236 | GOT_A => GOT_A, |
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237 | GOT_V => GOT_V, |
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238 | RESET_LANES => RESET_LANES_Buffer, |
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239 | |
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240 | -- System Interface |
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241 | |
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242 | USER_CLK => USER_CLK, |
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243 | RESET => RESET, |
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244 | START_RX => START_RX_Buffer, |
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245 | CHANNEL_UP => CHANNEL_UP_Buffer, |
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246 | |
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247 | -- Idle and Verification Sequence Generator Interface |
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248 | |
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249 | DID_VER => did_ver_i, |
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250 | GEN_VER => gen_ver_i, |
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251 | |
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252 | -- Channel Error Management Module Interface |
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253 | |
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254 | RESET_CHANNEL => reset_channel_i |
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255 | |
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256 | ); |
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257 | |
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258 | |
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259 | -- Idle and verification sequence generator module. |
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260 | |
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261 | idle_and_ver_gen_i : IDLE_AND_VER_GEN |
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262 | |
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263 | port map ( |
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264 | |
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265 | -- Channel Init SM Interface |
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266 | |
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267 | GEN_VER => gen_ver_i, |
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268 | DID_VER => did_ver_i, |
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269 | |
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270 | -- Aurora Lane Interface |
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271 | |
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272 | GEN_A => GEN_A_Buffer, |
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273 | GEN_K => GEN_K_Buffer, |
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274 | GEN_R => GEN_R_Buffer, |
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275 | GEN_V => GEN_V_Buffer, |
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276 | |
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277 | -- System Interface |
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278 | |
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279 | RESET => RESET, |
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280 | USER_CLK => USER_CLK |
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281 | |
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282 | ); |
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283 | |
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284 | |
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285 | |
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286 | -- Channel Error Management module. |
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287 | |
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288 | channel_error_detect_i : CHANNEL_ERROR_DETECT |
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289 | |
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290 | port map ( |
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291 | |
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292 | -- Aurora Lane Interface |
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293 | |
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294 | SOFT_ERROR => SOFT_ERROR, |
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295 | HARD_ERROR => HARD_ERROR, |
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296 | LANE_UP => LANE_UP, |
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297 | |
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298 | -- System Interface |
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299 | |
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300 | USER_CLK => USER_CLK, |
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301 | POWER_DOWN => POWER_DOWN, |
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302 | CHANNEL_SOFT_ERROR => CHANNEL_SOFT_ERROR_Buffer, |
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303 | CHANNEL_HARD_ERROR => CHANNEL_HARD_ERROR_Buffer, |
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304 | |
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305 | -- Channel Init State Machine Interface |
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306 | |
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307 | RESET_CHANNEL => reset_channel_i |
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308 | |
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309 | ); |
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310 | |
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311 | end MAPPED; |
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