1 | -- |
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2 | -- Project: Aurora Module Generator version 2.4 |
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3 | -- |
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4 | -- Date: $Date: 2005/12/15 01:59:13 $ |
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5 | -- Tag: $Name: i+IP+98818 $ |
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6 | -- File: $RCSfile: rx_ll_vhd.ejava,v $ |
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7 | -- Rev: $Revision: 1.1.2.5 $ |
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8 | -- |
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9 | -- Company: Xilinx |
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10 | -- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone |
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11 | -- |
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12 | -- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR |
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13 | -- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING |
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14 | -- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY |
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15 | -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS |
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16 | -- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, |
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17 | -- APPLICATION OR STANDARD, XILINX IS MAKING NO |
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18 | -- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE |
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19 | -- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE |
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20 | -- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY |
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21 | -- REQUIRE FOR YOUR IMPLEMENTATION. XILINX |
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22 | -- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH |
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23 | -- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, |
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24 | -- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR |
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25 | -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE |
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26 | -- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES |
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27 | -- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
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28 | -- PURPOSE. |
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29 | -- |
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30 | -- (c) Copyright 2004 Xilinx, Inc. |
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31 | -- All rights reserved. |
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32 | -- |
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33 | |
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34 | -- |
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35 | -- RX_LL |
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36 | -- |
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37 | -- Author: Nigel Gulstone |
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38 | -- Xilinx - Embedded Networking System Engineering Group |
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39 | -- |
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40 | -- VHDL Translation: Brian Woodard |
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41 | -- Xilinx - Garden Valley Design Team |
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42 | -- |
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43 | -- Description: The RX_LL module receives data from the Aurora Channel, |
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44 | -- converts it to LocalLink and sends it to the user interface. |
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45 | -- It also handles NFC and UFC messages. |
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46 | -- |
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47 | -- This module supports 1 2-byte lane designs. |
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48 | -- |
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49 | -- This module supports Immediate Mode Native Flow Control. |
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50 | -- |
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51 | |
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52 | library IEEE; |
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53 | use IEEE.STD_LOGIC_1164.all; |
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54 | |
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55 | entity RX_LL is |
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56 | |
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57 | port ( |
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58 | |
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59 | -- LocalLink PDU Interface |
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60 | |
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61 | RX_D : out std_logic_vector(0 to 15); |
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62 | RX_REM : out std_logic; |
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63 | RX_SRC_RDY_N : out std_logic; |
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64 | RX_SOF_N : out std_logic; |
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65 | RX_EOF_N : out std_logic; |
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66 | |
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67 | -- Global Logic Interface |
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68 | |
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69 | START_RX : in std_logic; |
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70 | |
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71 | -- Aurora Lane Interface |
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72 | |
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73 | RX_PAD : in std_logic; |
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74 | RX_PE_DATA : in std_logic_vector(0 to 15); |
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75 | RX_PE_DATA_V : in std_logic; |
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76 | RX_SCP : in std_logic; |
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77 | RX_ECP : in std_logic; |
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78 | RX_SNF : in std_logic; |
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79 | RX_FC_NB : in std_logic_vector(0 to 3); |
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80 | |
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81 | -- TX_LL Interface |
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82 | |
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83 | DECREMENT_NFC : in std_logic; |
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84 | TX_WAIT : out std_logic; |
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85 | |
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86 | -- Error Interface |
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87 | |
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88 | FRAME_ERROR : out std_logic; |
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89 | |
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90 | -- System Interface |
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91 | |
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92 | USER_CLK : in std_logic |
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93 | |
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94 | ); |
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95 | |
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96 | end RX_LL; |
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97 | |
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98 | architecture MAPPED of RX_LL is |
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99 | |
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100 | -- External Register Declarations -- |
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101 | |
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102 | signal RX_D_Buffer : std_logic_vector(0 to 15); |
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103 | signal RX_REM_Buffer : std_logic; |
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104 | signal RX_SRC_RDY_N_Buffer : std_logic; |
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105 | signal RX_SOF_N_Buffer : std_logic; |
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106 | signal RX_EOF_N_Buffer : std_logic; |
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107 | signal TX_WAIT_Buffer : std_logic; |
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108 | signal FRAME_ERROR_Buffer : std_logic; |
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109 | |
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110 | -- Wire Declarations -- |
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111 | |
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112 | signal start_rx_i : std_logic; |
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113 | |
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114 | -- Component Declarations -- |
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115 | |
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116 | component RX_LL_NFC |
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117 | |
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118 | port ( |
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119 | |
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120 | -- Aurora Lane Interface |
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121 | |
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122 | RX_SNF : in std_logic; |
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123 | RX_FC_NB : in std_logic_vector(0 to 3); |
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124 | |
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125 | -- TX_LL Interface |
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126 | |
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127 | DECREMENT_NFC : in std_logic; |
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128 | TX_WAIT : out std_logic; |
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129 | |
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130 | -- Global Logic Interface |
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131 | |
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132 | CHANNEL_UP : in std_logic; |
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133 | |
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134 | -- USER Interface |
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135 | |
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136 | USER_CLK : in std_logic |
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137 | |
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138 | ); |
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139 | |
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140 | end component; |
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141 | |
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142 | |
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143 | component RX_LL_PDU_DATAPATH |
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144 | |
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145 | port ( |
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146 | |
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147 | -- Traffic Separator Interface |
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148 | |
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149 | PDU_DATA : in std_logic_vector(0 to 15); |
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150 | PDU_DATA_V : in std_logic; |
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151 | PDU_PAD : in std_logic; |
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152 | PDU_SCP : in std_logic; |
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153 | PDU_ECP : in std_logic; |
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154 | |
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155 | -- LocalLink PDU Interface |
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156 | |
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157 | RX_D : out std_logic_vector(0 to 15); |
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158 | RX_REM : out std_logic; |
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159 | RX_SRC_RDY_N : out std_logic; |
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160 | RX_SOF_N : out std_logic; |
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161 | RX_EOF_N : out std_logic; |
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162 | |
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163 | -- Error Interface |
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164 | |
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165 | FRAME_ERROR : out std_logic; |
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166 | |
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167 | -- System Interface |
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168 | |
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169 | USER_CLK : in std_logic; |
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170 | RESET : in std_logic |
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171 | |
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172 | ); |
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173 | |
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174 | end component; |
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175 | |
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176 | |
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177 | begin |
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178 | |
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179 | RX_D <= RX_D_Buffer; |
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180 | RX_REM <= RX_REM_Buffer; |
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181 | RX_SRC_RDY_N <= RX_SRC_RDY_N_Buffer; |
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182 | RX_SOF_N <= RX_SOF_N_Buffer; |
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183 | RX_EOF_N <= RX_EOF_N_Buffer; |
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184 | TX_WAIT <= TX_WAIT_Buffer; |
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185 | FRAME_ERROR <= FRAME_ERROR_Buffer; |
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186 | |
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187 | start_rx_i <= not START_RX; |
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188 | |
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189 | -- Main Body of Code -- |
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190 | |
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191 | -- NFC processing -- |
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192 | |
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193 | nfc_module_i : RX_LL_NFC |
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194 | |
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195 | port map ( |
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196 | |
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197 | -- Aurora Lane Interface |
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198 | |
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199 | RX_SNF => RX_SNF, |
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200 | RX_FC_NB => RX_FC_NB, |
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201 | |
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202 | -- TX_LL Interface |
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203 | |
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204 | DECREMENT_NFC => DECREMENT_NFC, |
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205 | TX_WAIT => TX_WAIT_Buffer, |
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206 | |
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207 | -- Global Logic Interface |
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208 | |
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209 | CHANNEL_UP => START_RX, |
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210 | |
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211 | -- USER Interface |
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212 | |
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213 | USER_CLK => USER_CLK |
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214 | |
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215 | ); |
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216 | |
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217 | |
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218 | -- Datapath for user PDUs -- |
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219 | |
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220 | rx_ll_pdu_datapath_i : RX_LL_PDU_DATAPATH |
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221 | |
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222 | port map ( |
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223 | |
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224 | -- Traffic Separator Interface |
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225 | |
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226 | PDU_DATA => RX_PE_DATA, |
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227 | PDU_DATA_V => RX_PE_DATA_V, |
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228 | PDU_PAD => RX_PAD, |
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229 | PDU_SCP => RX_SCP, |
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230 | PDU_ECP => RX_ECP, |
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231 | |
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232 | -- LocalLink PDU Interface |
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233 | |
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234 | RX_D => RX_D_Buffer, |
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235 | RX_REM => RX_REM_Buffer, |
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236 | RX_SRC_RDY_N => RX_SRC_RDY_N_Buffer, |
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237 | RX_SOF_N => RX_SOF_N_Buffer, |
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238 | RX_EOF_N => RX_EOF_N_Buffer, |
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239 | |
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240 | -- Error Interface |
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241 | |
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242 | FRAME_ERROR => FRAME_ERROR_Buffer, |
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243 | |
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244 | -- System Interface |
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245 | |
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246 | USER_CLK => USER_CLK, |
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247 | RESET => start_rx_i |
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248 | |
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249 | ); |
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250 | |
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251 | |
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252 | end MAPPED; |
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