1 | ------------------------------------------------------------------------------- |
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2 | -- |
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3 | -- Project: Aurora Module Generator version 2.4 |
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4 | -- |
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5 | -- Date: $Date: 2005/11/07 21:30:54 $ |
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6 | -- Tag: $Name: i+IP+98818 $ |
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7 | -- File: $RCSfile: rx_ll_pdu_datapath_vhd.ejava,v $ |
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8 | -- Rev: $Revision: 1.1.2.4 $ |
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9 | -- |
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10 | -- Company: Xilinx |
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11 | -- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone |
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12 | -- |
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13 | -- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR |
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14 | -- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING |
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15 | -- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY |
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16 | -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS |
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17 | -- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, |
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18 | -- APPLICATION OR STANDARD, XILINX IS MAKING NO |
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19 | -- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE |
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20 | -- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE |
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21 | -- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY |
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22 | -- REQUIRE FOR YOUR IMPLEMENTATION. XILINX |
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23 | -- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH |
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24 | -- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, |
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25 | -- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR |
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26 | -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE |
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27 | -- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES |
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28 | -- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
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29 | -- PURPOSE. |
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30 | -- |
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31 | -- (c) Copyright 2004 Xilinx, Inc. |
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32 | -- All rights reserved. |
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33 | -- |
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34 | ------------------------------------------------------------------------------- |
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35 | -- |
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36 | -- RX_LL_PDU_DATAPATH |
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37 | -- |
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38 | -- Author: Nigel Gulstone |
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39 | -- Xilinx - Embedded Networking System Engineering Group |
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40 | -- |
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41 | -- Description: the RX_LL_PDU_DATAPATH module takes regular PDU data in Aurora format |
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42 | -- and transforms it to LocalLink formatted data |
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43 | -- |
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44 | -- This module supports 1 2-byte lane designs |
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45 | -- |
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46 | -- |
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47 | |
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48 | library IEEE; |
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49 | use IEEE.STD_LOGIC_1164.all; |
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50 | use IEEE.STD_LOGIC_ARITH.all; |
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51 | use IEEE.STD_LOGIC_UNSIGNED.all; |
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52 | use WORK.AURORA.all; |
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53 | |
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54 | entity RX_LL_PDU_DATAPATH is |
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55 | |
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56 | port ( |
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57 | |
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58 | -- Traffic Separator Interface |
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59 | |
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60 | PDU_DATA : in std_logic_vector(0 to 15); |
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61 | PDU_DATA_V : in std_logic; |
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62 | PDU_PAD : in std_logic; |
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63 | PDU_SCP : in std_logic; |
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64 | PDU_ECP : in std_logic; |
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65 | |
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66 | -- LocalLink PDU Interface |
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67 | |
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68 | RX_D : out std_logic_vector(0 to 15); |
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69 | RX_REM : out std_logic; |
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70 | RX_SRC_RDY_N : out std_logic; |
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71 | RX_SOF_N : out std_logic; |
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72 | RX_EOF_N : out std_logic; |
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73 | |
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74 | -- Error Interface |
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75 | |
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76 | FRAME_ERROR : out std_logic; |
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77 | |
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78 | -- System Interface |
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79 | |
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80 | USER_CLK : in std_logic; |
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81 | RESET : in std_logic |
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82 | |
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83 | ); |
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84 | |
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85 | end RX_LL_PDU_DATAPATH; |
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86 | |
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87 | |
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88 | architecture RTL of RX_LL_PDU_DATAPATH is |
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89 | |
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90 | --****************************Parameter Declarations************************** |
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91 | |
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92 | constant DLY : time := 1 ns; |
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93 | |
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94 | |
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95 | --****************************External Register Declarations************************** |
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96 | |
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97 | signal RX_D_Buffer : std_logic_vector(0 to 15); |
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98 | signal RX_REM_Buffer : std_logic; |
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99 | signal RX_SRC_RDY_N_Buffer : std_logic; |
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100 | signal RX_SOF_N_Buffer : std_logic; |
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101 | signal RX_EOF_N_Buffer : std_logic; |
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102 | signal FRAME_ERROR_Buffer : std_logic; |
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103 | |
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104 | |
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105 | --****************************Internal Register Declarations************************** |
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106 | signal storage_r : std_logic_vector(0 to 15); |
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107 | signal storage_v_r : std_logic; |
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108 | signal in_frame_r : std_logic; |
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109 | signal sof_in_storage_r : std_logic; |
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110 | signal pad_in_storage_r : std_logic; |
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111 | |
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112 | |
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113 | |
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114 | |
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115 | --*********************************Wire Declarations********************************** |
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116 | signal src_rdy_n_c : std_logic; |
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117 | signal storage_ce_c : std_logic; |
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118 | |
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119 | |
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120 | |
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121 | begin |
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122 | |
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123 | --*********************************Main Body of Code********************************** |
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124 | |
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125 | -- VHDL Helper Logic |
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126 | RX_D <= RX_D_Buffer; |
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127 | RX_REM <= RX_REM_Buffer; |
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128 | RX_SRC_RDY_N <= RX_SRC_RDY_N_Buffer; |
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129 | RX_SOF_N <= RX_SOF_N_Buffer; |
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130 | RX_EOF_N <= RX_EOF_N_Buffer; |
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131 | FRAME_ERROR <= FRAME_ERROR_Buffer; |
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132 | |
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133 | |
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134 | |
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135 | |
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136 | --All input goes into a storage register before it is sent on to the output |
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137 | process(USER_CLK) |
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138 | begin |
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139 | if(USER_CLK 'event and USER_CLK = '1') then |
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140 | if(storage_ce_c = '1') then |
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141 | storage_r <= PDU_DATA after DLY; |
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142 | end if; |
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143 | end if; |
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144 | end process; |
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145 | |
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146 | |
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147 | --Keep track of whether or not there is data in storage |
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148 | process(USER_CLK) |
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149 | begin |
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150 | if(USER_CLK 'event and USER_CLK = '1') then |
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151 | if(RESET= '1') then |
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152 | storage_v_r <= '0' after DLY; |
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153 | elsif(storage_ce_c = '1') then |
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154 | storage_v_r <= '1' after DLY; |
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155 | elsif(storage_v_r = '1') then |
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156 | storage_v_r <= src_rdy_n_c after DLY; |
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157 | end if; |
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158 | end if; |
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159 | end process; |
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160 | |
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161 | |
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162 | --Output data is registered |
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163 | process(USER_CLK) |
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164 | begin |
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165 | if(USER_CLK 'event and USER_CLK = '1') then |
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166 | RX_D_Buffer <= storage_r after DLY; |
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167 | end if; |
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168 | end process; |
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169 | |
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170 | |
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171 | --Assert the SRC_RDY_N signal when there is data in storage and incomiming data or the |
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172 | -- end of a frame |
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173 | src_rdy_n_c <= not (storage_v_r and (storage_ce_c or PDU_ECP)); |
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174 | |
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175 | |
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176 | --Register the SRC_RDY_N signal |
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177 | process(USER_CLK) |
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178 | begin |
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179 | if(USER_CLK 'event and USER_CLK = '1') then |
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180 | if(RESET = '1') then |
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181 | RX_SRC_RDY_N_Buffer <= '1' after DLY; |
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182 | else |
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183 | RX_SRC_RDY_N_Buffer <= src_rdy_n_c after DLY; |
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184 | end if; |
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185 | end if; |
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186 | end process; |
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187 | |
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188 | |
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189 | --Load data into storage when there is valid incoming data |
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190 | storage_ce_c <= in_frame_r and PDU_DATA_V; |
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191 | |
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192 | |
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193 | --Data is in a frame when it is preceded by an SOF followed by any number of non-ecp characters |
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194 | process(USER_CLK) |
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195 | begin |
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196 | if(USER_CLK 'event and USER_CLK = '1') then |
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197 | if(RESET = '1') then |
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198 | in_frame_r <= '0' after DLY; |
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199 | elsif(PDU_SCP = '1') then |
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200 | in_frame_r <= '1' after DLY; |
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201 | elsif(PDU_ECP = '1') then |
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202 | in_frame_r <= '0' after DLY; |
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203 | end if; |
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204 | end if; |
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205 | end process; |
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206 | |
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207 | |
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208 | --Hold start of frame until it can be asserted with data |
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209 | process(USER_CLK) |
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210 | begin |
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211 | if(USER_CLK 'event and USER_CLK = '1') then |
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212 | if(PDU_SCP = '1') then |
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213 | sof_in_storage_r <= '1' after DLY; |
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214 | elsif(sof_in_storage_r = '1') then |
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215 | sof_in_storage_r <= src_rdy_n_c after DLY; |
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216 | end if; |
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217 | end if; |
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218 | end process; |
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219 | |
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220 | |
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221 | --Register sof_in_storage for use on the LocalLink Interface |
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222 | process(USER_CLK) |
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223 | begin |
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224 | if(USER_CLK 'event and USER_CLK = '1') then |
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225 | RX_SOF_N_Buffer <= not sof_in_storage_r after DLY; |
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226 | end if; |
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227 | end process; |
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228 | |
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229 | |
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230 | --Register eof for use on the LocalLink Interface |
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231 | process(USER_CLK) |
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232 | begin |
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233 | if(USER_CLK 'event and USER_CLK = '1') then |
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234 | RX_EOF_N_Buffer <= not PDU_ECP after DLY; |
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235 | end if; |
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236 | end process; |
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237 | |
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238 | |
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239 | |
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240 | --Store the pad signal for any data that gets moved into storage |
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241 | process(USER_CLK) |
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242 | begin |
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243 | if(USER_CLK 'event and USER_CLK = '1') then |
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244 | if(storage_ce_c = '1') then |
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245 | pad_in_storage_r <= PDU_PAD after DLY; |
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246 | end if; |
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247 | end if; |
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248 | end process; |
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249 | |
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250 | |
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251 | --Register the pad signal for use on the LocalLink inteface |
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252 | process(USER_CLK) |
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253 | begin |
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254 | if(USER_CLK 'event and USER_CLK = '1') then |
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255 | RX_REM_Buffer <= not pad_in_storage_r after DLY; |
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256 | end if; |
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257 | end process; |
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258 | |
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259 | |
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260 | --Indicate a frame error when a start arrives inframe, and end arrives out |
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261 | -- of frame, or an end arrives with no data in storage, indicating an empty |
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262 | -- frame |
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263 | process(USER_CLK) |
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264 | begin |
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265 | if(USER_CLK 'event and USER_CLK = '1') then |
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266 | FRAME_ERROR_Buffer <= (PDU_SCP and in_frame_r) or |
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267 | (PDU_ECP and not in_frame_r) or |
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268 | (PDU_ECP and not storage_v_r) after DLY; |
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269 | end if; |
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270 | end process; |
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271 | |
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272 | |
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273 | |
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274 | |
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275 | end RTL; |
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276 | |
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277 | |
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