1 | -- |
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2 | -- Project: Aurora Module Generator version 2.4 |
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3 | -- |
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4 | -- Date: $Date: 2005/11/07 21:30:55 $ |
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5 | -- Tag: $Name: i+IP+98818 $ |
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6 | -- File: $RCSfile: sym_dec_vhd.ejava,v $ |
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7 | -- Rev: $Revision: 1.1.2.4 $ |
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8 | -- |
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9 | -- Company: Xilinx |
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10 | -- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone |
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11 | -- |
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12 | -- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR |
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13 | -- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING |
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14 | -- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY |
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15 | -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS |
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16 | -- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, |
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17 | -- APPLICATION OR STANDARD, XILINX IS MAKING NO |
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18 | -- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE |
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19 | -- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE |
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20 | -- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY |
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21 | -- REQUIRE FOR YOUR IMPLEMENTATION. XILINX |
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22 | -- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH |
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23 | -- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, |
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24 | -- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR |
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25 | -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE |
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26 | -- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES |
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27 | -- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
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28 | -- PURPOSE. |
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29 | -- |
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30 | -- (c) Copyright 2004 Xilinx, Inc. |
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31 | -- All rights reserved. |
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32 | -- |
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33 | |
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34 | -- |
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35 | -- SYM_DEC |
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36 | -- |
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37 | -- Author: Nigel Gulstone |
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38 | -- Xilinx - Embedded Networking System Engineering Group |
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39 | -- |
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40 | -- VHDL Translation: Brian Woodard |
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41 | -- Xilinx - Garden Valley Design Team |
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42 | -- |
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43 | -- Description: The SYM_DEC module is a symbol decoder for the 2-byte |
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44 | -- Aurora Lane. Its inputs are the raw data from the MGT. |
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45 | -- It word-aligns the regular data and decodes all of the |
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46 | -- Aurora control symbols. Its outputs are the word-aligned |
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47 | -- data and signals indicating the arrival of specific |
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48 | -- control characters. |
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49 | -- |
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50 | -- This module supports Immediate Mode Native Flow Control. |
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51 | -- |
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52 | |
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53 | library IEEE; |
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54 | use IEEE.STD_LOGIC_1164.all; |
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55 | use WORK.AURORA.all; |
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56 | |
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57 | entity SYM_DEC is |
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58 | |
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59 | port ( |
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60 | |
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61 | -- RX_LL Interface |
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62 | |
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63 | RX_PAD : out std_logic; -- LSByte is PAD. |
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64 | RX_PE_DATA : out std_logic_vector(0 to 15); -- Word aligned data from channel partner. |
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65 | RX_PE_DATA_V : out std_logic; -- Data is valid data and not a control character. |
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66 | RX_SCP : out std_logic; -- SCP symbol received. |
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67 | RX_ECP : out std_logic; -- ECP symbol received. |
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68 | RX_SNF : out std_logic; -- SNF symbol received. |
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69 | RX_FC_NB : out std_logic_vector(0 to 3); -- Flow Control size code. Valid with RX_SNF or RX_SUF. |
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70 | |
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71 | -- Lane Init SM Interface |
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72 | |
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73 | DO_WORD_ALIGN : in std_logic; -- Word alignment is allowed. |
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74 | RX_SP : out std_logic; -- SP sequence received with positive or negative data. |
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75 | RX_SPA : out std_logic; -- SPA sequence received. |
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76 | RX_NEG : out std_logic; -- Intverted data for SP or SPA received. |
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77 | |
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78 | -- Global Logic Interface |
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79 | |
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80 | GOT_A : out std_logic_vector(0 to 1); -- A character received on indicated byte(s). |
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81 | GOT_V : out std_logic; -- V sequence received. |
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82 | |
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83 | -- MGT Interface |
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84 | |
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85 | RX_DATA : in std_logic_vector(15 downto 0); -- Raw RX data from MGT. |
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86 | RX_CHAR_IS_K : in std_logic_vector(1 downto 0); -- Bits indicating which bytes are control characters. |
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87 | RX_CHAR_IS_COMMA : in std_logic_vector(1 downto 0); -- Rx'ed a comma. |
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88 | |
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89 | -- System Interface |
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90 | |
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91 | USER_CLK : in std_logic; -- System clock for all non-MGT Aurora Logic. |
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92 | RESET : in std_logic |
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93 | |
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94 | ); |
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95 | |
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96 | end SYM_DEC; |
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97 | |
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98 | architecture RTL of SYM_DEC is |
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99 | |
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100 | -- Parameter Declarations -- |
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101 | |
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102 | constant DLY : time := 1 ns; |
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103 | |
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104 | constant K_CHAR_0 : std_logic_vector(0 to 3) := X"B"; |
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105 | constant K_CHAR_1 : std_logic_vector(0 to 3) := X"C"; |
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106 | constant SP_DATA_0 : std_logic_vector(0 to 3) := X"4"; |
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107 | constant SP_DATA_1 : std_logic_vector(0 to 3) := X"A"; |
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108 | constant SPA_DATA_0 : std_logic_vector(0 to 3) := X"2"; |
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109 | constant SPA_DATA_1 : std_logic_vector(0 to 3) := X"C"; |
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110 | constant SP_NEG_DATA_0 : std_logic_vector(0 to 3) := X"B"; |
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111 | constant SP_NEG_DATA_1 : std_logic_vector(0 to 3) := X"5"; |
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112 | constant SPA_NEG_DATA_0 : std_logic_vector(0 to 3) := X"D"; |
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113 | constant SPA_NEG_DATA_1 : std_logic_vector(0 to 3) := X"3"; |
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114 | constant PAD_0 : std_logic_vector(0 to 3) := X"9"; |
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115 | constant PAD_1 : std_logic_vector(0 to 3) := X"C"; |
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116 | constant SCP_0 : std_logic_vector(0 to 3) := X"5"; |
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117 | constant SCP_1 : std_logic_vector(0 to 3) := X"C"; |
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118 | constant SCP_2 : std_logic_vector(0 to 3) := X"F"; |
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119 | constant SCP_3 : std_logic_vector(0 to 3) := X"B"; |
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120 | constant ECP_0 : std_logic_vector(0 to 3) := X"F"; |
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121 | constant ECP_1 : std_logic_vector(0 to 3) := X"D"; |
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122 | constant ECP_2 : std_logic_vector(0 to 3) := X"F"; |
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123 | constant ECP_3 : std_logic_vector(0 to 3) := X"E"; |
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124 | constant SNF_0 : std_logic_vector(0 to 3) := X"D"; |
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125 | constant SNF_1 : std_logic_vector(0 to 3) := X"C"; |
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126 | constant A_CHAR_0 : std_logic_vector(0 to 3) := X"7"; |
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127 | constant A_CHAR_1 : std_logic_vector(0 to 3) := X"C"; |
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128 | constant VER_DATA_0 : std_logic_vector(0 to 3) := X"E"; |
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129 | constant VER_DATA_1 : std_logic_vector(0 to 3) := X"8"; |
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130 | |
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131 | -- External Register Declarations -- |
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132 | |
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133 | signal RX_PAD_Buffer : std_logic; |
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134 | signal RX_PE_DATA_Buffer : std_logic_vector(0 to 15); |
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135 | signal RX_PE_DATA_V_Buffer : std_logic; |
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136 | signal RX_SCP_Buffer : std_logic; |
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137 | signal RX_ECP_Buffer : std_logic; |
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138 | signal RX_SNF_Buffer : std_logic; |
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139 | signal RX_FC_NB_Buffer : std_logic_vector(0 to 3); |
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140 | signal RX_SP_Buffer : std_logic; |
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141 | signal RX_SPA_Buffer : std_logic; |
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142 | signal RX_NEG_Buffer : std_logic; |
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143 | signal GOT_A_Buffer : std_logic_vector(0 to 1); |
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144 | signal GOT_V_Buffer : std_logic; |
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145 | |
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146 | -- Internal Register Declarations -- |
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147 | |
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148 | signal left_aligned_r : std_logic; |
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149 | signal previous_cycle_data_r : std_logic_vector(0 to 7); |
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150 | signal previous_cycle_control_r : std_logic; |
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151 | signal prev_beat_sp_r : std_logic; |
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152 | signal prev_beat_spa_r : std_logic; |
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153 | signal word_aligned_data_r : std_logic_vector(0 to 15); |
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154 | signal word_aligned_control_bits_r : std_logic_vector(0 to 1); |
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155 | signal rx_pe_data_r : std_logic_vector(0 to 15); |
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156 | signal rx_pe_control_r : std_logic_vector(0 to 1); |
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157 | signal rx_pad_d_r : std_logic_vector(0 to 1); |
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158 | signal rx_scp_d_r : std_logic_vector(0 to 3); |
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159 | signal rx_ecp_d_r : std_logic_vector(0 to 3); |
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160 | signal rx_snf_d_r : std_logic_vector(0 to 1); |
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161 | signal prev_beat_sp_d_r : std_logic_vector(0 to 3); |
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162 | signal prev_beat_spa_d_r : std_logic_vector(0 to 3); |
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163 | signal rx_sp_d_r : std_logic_vector(0 to 3); |
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164 | signal rx_spa_d_r : std_logic_vector(0 to 3); |
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165 | signal rx_sp_neg_d_r : std_logic_vector(0 to 1); |
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166 | signal rx_spa_neg_d_r : std_logic_vector(0 to 1); |
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167 | signal prev_beat_v_d_r : std_logic_vector(0 to 3); |
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168 | signal prev_beat_v_r : std_logic; |
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169 | signal rx_v_d_r : std_logic_vector(0 to 3); |
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170 | signal got_a_d_r : std_logic_vector(0 to 3); |
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171 | signal first_v_received_r : std_logic := '0'; |
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172 | |
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173 | -- Wire Declarations -- |
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174 | |
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175 | signal got_v_c : std_logic; |
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176 | |
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177 | begin |
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178 | |
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179 | RX_PAD <= RX_PAD_Buffer; |
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180 | RX_PE_DATA <= RX_PE_DATA_Buffer; |
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181 | RX_PE_DATA_V <= RX_PE_DATA_V_Buffer; |
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182 | RX_SCP <= RX_SCP_Buffer; |
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183 | RX_ECP <= RX_ECP_Buffer; |
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184 | RX_SNF <= RX_SNF_Buffer; |
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185 | RX_FC_NB <= RX_FC_NB_Buffer; |
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186 | RX_SP <= RX_SP_Buffer; |
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187 | RX_SPA <= RX_SPA_Buffer; |
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188 | RX_NEG <= RX_NEG_Buffer; |
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189 | GOT_A <= GOT_A_Buffer; |
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190 | GOT_V <= GOT_V_Buffer; |
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191 | |
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192 | -- Main Body of Code -- |
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193 | |
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194 | -- Word Alignment -- |
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195 | |
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196 | -- Determine whether the lane is aligned to the left byte (MS byte) or the |
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197 | -- right byte (LS byte). This information is used for word alignment. To |
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198 | -- prevent the word align from changing during normal operation, we do word |
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199 | -- alignment only when it is allowed by the lane_init_sm. |
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200 | |
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201 | process (USER_CLK) |
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202 | |
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203 | variable vec : std_logic_vector(0 to 3); |
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204 | |
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205 | begin |
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206 | |
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207 | if (USER_CLK 'event and USER_CLK = '1') then |
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208 | |
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209 | if ((DO_WORD_ALIGN and not first_v_received_r) = '1') then |
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210 | |
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211 | vec := RX_CHAR_IS_COMMA & RX_CHAR_IS_K; |
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212 | |
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213 | case vec is |
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214 | |
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215 | when "1010" => left_aligned_r <= '1' after DLY; |
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216 | when "0101" => left_aligned_r <= '0' after DLY; |
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217 | when others => left_aligned_r <= left_aligned_r after DLY; |
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218 | |
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219 | end case; |
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220 | |
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221 | end if; |
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222 | |
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223 | end if; |
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224 | |
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225 | end process; |
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226 | |
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227 | |
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228 | -- Store the LS byte from the previous cycle. If the lane is aligned on |
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229 | -- the LS byte, we use it as the MS byte on the current cycle. |
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230 | |
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231 | process (USER_CLK) |
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232 | |
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233 | begin |
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234 | |
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235 | if (USER_CLK 'event and USER_CLK = '1') then |
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236 | |
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237 | previous_cycle_data_r(0) <= RX_DATA(7) after DLY; |
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238 | previous_cycle_data_r(1) <= RX_DATA(6) after DLY; |
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239 | previous_cycle_data_r(2) <= RX_DATA(5) after DLY; |
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240 | previous_cycle_data_r(3) <= RX_DATA(4) after DLY; |
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241 | previous_cycle_data_r(4) <= RX_DATA(3) after DLY; |
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242 | previous_cycle_data_r(5) <= RX_DATA(2) after DLY; |
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243 | previous_cycle_data_r(6) <= RX_DATA(1) after DLY; |
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244 | previous_cycle_data_r(7) <= RX_DATA(0) after DLY; |
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245 | |
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246 | end if; |
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247 | |
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248 | end process; |
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249 | |
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250 | |
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251 | -- Store the control bit from the previous cycle LS byte. It becomes the |
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252 | -- control bit for the MS byte on this cycle if the lane is aligned to the |
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253 | -- LS byte. |
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254 | |
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255 | process (USER_CLK) |
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256 | |
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257 | begin |
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258 | |
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259 | if (USER_CLK 'event and USER_CLK = '1') then |
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260 | |
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261 | previous_cycle_control_r <= RX_CHAR_IS_K(0) after DLY; |
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262 | |
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263 | end if; |
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264 | |
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265 | end process; |
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266 | |
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267 | |
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268 | -- Select the word-aligned MS byte. Use the current MS byte if the data is |
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269 | -- left-aligned, otherwise use the LS byte from the previous cycle. |
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270 | |
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271 | process (USER_CLK) |
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272 | |
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273 | begin |
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274 | |
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275 | if (USER_CLK 'event and USER_CLK = '1') then |
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276 | |
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277 | if (left_aligned_r = '1') then |
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278 | |
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279 | word_aligned_data_r(0) <= RX_DATA(15) after DLY; |
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280 | word_aligned_data_r(1) <= RX_DATA(14) after DLY; |
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281 | word_aligned_data_r(2) <= RX_DATA(13) after DLY; |
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282 | word_aligned_data_r(3) <= RX_DATA(12) after DLY; |
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283 | word_aligned_data_r(4) <= RX_DATA(11) after DLY; |
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284 | word_aligned_data_r(5) <= RX_DATA(10) after DLY; |
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285 | word_aligned_data_r(6) <= RX_DATA(9) after DLY; |
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286 | word_aligned_data_r(7) <= RX_DATA(8) after DLY; |
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287 | |
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288 | else |
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289 | |
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290 | word_aligned_data_r(0 to 7) <= previous_cycle_data_r after DLY; |
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291 | |
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292 | end if; |
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293 | |
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294 | end if; |
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295 | |
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296 | end process; |
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297 | |
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298 | |
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299 | -- Select the word-aligned LS byte. Use the current LSByte if the data is |
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300 | -- right-aligned, otherwise use the current MS byte. |
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301 | |
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302 | process (USER_CLK) |
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303 | |
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304 | begin |
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305 | |
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306 | if (USER_CLK 'event and USER_CLK = '1') then |
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307 | |
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308 | if (left_aligned_r = '1') then |
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309 | |
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310 | word_aligned_data_r(8) <= RX_DATA(7) after DLY; |
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311 | word_aligned_data_r(9) <= RX_DATA(6) after DLY; |
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312 | word_aligned_data_r(10) <= RX_DATA(5) after DLY; |
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313 | word_aligned_data_r(11) <= RX_DATA(4) after DLY; |
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314 | word_aligned_data_r(12) <= RX_DATA(3) after DLY; |
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315 | word_aligned_data_r(13) <= RX_DATA(2) after DLY; |
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316 | word_aligned_data_r(14) <= RX_DATA(1) after DLY; |
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317 | word_aligned_data_r(15) <= RX_DATA(0) after DLY; |
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318 | |
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319 | else |
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320 | |
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321 | word_aligned_data_r(8) <= RX_DATA(15) after DLY; |
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322 | word_aligned_data_r(9) <= RX_DATA(14) after DLY; |
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323 | word_aligned_data_r(10) <= RX_DATA(13) after DLY; |
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324 | word_aligned_data_r(11) <= RX_DATA(12) after DLY; |
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325 | word_aligned_data_r(12) <= RX_DATA(11) after DLY; |
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326 | word_aligned_data_r(13) <= RX_DATA(10) after DLY; |
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327 | word_aligned_data_r(14) <= RX_DATA(9) after DLY; |
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328 | word_aligned_data_r(15) <= RX_DATA(8) after DLY; |
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329 | |
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330 | end if; |
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331 | |
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332 | end if; |
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333 | |
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334 | end process; |
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335 | |
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336 | |
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337 | -- Select the word-aligned MS byte control bit. Use the current MSByte's |
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338 | -- control bit if the data is left-aligned, otherwise use the LS byte's |
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339 | -- control bit from the previous cycle. |
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340 | |
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341 | process (USER_CLK) |
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342 | |
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343 | begin |
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344 | |
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345 | if (USER_CLK 'event and USER_CLK = '1') then |
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346 | |
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347 | if (left_aligned_r = '1') then |
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348 | |
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349 | word_aligned_control_bits_r(0) <= RX_CHAR_IS_K(1) after DLY; |
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350 | |
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351 | else |
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352 | |
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353 | word_aligned_control_bits_r(0) <= previous_cycle_control_r after DLY; |
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354 | |
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355 | end if; |
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356 | |
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357 | end if; |
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358 | |
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359 | end process; |
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360 | |
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361 | |
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362 | -- Select the word-aligned LS byte control bit. Use the current LSByte's control |
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363 | -- bit if the data is left-aligned, otherwise use the current MS byte's control bit. |
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364 | |
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365 | process (USER_CLK) |
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366 | |
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367 | begin |
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368 | |
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369 | if (USER_CLK 'event and USER_CLK = '1') then |
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370 | |
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371 | if (left_aligned_r = '1') then |
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372 | |
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373 | word_aligned_control_bits_r(1) <= RX_CHAR_IS_K(0) after DLY; |
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374 | |
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375 | else |
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376 | |
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377 | word_aligned_control_bits_r(1) <= RX_CHAR_IS_K(1) after DLY; |
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378 | |
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379 | end if; |
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380 | |
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381 | end if; |
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382 | |
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383 | end process; |
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384 | |
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385 | |
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386 | -- Pipeline the word-aligned data for 1 cycle to match the Decodes. |
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387 | |
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388 | process (USER_CLK) |
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389 | |
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390 | begin |
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391 | |
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392 | if (USER_CLK 'event and USER_CLK = '1') then |
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393 | |
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394 | rx_pe_data_r <= word_aligned_data_r after DLY; |
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395 | |
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396 | end if; |
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397 | |
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398 | end process; |
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399 | |
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400 | |
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401 | -- Register the pipelined word-aligned data for the RX_LL interface. |
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402 | |
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403 | process (USER_CLK) |
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404 | |
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405 | begin |
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406 | |
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407 | if (USER_CLK 'event and USER_CLK = '1') then |
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408 | |
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409 | RX_PE_DATA_Buffer <= rx_pe_data_r after DLY; |
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410 | |
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411 | end if; |
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412 | |
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413 | end process; |
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414 | |
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415 | |
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416 | -- Decode Control Symbols -- |
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417 | |
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418 | -- All decodes are pipelined to keep the number of logic levels to a minimum. |
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419 | |
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420 | -- Delay the control bits: they are most often used in the second stage of |
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421 | -- the decoding process. |
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422 | |
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423 | process (USER_CLK) |
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424 | |
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425 | begin |
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426 | |
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427 | if (USER_CLK 'event and USER_CLK = '1') then |
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428 | |
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429 | rx_pe_control_r <= word_aligned_control_bits_r after DLY; |
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430 | |
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431 | end if; |
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432 | |
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433 | end process; |
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434 | |
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435 | |
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436 | -- Decode PAD |
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437 | |
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438 | process (USER_CLK) |
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439 | |
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440 | begin |
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441 | |
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442 | if (USER_CLK 'event and USER_CLK = '1') then |
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443 | |
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444 | rx_pad_d_r(0) <= std_bool(word_aligned_data_r(8 to 11) = PAD_0) after DLY; |
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445 | rx_pad_d_r(1) <= std_bool(word_aligned_data_r(12 to 15) = PAD_1) after DLY; |
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446 | |
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447 | end if; |
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448 | |
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449 | end process; |
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450 | |
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451 | |
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452 | process (USER_CLK) |
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453 | |
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454 | begin |
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455 | |
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456 | if (USER_CLK 'event and USER_CLK = '1') then |
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457 | |
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458 | RX_PAD_Buffer <= std_bool((rx_pad_d_r = "11") and (rx_pe_control_r = "01")) after DLY; |
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459 | |
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460 | end if; |
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461 | |
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462 | end process; |
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463 | |
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464 | |
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465 | -- Decode RX_PE_DATA_V |
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466 | |
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467 | process (USER_CLK) |
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468 | |
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469 | begin |
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470 | |
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471 | if (USER_CLK 'event and USER_CLK = '1') then |
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472 | |
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473 | RX_PE_DATA_V_Buffer <= not rx_pe_control_r(0) after DLY; |
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474 | |
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475 | end if; |
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476 | |
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477 | end process; |
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478 | |
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479 | |
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480 | -- Decode RX_SCP |
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481 | |
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482 | process (USER_CLK) |
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483 | |
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484 | begin |
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485 | |
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486 | if (USER_CLK 'event and USER_CLK = '1') then |
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487 | |
---|
488 | rx_scp_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = SCP_0) after DLY; |
---|
489 | rx_scp_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = SCP_1) after DLY; |
---|
490 | rx_scp_d_r(2) <= std_bool(word_aligned_data_r(8 to 11) = SCP_2) after DLY; |
---|
491 | rx_scp_d_r(3) <= std_bool(word_aligned_data_r(12 to 15) = SCP_3) after DLY; |
---|
492 | |
---|
493 | end if; |
---|
494 | |
---|
495 | end process; |
---|
496 | |
---|
497 | |
---|
498 | process (USER_CLK) |
---|
499 | |
---|
500 | begin |
---|
501 | |
---|
502 | if (USER_CLK 'event and USER_CLK = '1') then |
---|
503 | |
---|
504 | RX_SCP_Buffer <= rx_pe_control_r(0) and |
---|
505 | rx_pe_control_r(1) and |
---|
506 | rx_scp_d_r(0) and |
---|
507 | rx_scp_d_r(1) and |
---|
508 | rx_scp_d_r(2) and |
---|
509 | rx_scp_d_r(3) after DLY; |
---|
510 | |
---|
511 | end if; |
---|
512 | |
---|
513 | end process; |
---|
514 | |
---|
515 | |
---|
516 | -- Decode RX_ECP |
---|
517 | |
---|
518 | process (USER_CLK) |
---|
519 | |
---|
520 | begin |
---|
521 | |
---|
522 | if (USER_CLK 'event and USER_CLK = '1') then |
---|
523 | |
---|
524 | rx_ecp_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = ECP_0) after DLY; |
---|
525 | rx_ecp_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = ECP_1) after DLY; |
---|
526 | rx_ecp_d_r(2) <= std_bool(word_aligned_data_r(8 to 11) = ECP_2) after DLY; |
---|
527 | rx_ecp_d_r(3) <= std_bool(word_aligned_data_r(12 to 15) = ECP_3) after DLY; |
---|
528 | |
---|
529 | end if; |
---|
530 | |
---|
531 | end process; |
---|
532 | |
---|
533 | |
---|
534 | process (USER_CLK) |
---|
535 | |
---|
536 | begin |
---|
537 | |
---|
538 | if (USER_CLK 'event and USER_CLK = '1') then |
---|
539 | |
---|
540 | RX_ECP_Buffer <= rx_pe_control_r(0) and |
---|
541 | rx_pe_control_r(1) and |
---|
542 | rx_ecp_d_r(0) and |
---|
543 | rx_ecp_d_r(1) and |
---|
544 | rx_ecp_d_r(2) and |
---|
545 | rx_ecp_d_r(3) after DLY; |
---|
546 | |
---|
547 | end if; |
---|
548 | |
---|
549 | end process; |
---|
550 | |
---|
551 | |
---|
552 | -- Decode RX_SNF |
---|
553 | |
---|
554 | process (USER_CLK) |
---|
555 | |
---|
556 | begin |
---|
557 | |
---|
558 | if (USER_CLK 'event and USER_CLK = '1') then |
---|
559 | |
---|
560 | rx_snf_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = SNF_0) after DLY; |
---|
561 | rx_snf_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = SNF_1) after DLY; |
---|
562 | |
---|
563 | end if; |
---|
564 | |
---|
565 | end process; |
---|
566 | |
---|
567 | |
---|
568 | process (USER_CLK) |
---|
569 | |
---|
570 | begin |
---|
571 | |
---|
572 | if (USER_CLK 'event and USER_CLK = '1') then |
---|
573 | |
---|
574 | RX_SNF_Buffer <= rx_pe_control_r(0) and |
---|
575 | rx_snf_d_r(0) and |
---|
576 | rx_snf_d_r(1) after DLY; |
---|
577 | |
---|
578 | end if; |
---|
579 | |
---|
580 | end process; |
---|
581 | |
---|
582 | |
---|
583 | -- Extract the Flow Control Size code and register it for the RX_LL interface. |
---|
584 | |
---|
585 | process (USER_CLK) |
---|
586 | |
---|
587 | begin |
---|
588 | |
---|
589 | if (USER_CLK 'event and USER_CLK = '1') then |
---|
590 | |
---|
591 | RX_FC_NB_Buffer <= rx_pe_data_r(8 to 11) after DLY; |
---|
592 | |
---|
593 | end if; |
---|
594 | |
---|
595 | end process; |
---|
596 | |
---|
597 | |
---|
598 | -- For an SP sequence to be valid, there must be 2 bytes of SP Data preceded |
---|
599 | -- by a Comma and an SP Data byte in the MS byte and LS byte positions |
---|
600 | -- respectively. This flop stores the decode of the Comma and SP Data byte |
---|
601 | -- combination from the previous cycle. Data can be positive or negative. |
---|
602 | |
---|
603 | process (USER_CLK) |
---|
604 | |
---|
605 | begin |
---|
606 | |
---|
607 | if (USER_CLK 'event and USER_CLK = '1') then |
---|
608 | |
---|
609 | prev_beat_sp_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = K_CHAR_0) after DLY; |
---|
610 | prev_beat_sp_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = K_CHAR_1) after DLY; |
---|
611 | prev_beat_sp_d_r(2) <= std_bool((word_aligned_data_r(8 to 11) = SP_DATA_0) or |
---|
612 | (word_aligned_data_r(8 to 11) = SP_NEG_DATA_0)) after DLY; |
---|
613 | prev_beat_sp_d_r(3) <= std_bool((word_aligned_data_r(12 to 15) = SP_DATA_1) or |
---|
614 | (word_aligned_data_r(12 to 15) = SP_NEG_DATA_1)) after DLY; |
---|
615 | |
---|
616 | end if; |
---|
617 | |
---|
618 | end process; |
---|
619 | |
---|
620 | |
---|
621 | process (USER_CLK) |
---|
622 | |
---|
623 | begin |
---|
624 | |
---|
625 | if (USER_CLK 'event and USER_CLK = '1') then |
---|
626 | |
---|
627 | prev_beat_sp_r <= std_bool((rx_pe_control_r = "10") and |
---|
628 | (prev_beat_sp_d_r = "1111")) after DLY; |
---|
629 | |
---|
630 | end if; |
---|
631 | |
---|
632 | end process; |
---|
633 | |
---|
634 | |
---|
635 | -- This flow stores the decode of a Comma and SPA Data byte combination from the |
---|
636 | -- previous cycle. It is used along with decodes for SPA data in the current |
---|
637 | -- cycle to determine whether an SPA sequence was received. |
---|
638 | |
---|
639 | process (USER_CLK) |
---|
640 | |
---|
641 | begin |
---|
642 | |
---|
643 | if (USER_CLK 'event and USER_CLK = '1') then |
---|
644 | |
---|
645 | prev_beat_spa_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = K_CHAR_0) after DLY; |
---|
646 | prev_beat_spa_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = K_CHAR_1) after DLY; |
---|
647 | prev_beat_spa_d_r(2) <= std_bool(word_aligned_data_r(8 to 11) = SPA_DATA_0) after DLY; |
---|
648 | prev_beat_spa_d_r(3) <= std_bool(word_aligned_data_r(12 to 15) = SPA_DATA_1) after DLY; |
---|
649 | |
---|
650 | end if; |
---|
651 | |
---|
652 | end process; |
---|
653 | |
---|
654 | |
---|
655 | process (USER_CLK) |
---|
656 | |
---|
657 | begin |
---|
658 | |
---|
659 | if (USER_CLK 'event and USER_CLK = '1') then |
---|
660 | |
---|
661 | prev_beat_spa_r <= std_bool((rx_pe_control_r = "10") and |
---|
662 | (prev_beat_spa_d_r = "1111")) after DLY; |
---|
663 | |
---|
664 | end if; |
---|
665 | |
---|
666 | end process; |
---|
667 | |
---|
668 | |
---|
669 | -- Indicate the SP sequence was received. |
---|
670 | |
---|
671 | process (USER_CLK) |
---|
672 | |
---|
673 | begin |
---|
674 | |
---|
675 | if (USER_CLK 'event and USER_CLK = '1') then |
---|
676 | |
---|
677 | rx_sp_d_r(0) <= std_bool((word_aligned_data_r(0 to 3) = SP_DATA_0) or |
---|
678 | (word_aligned_data_r(0 to 3) = SP_NEG_DATA_0)) after DLY; |
---|
679 | rx_sp_d_r(1) <= std_bool((word_aligned_data_r(4 to 7) = SP_DATA_1) or |
---|
680 | (word_aligned_data_r(4 to 7) = SP_NEG_DATA_1)) after DLY; |
---|
681 | rx_sp_d_r(2) <= std_bool((word_aligned_data_r(8 to 11) = SP_DATA_0) or |
---|
682 | (word_aligned_data_r(8 to 11) = SP_NEG_DATA_0)) after DLY; |
---|
683 | rx_sp_d_r(3) <= std_bool((word_aligned_data_r(12 to 15) = SP_DATA_1) or |
---|
684 | (word_aligned_data_r(12 to 15) = SP_NEG_DATA_1)) after DLY; |
---|
685 | |
---|
686 | end if; |
---|
687 | |
---|
688 | end process; |
---|
689 | |
---|
690 | |
---|
691 | process (USER_CLK) |
---|
692 | |
---|
693 | begin |
---|
694 | |
---|
695 | if (USER_CLK 'event and USER_CLK = '1') then |
---|
696 | |
---|
697 | RX_SP_Buffer <= prev_beat_sp_r and |
---|
698 | std_bool((rx_pe_control_r = "00") and |
---|
699 | (rx_sp_d_r = "1111")) after DLY; |
---|
700 | |
---|
701 | end if; |
---|
702 | |
---|
703 | end process; |
---|
704 | |
---|
705 | |
---|
706 | -- Indicate the SPA sequence was received. |
---|
707 | |
---|
708 | process (USER_CLK) |
---|
709 | |
---|
710 | begin |
---|
711 | |
---|
712 | if (USER_CLK 'event and USER_CLK = '1') then |
---|
713 | |
---|
714 | rx_spa_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = SPA_DATA_0) after DLY; |
---|
715 | rx_spa_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = SPA_DATA_1) after DLY; |
---|
716 | rx_spa_d_r(2) <= std_bool(word_aligned_data_r(8 to 11) = SPA_DATA_0) after DLY; |
---|
717 | rx_spa_d_r(3) <= std_bool(word_aligned_data_r(12 to 15) = SPA_DATA_1) after DLY; |
---|
718 | |
---|
719 | end if; |
---|
720 | |
---|
721 | end process; |
---|
722 | |
---|
723 | |
---|
724 | process (USER_CLK) |
---|
725 | |
---|
726 | begin |
---|
727 | |
---|
728 | if (USER_CLK 'event and USER_CLK = '1') then |
---|
729 | |
---|
730 | RX_SPA_Buffer <= prev_beat_spa_r and |
---|
731 | std_bool((rx_pe_control_r = "00") and |
---|
732 | (rx_spa_d_r = "1111")) after DLY; |
---|
733 | |
---|
734 | end if; |
---|
735 | |
---|
736 | end process; |
---|
737 | |
---|
738 | |
---|
739 | -- Indicate reversed data received. We look only at the word-aligned LS byte |
---|
740 | -- which, during an /SP/ or /SPA/ sequence, will always contain a data byte. |
---|
741 | |
---|
742 | process (USER_CLK) |
---|
743 | |
---|
744 | begin |
---|
745 | |
---|
746 | if (USER_CLK 'event and USER_CLK = '1') then |
---|
747 | |
---|
748 | rx_sp_neg_d_r(0) <= std_bool(word_aligned_data_r(8 to 11) = SP_NEG_DATA_0) after DLY; |
---|
749 | rx_sp_neg_d_r(1) <= std_bool(word_aligned_data_r(12 to 15) = SP_NEG_DATA_1) after DLY; |
---|
750 | rx_spa_neg_d_r(0) <= std_bool(word_aligned_data_r(8 to 11) = SPA_NEG_DATA_0) after DLY; |
---|
751 | rx_spa_neg_d_r(1) <= std_bool(word_aligned_data_r(12 to 15) = SPA_NEG_DATA_1) after DLY; |
---|
752 | |
---|
753 | end if; |
---|
754 | |
---|
755 | end process; |
---|
756 | |
---|
757 | |
---|
758 | process (USER_CLK) |
---|
759 | |
---|
760 | begin |
---|
761 | |
---|
762 | if (USER_CLK 'event and USER_CLK = '1') then |
---|
763 | |
---|
764 | RX_NEG_Buffer <= not rx_pe_control_r(1) and |
---|
765 | std_bool((rx_sp_neg_d_r = "11") or |
---|
766 | (rx_spa_neg_d_r = "11")) after DLY; |
---|
767 | |
---|
768 | end if; |
---|
769 | |
---|
770 | end process; |
---|
771 | |
---|
772 | |
---|
773 | -- GOT_A is decoded from the non_word-aligned input. |
---|
774 | |
---|
775 | process (USER_CLK) |
---|
776 | |
---|
777 | begin |
---|
778 | |
---|
779 | if (USER_CLK 'event and USER_CLK = '1') then |
---|
780 | |
---|
781 | got_a_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = A_CHAR_0) after DLY; |
---|
782 | got_a_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = A_CHAR_1) after DLY; |
---|
783 | got_a_d_r(2) <= std_bool(word_aligned_data_r(8 to 11) = A_CHAR_0) after DLY; |
---|
784 | got_a_d_r(3) <= std_bool(word_aligned_data_r(12 to 15) = A_CHAR_1) after DLY; |
---|
785 | |
---|
786 | end if; |
---|
787 | |
---|
788 | end process; |
---|
789 | |
---|
790 | |
---|
791 | process (USER_CLK) |
---|
792 | |
---|
793 | begin |
---|
794 | |
---|
795 | if (USER_CLK 'event and USER_CLK = '1') then |
---|
796 | |
---|
797 | GOT_A_Buffer(0) <= rx_pe_control_r(0) and std_bool(got_a_d_r(0 to 1) = "11") after DLY; |
---|
798 | GOT_A_Buffer(1) <= rx_pe_control_r(1) and std_bool(got_a_d_r(2 to 3) = "11") after DLY; |
---|
799 | |
---|
800 | end if; |
---|
801 | |
---|
802 | end process; |
---|
803 | |
---|
804 | |
---|
805 | -- Verification symbol decode -- |
---|
806 | |
---|
807 | -- This flow stores the decode of a Comma and SPA Data byte combination from the |
---|
808 | -- previous cycle. It is used along with decodes for SPA data in the current |
---|
809 | -- cycle to determine whether an SPA sequence was received. |
---|
810 | |
---|
811 | process (USER_CLK) |
---|
812 | |
---|
813 | begin |
---|
814 | |
---|
815 | if (USER_CLK 'event and USER_CLK = '1') then |
---|
816 | |
---|
817 | prev_beat_v_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = K_CHAR_0) after DLY; |
---|
818 | prev_beat_v_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = K_CHAR_1) after DLY; |
---|
819 | prev_beat_v_d_r(2) <= std_bool(word_aligned_data_r(8 to 11) = VER_DATA_0) after DLY; |
---|
820 | prev_beat_v_d_r(3) <= std_bool(word_aligned_data_r(12 to 15) = VER_DATA_1) after DLY; |
---|
821 | |
---|
822 | end if; |
---|
823 | |
---|
824 | end process; |
---|
825 | |
---|
826 | |
---|
827 | process (USER_CLK) |
---|
828 | |
---|
829 | begin |
---|
830 | |
---|
831 | if (USER_CLK 'event and USER_CLK = '1') then |
---|
832 | |
---|
833 | prev_beat_v_r <= std_bool((rx_pe_control_r = "10") and |
---|
834 | (prev_beat_v_d_r = "1111")) after DLY; |
---|
835 | |
---|
836 | end if; |
---|
837 | |
---|
838 | end process; |
---|
839 | |
---|
840 | |
---|
841 | -- Indicate the SP sequence was received. |
---|
842 | |
---|
843 | process (USER_CLK) |
---|
844 | |
---|
845 | begin |
---|
846 | |
---|
847 | if (USER_CLK 'event and USER_CLK = '1') then |
---|
848 | |
---|
849 | rx_v_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = VER_DATA_0) after DLY; |
---|
850 | rx_v_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = VER_DATA_1) after DLY; |
---|
851 | rx_v_d_r(2) <= std_bool(word_aligned_data_r(8 to 11) = VER_DATA_0) after DLY; |
---|
852 | rx_v_d_r(3) <= std_bool(word_aligned_data_r(12 to 15) = VER_DATA_1) after DLY; |
---|
853 | |
---|
854 | end if; |
---|
855 | |
---|
856 | end process; |
---|
857 | |
---|
858 | |
---|
859 | got_v_c <= prev_beat_v_r and |
---|
860 | std_bool((rx_pe_control_r = "00") and |
---|
861 | (rx_v_d_r = "1111")); |
---|
862 | |
---|
863 | process (USER_CLK) |
---|
864 | |
---|
865 | begin |
---|
866 | |
---|
867 | if (USER_CLK 'event and USER_CLK = '1') then |
---|
868 | |
---|
869 | GOT_V_Buffer <= got_v_c after DLY; |
---|
870 | |
---|
871 | end if; |
---|
872 | |
---|
873 | end process; |
---|
874 | |
---|
875 | |
---|
876 | -- Remember that the first V sequence has been detected. |
---|
877 | |
---|
878 | process (USER_CLK) |
---|
879 | |
---|
880 | begin |
---|
881 | |
---|
882 | if (USER_CLK 'event and USER_CLK = '1') then |
---|
883 | |
---|
884 | if (RESET = '1') then |
---|
885 | |
---|
886 | first_v_received_r <= '0' after DLY; |
---|
887 | |
---|
888 | else |
---|
889 | |
---|
890 | if (got_v_c = '1') then |
---|
891 | |
---|
892 | first_v_received_r <= '1' after DLY; |
---|
893 | |
---|
894 | end if; |
---|
895 | |
---|
896 | end if; |
---|
897 | |
---|
898 | end if; |
---|
899 | |
---|
900 | end process; |
---|
901 | |
---|
902 | end RTL; |
---|