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1 | library ieee; |
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2 | use ieee.std_logic_1164.all; |
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3 | use ieee.std_logic_arith.all; |
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4 | use ieee.std_logic_unsigned.all; |
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5 | |
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6 | entity tx_ff_ctrl is |
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7 | port ( |
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8 | tx_wr : in std_logic; |
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9 | tx_wdata :in std_logic_vector(15 downto 0); |
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10 | tx_rdy :out std_logic ; |
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11 | tx_first :in std_logic; |
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12 | tx_last :in std_logic ; |
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13 | tx_en :in std_logic ; |
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14 | |
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15 | tx_ff_wr :out std_logic; |
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16 | tx_ff_full :in std_logic ; |
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17 | tx_ff_wdata :out std_logic_vector(17 downto 0) ; |
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18 | tx_ff_almost_full : in std_logic; |
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19 | aur_lane_up :in std_logic |
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20 | ); |
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21 | end tx_ff_ctrl; |
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22 | |
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23 | |
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24 | architecture tx_ff_ctrl_b1 of tx_ff_ctrl is |
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25 | begin |
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26 | |
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27 | tx_rdy <= (not tx_ff_almost_full) and aur_lane_up and tx_en; |
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28 | |
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29 | |
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30 | |
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31 | tx_ff_Wr <= tx_wr and (not tx_ff_full) and aur_lane_up and tx_en; |
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32 | |
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33 | |
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34 | |
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35 | tx_ff_wdata <= tx_last&tx_first&tx_wdata; |
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36 | |
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37 | end tx_ff_ctrl_b1; |
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