1 | //-------------------------------------------------------------------------------------------- |
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2 | // ____ ____ |
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3 | // / /\/ / |
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4 | // /___/ \ / Vendor: Xilinx |
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5 | // \ \ \/ Version : 1.0 |
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6 | // \ \ Application : NULL MGT Tile |
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7 | // / / Filename : null_pair_example.v |
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8 | // /___/ /\ Date : 10/07/2005 |
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9 | // \ \ / \ |
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10 | // \___\/\___\ |
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11 | // |
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12 | // |
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13 | // Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR |
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14 | // INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING |
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15 | // PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY |
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16 | // PROVIDING THIS DESIGN, CODE, OR INFORMATION AS |
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17 | // ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, |
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18 | // APPLICATION OR STANDARD, XILINX IS MAKING NO |
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19 | // REPRESENTATION THAT THIS IMPLEMENTATION IS FREE |
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20 | // FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE |
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21 | // RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY |
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22 | // REQUIRE FOR YOUR IMPLEMENTATION. XILINX |
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23 | // EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH |
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24 | // RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, |
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25 | // INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR |
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26 | // REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE |
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27 | // FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES |
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28 | // OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
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29 | // PURPOSE. |
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30 | // |
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31 | // (c) Copyright 2004 Xilinx, Inc. |
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32 | // All rights reserved. |
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33 | // |
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34 | |
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35 | `timescale 1 ns / 1 ps |
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36 | |
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37 | module null_pair_example |
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38 | ( |
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39 | clk, |
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40 | rx1n, |
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41 | rx1p, |
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42 | tx1n, |
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43 | tx1p |
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44 | ); |
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45 | |
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46 | input clk; |
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47 | input [1:0] rx1n; |
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48 | input [1:0] rx1p; |
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49 | output [1:0] tx1n; |
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50 | output [1:0] tx1p; |
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51 | |
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52 | //----------------------------------------------------------------- |
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53 | // |
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54 | // NULL_PAIR wire declarations |
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55 | // |
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56 | //----------------------------------------------------------------- |
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57 | wire clk; |
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58 | wire [1:0] rx1n; |
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59 | wire [1:0] rx1p; |
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60 | wire [1:0] tx1n; |
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61 | wire [1:0] tx1p; |
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62 | wire global_sig; |
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63 | |
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64 | |
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65 | //----------------------------------------------------------------- |
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66 | // |
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67 | // NULL_PAIR core instance |
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68 | // |
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69 | //----------------------------------------------------------------- |
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70 | NULL_PAIR null_pair_inst |
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71 | ( |
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72 | .GREFCLK_IN (global_sig), |
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73 | .RX1N_IN (rx1n), |
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74 | .RX1P_IN (rx1p), |
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75 | .TX1N_OUT (tx1n), |
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76 | .TX1P_OUT (tx1p) |
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77 | ); |
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78 | |
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79 | |
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80 | //----------------------------------------------------------------- |
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81 | // |
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82 | // GREFCLK_IN port needs to be driven with any global signal |
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83 | // (any BUFG output, even a BUFG with ground for input will work). |
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84 | // |
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85 | //----------------------------------------------------------------- |
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86 | BUFG global_sig_i |
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87 | ( |
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88 | .I (clk), |
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89 | .O (global_sig) |
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90 | ); |
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91 | |
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92 | endmodule |
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93 | |
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94 | |
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95 | //------------------------------------------------------------------- |
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96 | // |
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97 | // NULL_PAIR core module declaration |
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98 | // |
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99 | //------------------------------------------------------------------- |
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100 | module NULL_PAIR( |
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101 | GREFCLK_IN, |
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102 | RX1N_IN, |
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103 | RX1P_IN, |
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104 | TX1N_OUT, |
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105 | TX1P_OUT); |
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106 | |
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107 | |
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108 | input GREFCLK_IN; |
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109 | input [1:0] RX1N_IN; |
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110 | input [1:0] RX1P_IN; |
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111 | output [1:0] TX1N_OUT; |
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112 | output [1:0] TX1P_OUT; |
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113 | |
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114 | endmodule |
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115 | |
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