1 | ## Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. |
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2 | |
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3 | ## You may copy and modify these files for your own internal use solely with |
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4 | ## Xilinx programmable logic devices and Xilinx EDK system or create IP |
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5 | ## modules solely for Xilinx programmable logic devices and Xilinx EDK system. |
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6 | ## No rights are granted to distribute any files unless they are distributed in |
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7 | ## Xilinx programmable logic devices. |
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8 | ################################################################### |
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9 | ## |
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10 | ## Name : ofdm_TxRx_mimo_opbw |
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11 | ## Desc : Microprocessor Peripheral Description |
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12 | ## : Automatically generated by PsfUtility |
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13 | ## |
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14 | ################################################################### |
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15 | |
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16 | BEGIN ofdm_AGC_mimo_opbw |
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17 | |
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18 | ## Peripheral Options |
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19 | OPTION IPTYPE = PERIPHERAL |
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20 | OPTION STYLE = BLACKBOX |
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21 | OPTION IMP_NETLIST = FALSE |
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22 | #OPTION HDL = VHDL |
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23 | |
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24 | |
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25 | ## Bus Interfaces |
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26 | BUS_INTERFACE BUS = SOPB, BUS_TYPE = SLAVE, BUS_STD = OPB |
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27 | |
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28 | ## Generics for VHDL or Parameters for Verilog |
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29 | PARAMETER C_BASEADDR = 0xFFFFFFFF, DT = std_logic_vector(0 to 31), BUS = SOPB, ADDRESS = BASE, PAIR = C_HIGHADDR, MIN_SIZE = 0x10000 |
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30 | PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector(0 to 31), BUS = SOPB, ADDRESS = HIGH, PAIR = C_BASEADDR |
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31 | PARAMETER C_OPB_AWIDTH = 32, DT = INTEGER, BUS = SOPB |
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32 | PARAMETER C_OPB_DWIDTH = 32, DT = INTEGER, BUS = SOPB |
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33 | |
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34 | ## Ports |
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35 | PORT ce = "net_vcc", DIR = I |
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36 | PORT i_in_a = "", DIR = I, VEC = [0:13] |
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37 | PORT i_in_b = "", DIR = I, VEC = [0:13] |
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38 | PORT opb_abus = OPB_ABus, DIR = I, VEC = [0:31], BUS = SOPB |
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39 | PORT opb_be = OPB_BE, DIR = I, VEC = [0:3], BUS = SOPB |
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40 | PORT opb_clk = "", DIR = I, BUS = SOPB |
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41 | PORT opb_dbus = OPB_DBus, DIR = I, VEC = [0:31], BUS = SOPB |
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42 | PORT opb_rnw = OPB_RNW, DIR = I, BUS = SOPB |
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43 | PORT opb_rst = OPB_Rst, DIR = I, BUS = SOPB |
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44 | PORT opb_select = OPB_select, DIR = I, BUS = SOPB |
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45 | PORT opb_seqaddr = OPB_seqAddr, DIR = I, BUS = SOPB |
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46 | PORT packet_in = "", DIR = I |
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47 | PORT q_in_a = "", DIR = I, VEC = [0:13] |
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48 | PORT q_in_b = "", DIR = I, VEC = [0:13] |
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49 | PORT reset_in = "", DIR = I |
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50 | PORT rssi_in_a = "", DIR = I, VEC = [0:9] |
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51 | PORT rssi_in_b = "", DIR = I, VEC = [0:9] |
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52 | PORT done_a = "", DIR = O |
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53 | PORT done_b = "", DIR = O |
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54 | PORT g_bb_a = "", DIR = O, VEC = [0:4] |
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55 | PORT g_bb_b = "", DIR = O, VEC = [0:4] |
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56 | PORT g_rf_a = "", DIR = O, VEC = [0:1] |
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57 | PORT g_rf_b = "", DIR = O, VEC = [0:1] |
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58 | PORT i_out_a = "", DIR = O, VEC = [0:13] |
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59 | PORT i_out_b = "", DIR = O, VEC = [0:13] |
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60 | PORT q_out_a = "", DIR = O, VEC = [0:13] |
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61 | PORT q_out_b = "", DIR = O, VEC = [0:13] |
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62 | PORT rxhp_a = "", DIR = O |
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63 | PORT rxhp_b = "", DIR = O |
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64 | PORT sgp_dbus = Sl_DBus, DIR = O, VEC = [0:31], BUS = SOPB |
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65 | PORT sgp_errack = Sl_errAck, DIR = O, BUS = SOPB |
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66 | PORT sgp_retry = Sl_retry, DIR = O, BUS = SOPB |
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67 | PORT sgp_toutsup = Sl_toutSup, DIR = O, BUS = SOPB |
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68 | PORT sgp_xferack = Sl_xferAck, DIR = O, BUS = SOPB |
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69 | |
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70 | END |
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