1 | ## Copyright (c) 2004 Xilinx, Inc. All Rights Reserved.
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2 | ## You may copy and modify these files for your own internal use solely with
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3 | ## Xilinx programmable logic devices and Xilinx EDK system or create IP
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4 | ## modules solely for Xilinx programmable logic devices and Xilinx EDK system.
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5 | ## No rights are granted to distribute any files unless they are distributed in
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6 | ## Xilinx programmable logic devices.
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7 | ###################################################################
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8 | ##
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9 | ## Name : radio_bridge
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10 | ## Desc : Microprocessor Peripheral Description
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11 | ## : Automatically generated by PsfUtility
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12 | ##
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13 | ###################################################################
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14 |
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15 | BEGIN radio_bridge
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16 |
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17 | ## Peripheral Options
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18 | OPTION IPTYPE = PERIPHERAL
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19 | OPTION IMP_NETLIST = TRUE
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20 | OPTION HDL = VERILOG
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21 | OPTION CORE_STATE = ACTIVE
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22 | OPTION IP_GROUP = USER
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23 | OPTION USAGE_LEVEL = BASE_USER
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24 |
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25 | IO_INTERFACE IO_IF = radio_bridge, IO_TYPE = WARP_RADIOBRIDGE_V1
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26 |
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27 | ## Bus Interfaces
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28 |
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29 | ## Generics for VHDL or Parameters for Verilog
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30 |
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31 | ## Ports
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32 | PORT converter_clock_in = "sys_clk_s", DIR = I
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33 | PORT converter_clock_out = "", DIR = O
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34 |
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35 | PORT user_ADC_I = "", DIR = O, VEC = [0:13], IO_IS = userADCI
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36 | PORT user_ADC_Q = "", DIR = O, VEC = [0:13], IO_IS = userADCQ
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37 |
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38 | PORT radio_DAC_I = "", DIR = O, VEC = [0:15], IO_IS = radioDACI
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39 | PORT radio_DAC_Q = "", DIR = O, VEC = [0:15], IO_IS = radioDACQ
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40 |
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41 | PORT user_DAC_I = "", DIR = I, VEC = [0:15], IO_IS = userDACI
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42 | PORT user_DAC_Q = "", DIR = I, VEC = [0:15], IO_IS = userDACQ
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43 |
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44 | PORT radio_ADC_I = "", DIR = I, VEC = [0:13], IO_IS = radioADCI
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45 | PORT radio_ADC_Q = "", DIR = I, VEC = [0:13], IO_IS = radioADCQ
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46 |
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47 |
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48 | PORT user_RF_gain = "", DIR = I, VEC = [0:1], IO_IS = userRFG
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49 | PORT user_BB_gain = "", DIR = I, VEC = [0:4], IO_IS = userBBG
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50 | PORT radio_RF_gain = "", DIR = O, VEC = [0:1], IO_IS = radioRFG
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51 | PORT radio_BB_gain = "", DIR = O, VEC = [0:4], IO_IS = radioBBG
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52 |
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53 | PORT controller_spi_clk = "", DIR = I
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54 | PORT controller_spi_data = "", DIR = I
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55 | PORT controller_radio_cs = "", DIR = I
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56 | PORT controller_dac_cs = "", DIR = I
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57 | PORT controller_SHDN = "", DIR = I
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58 | PORT controller_TxEn = "", DIR = I
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59 | PORT controller_RxEn = "", DIR = I
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60 | PORT controller_RxHP = "", DIR = I
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61 | PORT controller_24PA = "", DIR = I
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62 | PORT controller_5PA = "", DIR = I
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63 | PORT controller_ANTSW = "", DIR = I, VEC = [0:1], IO_IS = c2b_ANTSW
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64 | PORT controller_LED = "", DIR = I, VEC = [0:2], IO_IS = c2b_LED
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65 | PORT controller_RX_ADC_DCS = "", DIR = I
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66 | PORT controller_RX_ADC_DFS = "", DIR = I
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67 | PORT controller_RX_ADC_PWDNA = "", DIR = I
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68 | PORT controller_RX_ADC_PWDNB = "", DIR = I
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69 | PORT controller_RSSI_ADC_CLAMP = "", DIR = I
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70 | PORT controller_RSSI_ADC_HIZ = "", DIR = I
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71 | PORT controller_RSSI_ADC_SLEEP = "", DIR = I
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72 | PORT controller_DIPSW = "", DIR = O, VEC = [0:3], IO_IS = c2b_DIPSW
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73 | PORT controller_RSSI_ADC_D = "", DIR = O, VEC = [0:9], IO_IS = c2b_RSSI_ADC_D
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74 | PORT controller_LD = "", DIR = O
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75 | PORT controller_RX_ADC_OTRA = "", DIR = O
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76 | PORT controller_RX_ADC_OTRB = "", DIR = O
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77 | PORT controller_RSSI_ADC_OTR = "", DIR = O
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78 | PORT controller_DAC_PLL_LOCK = "", DIR = O
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79 | PORT controller_DAC_RESET = "", DIR = I
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80 | PORT dac_spi_data = "", DIR = O
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81 | PORT dac_spi_cs = "", DIR = O
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82 | PORT dac_spi_clk = "", DIR = O
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83 | PORT radio_spi_clk = "", DIR = O
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84 | PORT radio_spi_data = "", DIR = O
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85 | PORT radio_spi_cs = "", DIR = O
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86 | PORT radio_SHDN = "", DIR = O
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87 | PORT radio_TxEn = "", DIR = O
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88 | PORT radio_RxEn = "", DIR = O
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89 | PORT radio_RxHP = "", DIR = O
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90 | PORT radio_24PA = "", DIR = O
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91 | PORT radio_5PA = "", DIR = O
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92 | PORT radio_ANTSW = "", DIR = O, VEC = [0:1], IO_IS = b2r_ANTSW
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93 | PORT radio_LED = "", DIR = O, VEC = [0:2], IO_IS = b2r_LED
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94 | PORT radio_RX_ADC_DCS = "", DIR = O
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95 | PORT radio_RX_ADC_DFS = "", DIR = O
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96 | PORT radio_RX_ADC_PWDNA = "", DIR = O
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97 | PORT radio_RX_ADC_PWDNB = "", DIR = O
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98 | PORT radio_DIPSW = "", DIR = O, VEC = [0:3], IO_IS = b2r_DIPSW
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99 | PORT radio_RSSI_ADC_CLAMP = "", DIR = O
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100 | PORT radio_RSSI_ADC_HIZ = "", DIR = O
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101 | PORT radio_RSSI_ADC_SLEEP = "", DIR = O
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102 | PORT radio_RSSI_ADC_D = "", DIR = I, VEC = [0:9], IO_IS = b2r_RSSI_ADC_D
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103 | PORT radio_LD = "", DIR = I
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104 | PORT radio_RX_ADC_OTRA = "", DIR = I
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105 | PORT radio_RX_ADC_OTRB = "", DIR = I
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106 | PORT radio_RSSI_ADC_OTR = "", DIR = I
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107 | PORT radio_DAC_PLL_LOCK = "", DIR = I
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108 | PORT radio_DAC_RESET = "", DIR = O
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109 |
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110 | END
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