1 | ////////////////////////////////////////////////////////// |
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2 | // Copyright (c) 2006 Rice University // |
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3 | // All Rights Reserved // |
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4 | // This code is covered by the Rice-WARP license // |
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5 | // See http://warp.rice.edu/license/ for details // |
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6 | ////////////////////////////////////////////////////////// |
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7 | |
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8 | module radio_bridge |
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9 | ( |
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10 | converter_clock_in, |
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11 | converter_clock_out, |
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12 | |
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13 | user_RSSI_ADC_clk, |
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14 | radio_RSSI_ADC_clk, |
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15 | |
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16 | user_RSSI_ADC_D, |
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17 | |
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18 | user_EEPROM_IO_T, |
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19 | user_EEPROM_IO_O, |
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20 | user_EEPROM_IO_I, |
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21 | |
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22 | radio_EEPROM_IO, |
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23 | |
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24 | radio_DAC_I, |
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25 | radio_DAC_Q, |
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26 | |
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27 | radio_ADC_I, |
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28 | radio_ADC_Q, |
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29 | |
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30 | user_DAC_I, |
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31 | user_DAC_Q, |
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32 | |
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33 | user_ADC_I, |
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34 | user_ADC_Q, |
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35 | |
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36 | user_RF_gain, |
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37 | user_BB_gain, |
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38 | |
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39 | radio_RF_gain, |
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40 | radio_BB_gain, |
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41 | |
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42 | controller_spi_clk, |
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43 | controller_spi_data, |
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44 | controller_radio_cs, |
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45 | controller_dac_cs, |
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46 | controller_SHDN, |
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47 | controller_TxEn, |
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48 | controller_RxEn, |
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49 | controller_RxHP, |
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50 | controller_24PA, |
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51 | controller_5PA, |
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52 | controller_ANTSW, |
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53 | controller_LED, |
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54 | controller_RX_ADC_DCS, |
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55 | controller_RX_ADC_DFS, |
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56 | controller_RX_ADC_PWDNA, |
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57 | controller_RX_ADC_PWDNB, |
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58 | controller_DIPSW, |
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59 | controller_RSSI_ADC_CLAMP, |
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60 | controller_RSSI_ADC_HIZ, |
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61 | controller_RSSI_ADC_SLEEP, |
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62 | controller_RSSI_ADC_D, |
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63 | |
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64 | controller_LD, |
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65 | controller_RX_ADC_OTRA, |
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66 | controller_RX_ADC_OTRB, |
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67 | controller_RSSI_ADC_OTR, |
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68 | controller_DAC_PLL_LOCK, |
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69 | controller_DAC_RESET, |
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70 | |
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71 | dac_spi_data, |
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72 | dac_spi_cs, |
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73 | dac_spi_clk, |
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74 | |
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75 | radio_spi_clk, |
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76 | radio_spi_data, |
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77 | radio_spi_cs, |
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78 | |
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79 | radio_SHDN, |
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80 | radio_TxEn, |
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81 | radio_RxEn, |
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82 | radio_RxHP, |
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83 | radio_24PA, |
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84 | radio_5PA, |
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85 | radio_ANTSW, |
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86 | radio_LED, |
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87 | radio_RX_ADC_DCS, |
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88 | radio_RX_ADC_DFS, |
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89 | radio_RX_ADC_PWDNA, |
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90 | radio_RX_ADC_PWDNB, |
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91 | radio_DIPSW, |
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92 | radio_RSSI_ADC_CLAMP, |
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93 | radio_RSSI_ADC_HIZ, |
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94 | radio_RSSI_ADC_SLEEP, |
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95 | radio_RSSI_ADC_D, |
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96 | |
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97 | radio_LD, |
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98 | radio_RX_ADC_OTRA, |
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99 | radio_RX_ADC_OTRB, |
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100 | radio_RSSI_ADC_OTR, |
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101 | radio_DAC_PLL_LOCK, |
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102 | radio_DAC_RESET |
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103 | ); |
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104 | |
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105 | /**********************/ |
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106 | /* Clock & Data Ports */ |
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107 | /**********************/ |
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108 | input converter_clock_in; |
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109 | output converter_clock_out; |
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110 | |
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111 | input user_RSSI_ADC_clk; |
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112 | output radio_RSSI_ADC_clk; |
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113 | output [0:9] user_RSSI_ADC_D; |
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114 | |
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115 | input user_EEPROM_IO_T; |
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116 | input user_EEPROM_IO_O; |
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117 | output user_EEPROM_IO_I; |
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118 | |
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119 | output [0:15] radio_DAC_I; |
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120 | output [0:15] radio_DAC_Q; |
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121 | |
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122 | input [0:13] radio_ADC_I; |
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123 | input [0:13] radio_ADC_Q; |
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124 | |
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125 | input [0:15] user_DAC_I; |
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126 | input [0:15] user_DAC_Q; |
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127 | |
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128 | output [0:13] user_ADC_I; |
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129 | output [0:13] user_ADC_Q; |
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130 | |
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131 | input [0:1] user_RF_gain; |
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132 | input [0:4] user_BB_gain; |
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133 | |
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134 | output [0:1] radio_RF_gain; |
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135 | output [0:4] radio_BB_gain; |
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136 | |
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137 | /*******************************************/ |
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138 | /* Radio Controller <-> Radio Bridge Ports */ |
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139 | /*******************************************/ |
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140 | input controller_spi_clk; |
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141 | input controller_spi_data; |
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142 | input controller_radio_cs; |
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143 | input controller_dac_cs; |
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144 | |
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145 | input controller_SHDN; |
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146 | input controller_TxEn; |
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147 | input controller_RxEn; |
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148 | input controller_RxHP; |
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149 | input controller_24PA; |
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150 | input controller_5PA; |
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151 | input [0:1] controller_ANTSW; |
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152 | input [0:2] controller_LED; |
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153 | input controller_RX_ADC_DCS; |
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154 | input controller_RX_ADC_DFS; |
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155 | input controller_RX_ADC_PWDNA; |
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156 | input controller_RX_ADC_PWDNB; |
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157 | input controller_RSSI_ADC_CLAMP; |
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158 | input controller_RSSI_ADC_HIZ; |
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159 | input controller_RSSI_ADC_SLEEP; |
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160 | input controller_DAC_RESET; |
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161 | |
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162 | output [0:3] controller_DIPSW; |
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163 | output [0:9] controller_RSSI_ADC_D; |
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164 | output controller_LD; |
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165 | output controller_RX_ADC_OTRA; |
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166 | output controller_RX_ADC_OTRB; |
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167 | output controller_RSSI_ADC_OTR; |
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168 | output controller_DAC_PLL_LOCK; |
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169 | |
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170 | /**************************************/ |
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171 | /* Radio Bridge <-> Radio Board Ports */ |
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172 | /**************************************/ |
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173 | output dac_spi_data; |
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174 | output dac_spi_cs; |
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175 | output dac_spi_clk; |
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176 | |
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177 | output radio_spi_clk; |
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178 | output radio_spi_data; |
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179 | output radio_spi_cs; |
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180 | |
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181 | output radio_SHDN; |
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182 | output radio_TxEn; |
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183 | output radio_RxEn; |
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184 | output radio_RxHP; |
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185 | output radio_24PA; |
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186 | output radio_5PA; |
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187 | output [0:1] radio_ANTSW; |
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188 | output [0:2] radio_LED; |
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189 | output radio_RX_ADC_DCS; |
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190 | output radio_RX_ADC_DFS; |
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191 | output radio_RX_ADC_PWDNA; |
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192 | output radio_RX_ADC_PWDNB; |
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193 | output [0:3] radio_DIPSW; |
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194 | output radio_RSSI_ADC_CLAMP; |
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195 | output radio_RSSI_ADC_HIZ; |
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196 | output radio_RSSI_ADC_SLEEP; |
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197 | output radio_DAC_RESET; |
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198 | |
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199 | input [0:9] radio_RSSI_ADC_D; |
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200 | input radio_LD; |
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201 | input radio_RX_ADC_OTRA; |
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202 | input radio_RX_ADC_OTRB; |
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203 | input radio_RSSI_ADC_OTR; |
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204 | input radio_DAC_PLL_LOCK; |
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205 | |
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206 | inout radio_EEPROM_IO; |
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207 | |
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208 | /**********************************/ |
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209 | /* Clocks and analog data signals */ |
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210 | /**********************************/ |
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211 | assign converter_clock_out = converter_clock_in; |
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212 | |
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213 | assign radio_RSSI_ADC_clk = user_RSSI_ADC_clk; |
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214 | |
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215 | assign user_ADC_I = radio_ADC_I; |
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216 | assign user_ADC_Q = radio_ADC_Q; |
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217 | |
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218 | assign radio_DAC_I = user_DAC_I; |
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219 | assign radio_DAC_Q = user_DAC_Q; |
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220 | |
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221 | assign radio_RF_gain = user_RF_gain; |
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222 | assign radio_BB_gain = user_BB_gain; |
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223 | |
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224 | /********************************************/ |
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225 | /* Instantiate the IOBUF for EEPROM Devices */ |
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226 | /********************************************/ |
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227 | |
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228 | IOBUF xIOBUF( |
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229 | .T(user_EEPROM_IO_T), |
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230 | .I(user_EEPROM_IO_O), |
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231 | .O(user_EEPROM_IO_I), |
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232 | .IO(radio_EEPROM_IO) |
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233 | ); |
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234 | |
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235 | /*******************************************/ |
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236 | /* Radio Controller -> Radio Board Drivers */ |
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237 | /*******************************************/ |
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238 | assign dac_spi_clk = controller_spi_clk; |
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239 | assign dac_spi_data = controller_spi_data; |
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240 | assign dac_spi_cs = controller_dac_cs; |
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241 | |
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242 | assign radio_spi_clk = controller_spi_clk; |
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243 | assign radio_spi_data = controller_spi_data; |
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244 | assign radio_spi_cs = controller_radio_cs; |
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245 | |
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246 | assign radio_SHDN = controller_SHDN; |
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247 | assign radio_TxEn = controller_TxEn; |
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248 | assign radio_RxEn = controller_RxEn; |
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249 | assign radio_RxHP = controller_RxHP; |
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250 | assign radio_24PA = controller_24PA; |
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251 | assign radio_5PA = controller_5PA; |
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252 | assign radio_ANTSW = controller_ANTSW; |
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253 | assign radio_LED = controller_LED; |
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254 | assign radio_RX_ADC_DCS = controller_RX_ADC_DCS; |
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255 | assign radio_RX_ADC_DFS = controller_RX_ADC_DFS; |
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256 | assign radio_RX_ADC_PWDNA = controller_RX_ADC_PWDNA; |
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257 | assign radio_RX_ADC_PWDNB = controller_RX_ADC_PWDNB; |
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258 | assign radio_RSSI_ADC_CLAMP = controller_RSSI_ADC_CLAMP; |
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259 | assign radio_RSSI_ADC_HIZ = controller_RSSI_ADC_HIZ; |
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260 | assign radio_RSSI_ADC_SLEEP = controller_RSSI_ADC_SLEEP; |
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261 | |
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262 | /*******************************************/ |
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263 | /* Radio Board -> Radio Controller Drivers */ |
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264 | /*******************************************/ |
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265 | |
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266 | assign controller_DIPSW = radio_DIPSW; |
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267 | assign controller_RSSI_ADC_D = radio_RSSI_ADC_D; |
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268 | assign user_RSSI_ADC_D = radio_RSSI_ADC_D; |
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269 | assign controller_LD = radio_LD; |
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270 | assign controller_RX_ADC_OTRA = radio_RX_ADC_OTRA; |
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271 | assign controller_RX_ADC_OTRB = radio_RX_ADC_OTRB; |
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272 | assign controller_RSSI_ADC_OTR = radio_RSSI_ADC_OTR; |
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273 | assign controller_DAC_PLL_LOCK = radio_DAC_PLL_LOCK; |
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274 | assign radio_DAC_RESET = controller_DAC_RESET; |
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275 | |
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276 | endmodule |
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