1 | ###################################################################
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2 | # Copyright (c) 2006 Rice University
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3 | # All Rights Reserved
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4 | # This code is covered by the Rice-WARP license
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5 | # See http://warp.rice.edu/license/ for details
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6 | ###################################################################
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7 |
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8 | BEGIN radio_bridge
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9 |
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10 | ## Peripheral Options
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11 | OPTION IPTYPE = IP
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12 | OPTION IMP_NETLIST = TRUE
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13 | OPTION HDL = VERILOG
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14 | OPTION CORE_STATE = ACTIVE
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15 | OPTION IP_GROUP = USER
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16 | OPTION USAGE_LEVEL = BASE_USER
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17 |
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18 | IO_INTERFACE IO_IF = radio_bridge, IO_TYPE = WARP_RADIOBRIDGE_V1
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19 |
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20 | ## Ports
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21 | ####################################################################################
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22 | ## User Ports
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23 | ## The user must connect sources/sinks to these ports in XPS in order to use
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24 | ## the radio board. The rest of the board's connections are made automatically
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25 | ####################################################################################
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26 | PORT user_ADC_I = "", DIR = O, VEC = [0:13], IO_IS = userADCI
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27 | PORT user_ADC_Q = "", DIR = O, VEC = [0:13], IO_IS = userADCQ
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28 |
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29 | PORT user_DAC_I = "", DIR = I, VEC = [0:15], IO_IS = userDACI
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30 | PORT user_DAC_Q = "", DIR = I, VEC = [0:15], IO_IS = userDACQ
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31 |
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32 | PORT user_RxRF_gain = "", DIR = I, VEC = [0:1], IO_IS = userRxRFG
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33 | PORT user_RxBB_gain = "", DIR = I, VEC = [0:4], IO_IS = userRxBBG
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34 |
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35 | PORT user_Tx_gain = "", DIR = I, VEC = [0:5], IO_IS = userTxG
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36 |
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37 | PORT user_RSSI_ADC_clk = "", DIR = I
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38 |
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39 | PORT user_RSSI_ADC_D = "", DIR = O, VEC = [0:9], IO_IS = userRSSI_D
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40 |
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41 | PORT user_EEPROM_IO_T = "", DIR = I
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42 | PORT user_EEPROM_IO_O = "", DIR = I
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43 | PORT user_EEPROM_IO_I = "", DIR = O
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44 | ####################################################################################
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45 |
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46 | #Automatically tied to sys_clk_s, the OPB clock created by BSB
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47 | # Custom clock setups may need to change this
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48 | # Show defaults in System Assembly to view and change this assignment
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49 | PORT converter_clock_in = "sys_clk_s", DIR = I, SIGIS = CLK
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50 |
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51 | PORT converter_clock_out = "", DIR = O, SIGIS = CLK
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52 |
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53 | PORT radio_RSSI_ADC_clk = "", DIR = O
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54 |
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55 | PORT radio_DAC_I = "", DIR = O, VEC = [15:0], IO_IS = radioDACI, ENDIAN = LITTLE
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56 | PORT radio_DAC_Q = "", DIR = O, VEC = [15:0], IO_IS = radioDACQ, ENDIAN = LITTLE
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57 |
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58 | PORT radio_ADC_I = "", DIR = I, VEC = [13:0], IO_IS = radioADCI, ENDIAN = LITTLE
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59 | PORT radio_ADC_Q = "", DIR = I, VEC = [13:0], IO_IS = radioADCQ, ENDIAN = LITTLE
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60 |
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61 | PORT radio_B = "", DIR = O, VEC = [6:0], IO_IS = radioGain, ENDIAN = LITTLE
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62 |
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63 | PORT radio_ANTSW = "", DIR = O, VEC = [1:0], IO_IS = b2r_ANTSW, ENDIAN = LITTLE
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64 | PORT radio_LED = "", DIR = O, VEC = [2:0], IO_IS = b2r_LED, ENDIAN = LITTLE
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65 | PORT radio_DIPSW = "", DIR = O, VEC = [3:0], IO_IS = b2r_DIPSW, ENDIAN = LITTLE
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66 | PORT radio_RSSI_ADC_D = "", DIR = I, VEC = [9:0], IO_IS = b2r_RSSI_ADC_D, ENDIAN = LITTLE
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67 |
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68 | PORT radio_EEPROM_IO = "", DIR = IO, THREE_STATE = FALSE, IOB_STATE = BUF
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69 |
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70 | PORT radio_spi_clk = "", DIR = O
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71 | PORT radio_spi_data = "", DIR = O
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72 | PORT radio_spi_cs = "", DIR = O
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73 | PORT radio_SHDN = "", DIR = O
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74 | PORT radio_TxEn = "", DIR = O
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75 | PORT radio_RxEn = "", DIR = O
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76 | PORT radio_RxHP = "", DIR = O
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77 | PORT radio_24PA = "", DIR = O
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78 | PORT radio_5PA = "", DIR = O
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79 | PORT radio_RX_ADC_DCS = "", DIR = O
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80 | PORT radio_RX_ADC_DFS = "", DIR = O
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81 | PORT radio_RX_ADC_PWDNA = "", DIR = O
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82 | PORT radio_RX_ADC_PWDNB = "", DIR = O
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83 | PORT radio_RSSI_ADC_CLAMP = "", DIR = O
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84 | PORT radio_RSSI_ADC_HIZ = "", DIR = O
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85 | PORT radio_RSSI_ADC_SLEEP = "", DIR = O
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86 | PORT radio_LD = "", DIR = I
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87 | PORT radio_RX_ADC_OTRA = "", DIR = I
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88 | PORT radio_RX_ADC_OTRB = "", DIR = I
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89 | PORT radio_RSSI_ADC_OTR = "", DIR = I
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90 | PORT radio_DAC_PLL_LOCK = "", DIR = I
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91 | PORT radio_DAC_RESET = "", DIR = O
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92 |
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93 | PORT controller_spi_clk = "", DIR = I
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94 | PORT controller_spi_data = "", DIR = I
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95 | PORT controller_radio_cs = "", DIR = I
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96 | PORT controller_dac_cs = "", DIR = I
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97 | PORT controller_SHDN = "", DIR = I
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98 | PORT controller_TxEn = "", DIR = I
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99 | PORT controller_RxEn = "", DIR = I
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100 | PORT controller_RxHP = "", DIR = I
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101 | PORT controller_24PA = "", DIR = I
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102 | PORT controller_5PA = "", DIR = I
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103 | PORT controller_ANTSW = "", DIR = I, VEC = [0:1], IO_IS = c2b_ANTSW
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104 | PORT controller_LED = "", DIR = I, VEC = [0:2], IO_IS = c2b_LED
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105 | PORT controller_RX_ADC_DCS = "", DIR = I
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106 | PORT controller_RX_ADC_DFS = "", DIR = I
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107 | PORT controller_RX_ADC_PWDNA = "", DIR = I
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108 | PORT controller_RX_ADC_PWDNB = "", DIR = I
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109 | PORT controller_RSSI_ADC_CLAMP = "", DIR = I
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110 | PORT controller_RSSI_ADC_HIZ = "", DIR = I
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111 | PORT controller_RSSI_ADC_SLEEP = "", DIR = I
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112 | PORT controller_DIPSW = "", DIR = O, VEC = [0:3], IO_IS = c2b_DIPSW
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113 | PORT controller_RSSI_ADC_D = "", DIR = O, VEC = [0:9], IO_IS = c2b_RSSI_ADC_D
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114 | PORT controller_LD = "", DIR = O
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115 | PORT controller_RX_ADC_OTRA = "", DIR = O
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116 | PORT controller_RX_ADC_OTRB = "", DIR = O
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117 | PORT controller_RSSI_ADC_OTR = "", DIR = O
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118 | PORT controller_DAC_PLL_LOCK = "", DIR = O
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119 | PORT controller_DAC_RESET = "", DIR = I
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120 | PORT dac_spi_data = "", DIR = O
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121 | PORT dac_spi_cs = "", DIR = O
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122 | PORT dac_spi_clk = "", DIR = O
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123 |
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124 | END
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