source: PlatformSupport/Deprecated/pcores/radio_controller_v1_00_a/data/radio_controller_v2_1_0.mpd

Last change on this file was 32, checked in by snovich, 19 years ago

First radio controller that works. Does not control the amplifiers and the antenna switches

File size: 2.6 KB
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1## Copyright (c) 2004 Xilinx, Inc. All Rights Reserved.
2## You may copy and modify these files for your own internal use solely with
3## Xilinx programmable logic devices and  Xilinx EDK system or create IP
4## modules solely for Xilinx programmable logic devices and Xilinx EDK system.
5## No rights are granted to distribute any files unless they are distributed in
6## Xilinx programmable logic devices.
7###################################################################
8##
9## Name     : radio_controller
10## Desc     : Microprocessor Peripheral Description
11##          : Automatically generated by PsfUtility
12##
13###################################################################
14
15BEGIN radio_controller
16
17## Peripheral Options
18OPTION IPTYPE = PERIPHERAL
19OPTION IMP_NETLIST = TRUE
20OPTION HDL = MIXED
21OPTION IP_GROUP = MICROBLAZE:PPC:USER
22OPTION CORE_STATE = DEVELOPMENT
23
24
25## Bus Interfaces
26BUS_INTERFACE BUS = SOPB, BUS_TYPE = SLAVE, BUS_STD = OPB
27
28## Generics for VHDL or Parameters for Verilog
29PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x100, BUS = SOPB, ADDRESS = BASE, PAIR = C_HIGHADDR
30PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, BUS = SOPB, ADDRESS = HIGH, PAIR = C_BASEADDR
31PARAMETER C_OPB_AWIDTH = 32, DT = INTEGER, BUS = SOPB
32PARAMETER C_OPB_DWIDTH = 32, DT = INTEGER, BUS = SOPB
33PARAMETER C_FAMILY = virtex2p, DT = STRING
34
35## Ports
36PORT OPB_Clk = "", DIR = I, SIGIS = Clk, BUS = SOPB
37PORT OPB_Rst = OPB_Rst, DIR = I, SIGIS = Rst, BUS = SOPB
38PORT Sl_DBus = Sl_DBus, DIR = O, VEC = [0:(C_OPB_DWIDTH-1)], BUS = SOPB
39PORT Sl_errAck = Sl_errAck, DIR = O, BUS = SOPB
40PORT Sl_retry = Sl_retry, DIR = O, BUS = SOPB
41PORT Sl_toutSup = Sl_toutSup, DIR = O, BUS = SOPB
42PORT Sl_xferAck = Sl_xferAck, DIR = O, BUS = SOPB
43PORT OPB_ABus = OPB_ABus, DIR = I, VEC = [0:(C_OPB_AWIDTH-1)], BUS = SOPB
44PORT OPB_BE = OPB_BE, DIR = I, VEC = [0:((C_OPB_DWIDTH/8)-1)], BUS = SOPB
45PORT OPB_DBus = OPB_DBus, DIR = I, VEC = [0:(C_OPB_DWIDTH-1)], BUS = SOPB
46PORT OPB_RNW = OPB_RNW, DIR = I, BUS = SOPB
47PORT OPB_select = OPB_select, DIR = I, BUS = SOPB
48PORT OPB_seqAddr = OPB_seqAddr, DIR = I, BUS = SOPB
49PORT radio1shdn = "", DIR = O
50PORT radio2shdn = "", DIR = O
51PORT radio3shdn = "", DIR = O
52PORT radio4shdn = "", DIR = O
53PORT radio1txen = "", DIR = O
54PORT radio2txen = "", DIR = O
55PORT radio3txen = "", DIR = O
56PORT radio4txen = "", DIR = O
57PORT radio1rxen = "", DIR = O
58PORT radio2rxen = "", DIR = O
59PORT radio3rxen = "", DIR = O
60PORT radio4rxen = "", DIR = O
61PORT radio1ld = "", DIR = I
62PORT radio2ld = "", DIR = I
63PORT radio3ld = "", DIR = I
64PORT radio4ld = "", DIR = I
65
66
67END
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