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source: PlatformSupport/Deprecated/pcores/radio_controller_v1_00_a/hdl/vhdl/radio_controller.vhd

Last change on this file was 32, checked in by snovich, 19 years ago
First radio controller that works. Does not control the amplifiers and the antenna switches
File size: 23.5 KB

Line
1	------------------------------------------------------------------------------
2	-- radio_controller.vhd - entity/architecture pair
3	------------------------------------------------------------------------------
4	-- IMPORTANT:
5	-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
6	--
7	-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
8	--
9	-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
10	-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
11	-- OF THE USER_LOGIC ENTITY.
12	------------------------------------------------------------------------------
13	--
14	-- ***************************************************************************
15	-- Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
16	--
17	-- Xilinx, Inc.
18	-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
19	-- AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
20	-- SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
21	-- OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
22	-- APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
23	-- THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
24	-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
25	-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
26	-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
27	-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
28	-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
29	-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
30	-- FOR A PARTICULAR PURPOSE.
31	--
32	-- YOU MAY COPY AND MODIFY THESE FILES FOR YOUR OWN INTERNAL USE SOLELY
33	-- WITH XILINX PROGRAMMABLE LOGIC DEVICES AND XILINX EDK SYSTEM OR
34	-- CREATE IP MODULES SOLELY FOR XILINX PROGRAMMABLE LOGIC DEVICES AND
35	-- XILINX EDK SYSTEM. NO RIGHTS ARE GRANTED TO DISTRIBUTE ANY FILES
36	-- UNLESS THEY ARE DISTRIBUTED IN XILINX PROGRAMMABLE LOGIC DEVICES.
37	--
38	-- ***************************************************************************
39	--
40	------------------------------------------------------------------------------
41	-- Filename: radio_controller.vhd
42	-- Version: 1.00.a
43	-- Description: Top level design, instantiates IPIF and user logic.
44	-- Date: Fri Jun 24 10:11:25 2005 (by Create and Import Peripheral Wizard)
45	-- VHDL Standard: VHDL'93
46	------------------------------------------------------------------------------
47	-- Naming Conventions:
48	-- active low signals: "*_n"
49	-- clock signals: "clk", "clk_div#", "clk_#x"
50	-- reset signals: "rst", "rst_n"
51	-- generics: "C_*"
52	-- user defined types: "*_TYPE"
53	-- state machine next state: "*_ns"
54	-- state machine current state: "*_cs"
55	-- combinatorial signals: "*_com"
56	-- pipelined or register delay signals: "*_d#"
57	-- counter signals: "cnt"
58	-- clock enable signals: "*_ce"
59	-- internal version of output port: "*_i"
60	-- device pins: "*_pin"
61	-- ports: "- Names begin with Uppercase"
62	-- processes: "*_PROCESS"
63	-- component instantiations: "<ENTITY_>I_<#\|FUNC>"
64	------------------------------------------------------------------------------
65
66	library ieee;
67	use ieee.std_logic_1164.all;
68	use ieee.std_logic_arith.all;
69	use ieee.std_logic_unsigned.all;
70
71	library proc_common_v2_00_a;
72	use proc_common_v2_00_a.proc_common_pkg.all;
73	use proc_common_v2_00_a.ipif_pkg.all;
74	library opb_ipif_v3_01_a;
75	use opb_ipif_v3_01_a.all;
76
77	library radio_controller_v1_00_a;
78	use radio_controller_v1_00_a.all;
79
80	------------------------------------------------------------------------------
81	-- Entity section
82	------------------------------------------------------------------------------
83	-- Definition of Generics:
84	-- C_BASEADDR -- User logic base address
85	-- C_HIGHADDR -- User logic high address
86	-- C_OPB_AWIDTH -- OPB address bus width
87	-- C_OPB_DWIDTH -- OPB data bus width
88	-- C_FAMILY -- Target FPGA architecture
89	--
90	-- Definition of Ports:
91	-- OPB_Clk -- OPB Clock
92	-- OPB_Rst -- OPB Reset
93	-- Sl_DBus -- Slave data bus
94	-- Sl_errAck -- Slave error acknowledge
95	-- Sl_retry -- Slave retry
96	-- Sl_toutSup -- Slave timeout suppress
97	-- Sl_xferAck -- Slave transfer acknowledge
98	-- OPB_ABus -- OPB address bus
99	-- OPB_BE -- OPB byte enable
100	-- OPB_DBus -- OPB data bus
101	-- OPB_RNW -- OPB read/not write
102	-- OPB_select -- OPB select
103	-- OPB_seqAddr -- OPB sequential address
104	------------------------------------------------------------------------------
105
106	entity radio_controller is
107	generic
108	(
109	-- ADD USER GENERICS BELOW THIS LINE ---------------
110	--USER generics added here
111	-- ADD USER GENERICS ABOVE THIS LINE ---------------
112
113	-- DO NOT EDIT BELOW THIS LINE ---------------------
114	-- Bus protocol parameters, do not add to or delete
115	C_BASEADDR : std_logic_vector := X"00000000";
116	C_HIGHADDR : std_logic_vector := X"0000FFFF";
117	C_OPB_AWIDTH : integer := 32;
118	C_OPB_DWIDTH : integer := 32;
119	C_FAMILY : string := "virtex2p"
120	-- DO NOT EDIT ABOVE THIS LINE ---------------------
121	);
122	port
123	(
124	-- ADD USER PORTS BELOW THIS LINE ------------------
125	--USER ports added here
126	-- ADD USER PORTS ABOVE THIS LINE ------------------
127
128	radio1shdn : out std_logic;
129	radio2shdn : out std_logic;
130	radio3shdn : out std_logic;
131	radio4shdn : out std_logic;
132	radio1txen : out std_logic;
133	radio2txen : out std_logic;
134	radio3txen : out std_logic;
135	radio4txen : out std_logic;
136	radio1rxen : out std_logic;
137	radio2rxen : out std_logic;
138	radio3rxen : out std_logic;
139	radio4rxen : out std_logic;
140	radio1ld : in std_logic;
141	radio2ld : in std_logic;
142	radio3ld : in std_logic;
143	radio4ld : in std_logic;
144
145
146	-- DO NOT EDIT BELOW THIS LINE ---------------------
147	-- Bus protocol ports, do not add to or delete
148	OPB_Clk : in std_logic;
149	OPB_Rst : in std_logic;
150	Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
151	Sl_errAck : out std_logic;
152	Sl_retry : out std_logic;
153	Sl_toutSup : out std_logic;
154	Sl_xferAck : out std_logic;
155	OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
156	OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
157	OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
158	OPB_RNW : in std_logic;
159	OPB_select : in std_logic;
160	OPB_seqAddr : in std_logic
161	-- DO NOT EDIT ABOVE THIS LINE ---------------------
162	);
163
164	attribute SIGIS : string;
165	attribute SIGIS of OPB_Clk : signal is "Clk";
166	attribute SIGIS of OPB_Rst : signal is "Rst";
167
168	end entity radio_controller;
169
170	------------------------------------------------------------------------------
171	-- Architecture section
172	------------------------------------------------------------------------------
173
174	architecture IMP of radio_controller is
175
176	------------------------------------------
177	-- Constant: array of address range identifiers
178	------------------------------------------
179	constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE :=
180	(
181	0 => USER_00 -- user logic S/W register address space
182	);
183
184	------------------------------------------
185	-- Constant: array of address pairs for each address range
186	------------------------------------------
187	constant ZERO_ADDR_PAD : std_logic_vector(0 to 64-C_OPB_AWIDTH-1) := (others => '0');
188
189	constant USER_BASEADDR : std_logic_vector := C_BASEADDR;
190	constant USER_HIGHADDR : std_logic_vector := C_HIGHADDR;
191
192	constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
193	(
194	ZERO_ADDR_PAD & USER_BASEADDR, -- user logic base address
195	ZERO_ADDR_PAD & USER_HIGHADDR -- user logic high address
196	);
197
198	------------------------------------------
199	-- Constant: array of data widths for each target address range
200	------------------------------------------
201	constant USER_DWIDTH : integer := 32;
202
203	constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
204	(
205	0 => USER_DWIDTH -- user logic data width
206	);
207
208	------------------------------------------
209	-- Constant: array of desired number of chip enables for each address range
210	------------------------------------------
211	constant USER_NUM_CE : integer := 1;
212
213	constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
214	(
215	0 => pad_power2(USER_NUM_CE) -- user logic number of CEs
216	);
217
218	------------------------------------------
219	-- Constant: array of unique properties for each address range
220	------------------------------------------
221	constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE :=
222	(
223	0 => (others => 0) -- user logic slave space dependent properties (none defined)
224	);
225
226	------------------------------------------
227	-- Constant: pipeline mode
228	-- 1 = include OPB-In pipeline registers
229	-- 2 = include IP pipeline registers
230	-- 3 = include OPB-In and IP pipeline registers
231	-- 4 = include OPB-Out pipeline registers
232	-- 5 = include OPB-In and OPB-Out pipeline registers
233	-- 6 = include IP and OPB-Out pipeline registers
234	-- 7 = include OPB-In, IP, and OPB-Out pipeline registers
235	-- Note:
236	-- only mode 4, 5, 7 are supported for this release
237	------------------------------------------
238	constant PIPELINE_MODEL : integer := 5;
239
240	------------------------------------------
241	-- Constant: user core ID code
242	------------------------------------------
243	constant DEV_BLK_ID : integer := 0;
244
245	------------------------------------------
246	-- Constant: enable MIR/Reset register
247	------------------------------------------
248	constant DEV_MIR_ENABLE : integer := 0;
249
250	------------------------------------------
251	-- Constant: array of IP interrupt mode
252	-- 1 = Active-high interrupt condition
253	-- 2 = Active-low interrupt condition
254	-- 3 = Active-high pulse interrupt event
255	-- 4 = Active-low pulse interrupt event
256	-- 5 = Positive-edge interrupt event
257	-- 6 = Negative-edge interrupt event
258	------------------------------------------
259	constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
260	(
261	0 => 0 -- not used
262	);
263
264	------------------------------------------
265	-- Constant: enable device burst
266	------------------------------------------
267	constant DEV_BURST_ENABLE : integer := 0;
268
269	------------------------------------------
270	-- Constant: include address counter for burst transfers
271	------------------------------------------
272	constant INCLUDE_ADDR_CNTR : integer := 0;
273
274	------------------------------------------
275	-- Constant: include write buffer that decouples OPB and IPIC write transactions
276	------------------------------------------
277	constant INCLUDE_WR_BUF : integer := 0;
278
279	------------------------------------------
280	-- Constant: index for CS/CE
281	------------------------------------------
282	constant USER00_CS_INDEX : integer := get_id_index(ARD_ID_ARRAY, USER_00);
283
284	constant USER00_CE_INDEX : integer := calc_start_ce_index(ARD_NUM_CE_ARRAY, USER00_CS_INDEX);
285
286	------------------------------------------
287	-- IP Interconnect (IPIC) signal declarations -- do not delete
288	-- prefix 'i' stands for IPIF while prefix 'u' stands for user logic
289	-- typically user logic will be hooked up to IPIF directly via i<sig>
290	-- unless signal slicing and muxing are needed via u<sig>
291	------------------------------------------
292	signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
293	signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
294	signal iBus2IP_Data : std_logic_vector(0 to C_OPB_DWIDTH-1);
295	signal iBus2IP_BE : std_logic_vector(0 to C_OPB_DWIDTH/8-1);
296	signal iIP2Bus_Data : std_logic_vector(0 to C_OPB_DWIDTH-1) := (others => '0');
297	signal iIP2Bus_Ack : std_logic := '0';
298	signal iIP2Bus_Error : std_logic := '0';
299	signal iIP2Bus_Retry : std_logic := '0';
300	signal iIP2Bus_ToutSup : std_logic := '0';
301	signal ZERO_IP2Bus_PostedWrInh : std_logic_vector(0 to ARD_ID_ARRAY'length-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
302	signal ZERO_IP2RFIFO_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_RDFIFO_DATA))-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
303	signal ZERO_WFIFO2IP_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_WRFIFO_DATA))-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
304	signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
305	signal iBus2IP_Clk : std_logic;
306	signal iBus2IP_Reset : std_logic;
307	signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1);
308	signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1);
309	signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1);
310	signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1);
311	signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1);
312
313	------------------------------------------
314	-- Component declaration for verilog user logic
315	------------------------------------------
316	component user_logic is
317	generic
318	(
319	-- ADD USER GENERICS BELOW THIS LINE ---------------
320	--USER generics added here
321	-- ADD USER GENERICS ABOVE THIS LINE ---------------
322
323	-- DO NOT EDIT BELOW THIS LINE ---------------------
324	-- Bus protocol parameters, do not add to or delete
325	C_DWIDTH : integer := 32;
326	C_NUM_CE : integer := 1
327	-- DO NOT EDIT ABOVE THIS LINE ---------------------
328	);
329	port
330	(
331	-- ADD USER PORTS BELOW THIS LINE ------------------
332	--USER ports added here
333
334	Radio1SHDN : out std_logic;
335	Radio2SHDN : out std_logic;
336	Radio3SHDN : out std_logic;
337	Radio4SHDN : out std_logic;
338	Radio1TxEn : out std_logic;
339	Radio2TxEn : out std_logic;
340	Radio3TxEn : out std_logic;
341	Radio4TxEn : out std_logic;
342	Radio1RxEn : out std_logic;
343	Radio2RxEn : out std_logic;
344	Radio3RxEn : out std_logic;
345	Radio4RxEn : out std_logic;
346	Radio1LD : in std_logic;
347	Radio2LD : in std_logic;
348	Radio3LD : in std_logic;
349	Radio4LD : in std_logic;
350
351
352	-- ADD USER PORTS ABOVE THIS LINE ------------------
353
354	-- DO NOT EDIT BELOW THIS LINE ---------------------
355	-- Bus protocol ports, do not add to or delete
356	Bus2IP_Clk : in std_logic;
357	Bus2IP_Reset : in std_logic;
358	Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
359	Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
360	Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1);
361	Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1);
362	IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
363	IP2Bus_Ack : out std_logic;
364	IP2Bus_Retry : out std_logic;
365	IP2Bus_Error : out std_logic;
366	IP2Bus_ToutSup : out std_logic
367	-- DO NOT EDIT ABOVE THIS LINE ---------------------
368	);
369	end component user_logic;
370
371	begin
372
373	------------------------------------------
374	-- instantiate the OPB IPIF
375	------------------------------------------
376	OPB_IPIF_I : entity opb_ipif_v3_01_a.opb_ipif
377	generic map
378	(
379	C_ARD_ID_ARRAY => ARD_ID_ARRAY,
380	C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
381	C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY,
382	C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
383	C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY,
384	C_PIPELINE_MODEL => PIPELINE_MODEL,
385	C_DEV_BLK_ID => DEV_BLK_ID,
386	C_DEV_MIR_ENABLE => DEV_MIR_ENABLE,
387	C_OPB_AWIDTH => C_OPB_AWIDTH,
388	C_OPB_DWIDTH => C_OPB_DWIDTH,
389	C_FAMILY => C_FAMILY,
390	C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
391	C_DEV_BURST_ENABLE => DEV_BURST_ENABLE,
392	C_INCLUDE_ADDR_CNTR => INCLUDE_ADDR_CNTR,
393	C_INCLUDE_WR_BUF => INCLUDE_WR_BUF
394	)
395	port map
396	(
397	OPB_select => OPB_select,
398	OPB_DBus => OPB_DBus,
399	OPB_ABus => OPB_ABus,
400	OPB_BE => OPB_BE,
401	OPB_RNW => OPB_RNW,
402	OPB_seqAddr => OPB_seqAddr,
403	Sln_DBus => Sl_DBus,
404	Sln_xferAck => Sl_xferAck,
405	Sln_errAck => Sl_errAck,
406	Sln_retry => Sl_retry,
407	Sln_toutSup => Sl_toutSup,
408	Bus2IP_CS => open,
409	Bus2IP_CE => open,
410	Bus2IP_RdCE => iBus2IP_RdCE,
411	Bus2IP_WrCE => iBus2IP_WrCE,
412	Bus2IP_Data => iBus2IP_Data,
413	Bus2IP_Addr => open,
414	Bus2IP_AddrValid => open,
415	Bus2IP_BE => iBus2IP_BE,
416	Bus2IP_RNW => open,
417	Bus2IP_Burst => open,
418	IP2Bus_Data => iIP2Bus_Data,
419	IP2Bus_Ack => iIP2Bus_Ack,
420	IP2Bus_AddrAck => '0',
421	IP2Bus_Error => iIP2Bus_Error,
422	IP2Bus_Retry => iIP2Bus_Retry,
423	IP2Bus_ToutSup => iIP2Bus_ToutSup,
424	IP2Bus_PostedWrInh => ZERO_IP2Bus_PostedWrInh,
425	IP2RFIFO_Data => ZERO_IP2RFIFO_Data,
426	IP2RFIFO_WrMark => '0',
427	IP2RFIFO_WrRelease => '0',
428	IP2RFIFO_WrReq => '0',
429	IP2RFIFO_WrRestore => '0',
430	RFIFO2IP_AlmostFull => open,
431	RFIFO2IP_Full => open,
432	RFIFO2IP_Vacancy => open,
433	RFIFO2IP_WrAck => open,
434	IP2WFIFO_RdMark => '0',
435	IP2WFIFO_RdRelease => '0',
436	IP2WFIFO_RdReq => '0',
437	IP2WFIFO_RdRestore => '0',
438	WFIFO2IP_AlmostEmpty => open,
439	WFIFO2IP_Data => ZERO_WFIFO2IP_Data,
440	WFIFO2IP_Empty => open,
441	WFIFO2IP_Occupancy => open,
442	WFIFO2IP_RdAck => open,
443	IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent,
444	IP2INTC_Irpt => open,
445	Freeze => '0',
446	Bus2IP_Freeze => open,
447	OPB_Clk => OPB_Clk,
448	Bus2IP_Clk => iBus2IP_Clk,
449	IP2Bus_Clk => '0',
450	Reset => OPB_Rst,
451	Bus2IP_Reset => iBus2IP_Reset
452	);
453
454	------------------------------------------
455	-- instantiate the User Logic
456	------------------------------------------
457	USER_LOGIC_I : component user_logic
458	generic map
459	(
460	-- MAP USER GENERICS BELOW THIS LINE ---------------
461	--USER generics mapped here
462	-- MAP USER GENERICS ABOVE THIS LINE ---------------
463
464	C_DWIDTH => USER_DWIDTH,
465	C_NUM_CE => USER_NUM_CE
466	)
467	port map
468	(
469	-- MAP USER PORTS BELOW THIS LINE ------------------
470	--USER ports mapped here
471
472	Radio1SHDN => radio1shdn,
473	Radio2SHDN => radio2shdn,
474	Radio3SHDN => radio3shdn,
475	Radio4SHDN => radio4shdn,
476	Radio1TxEn => radio1txen,
477	Radio2TxEn => radio2txen,
478	Radio3TxEn => radio3txen,
479	Radio4TxEn => radio4txen,
480	Radio1RxEn => radio1rxen,
481	Radio2RxEn => radio2rxen,
482	Radio3RxEn => radio3rxen,
483	Radio4RxEn => radio4rxen,
484	Radio1LD => radio1ld,
485	Radio2LD => radio2ld,
486	Radio3LD => radio3ld,
487	Radio4LD => radio4ld,
488
489	-- MAP USER PORTS ABOVE THIS LINE ------------------
490
491	Bus2IP_Clk => iBus2IP_Clk,
492	Bus2IP_Reset => iBus2IP_Reset,
493	Bus2IP_Data => uBus2IP_Data,
494	Bus2IP_BE => uBus2IP_BE,
495	Bus2IP_RdCE => uBus2IP_RdCE,
496	Bus2IP_WrCE => uBus2IP_WrCE,
497	IP2Bus_Data => uIP2Bus_Data,
498	IP2Bus_Ack => iIP2Bus_Ack,
499	IP2Bus_Retry => iIP2Bus_Retry,
500	IP2Bus_Error => iIP2Bus_Error,
501	IP2Bus_ToutSup => iIP2Bus_ToutSup
502	);
503
504	------------------------------------------
505	-- hooking up signal slicing
506	------------------------------------------
507	uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1);
508	uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1);
509	uBus2IP_RdCE <= iBus2IP_RdCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1);
510	uBus2IP_WrCE <= iBus2IP_WrCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1);
511	iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data;
512
513	end IMP;

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