1 | ## Copyright (c) 2004 Xilinx, Inc. All Rights Reserved.
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2 | ## You may copy and modify these files for your own internal use solely with
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3 | ## Xilinx programmable logic devices and Xilinx EDK system or create IP
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4 | ## modules solely for Xilinx programmable logic devices and Xilinx EDK system.
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5 | ## No rights are granted to distribute any files unless they are distributed in
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6 | ## Xilinx programmable logic devices.
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7 | ###################################################################
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8 | ##
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9 | ## Name : radio_controller
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10 | ## Desc : Microprocessor Peripheral Description
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11 | ## : Automatically generated by PsfUtility
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12 | ##
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13 | ###################################################################
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14 |
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15 | BEGIN radio_controller
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16 |
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17 | ## Peripheral Options
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18 | OPTION IPTYPE = PERIPHERAL
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19 | OPTION IMP_NETLIST = TRUE
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20 | OPTION HDL = MIXED
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21 | OPTION IP_GROUP = MICROBLAZE:PPC:USER
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22 | OPTION CORE_STATE = DEVELOPMENT
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23 |
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24 |
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25 | ## Bus Interfaces
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26 | BUS_INTERFACE BUS = SOPB, BUS_TYPE = SLAVE, BUS_STD = OPB
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27 |
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28 | ## Generics for VHDL or Parameters for Verilog
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29 | PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x100, BUS = SOPB, ADDRESS = BASE, PAIR = C_HIGHADDR
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30 | PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, BUS = SOPB, ADDRESS = HIGH, PAIR = C_BASEADDR
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31 | PARAMETER C_OPB_AWIDTH = 32, DT = INTEGER, BUS = SOPB
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32 | PARAMETER C_OPB_DWIDTH = 32, DT = INTEGER, BUS = SOPB
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33 | PARAMETER C_FAMILY = virtex2p, DT = STRING
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34 |
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35 | ## Ports
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36 | PORT OPB_Clk = "", DIR = I, SIGIS = Clk, BUS = SOPB
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37 | PORT OPB_Rst = OPB_Rst, DIR = I, SIGIS = Rst, BUS = SOPB
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38 | PORT Sl_DBus = Sl_DBus, DIR = O, VEC = [0:(C_OPB_DWIDTH-1)], BUS = SOPB
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39 | PORT Sl_errAck = Sl_errAck, DIR = O, BUS = SOPB
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40 | PORT Sl_retry = Sl_retry, DIR = O, BUS = SOPB
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41 | PORT Sl_toutSup = Sl_toutSup, DIR = O, BUS = SOPB
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42 | PORT Sl_xferAck = Sl_xferAck, DIR = O, BUS = SOPB
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43 | PORT OPB_ABus = OPB_ABus, DIR = I, VEC = [0:(C_OPB_AWIDTH-1)], BUS = SOPB
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44 | PORT OPB_BE = OPB_BE, DIR = I, VEC = [0:((C_OPB_DWIDTH/8)-1)], BUS = SOPB
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45 | PORT OPB_DBus = OPB_DBus, DIR = I, VEC = [0:(C_OPB_DWIDTH-1)], BUS = SOPB
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46 | PORT OPB_RNW = OPB_RNW, DIR = I, BUS = SOPB
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47 | PORT OPB_select = OPB_select, DIR = I, BUS = SOPB
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48 | PORT OPB_seqAddr = OPB_seqAddr, DIR = I, BUS = SOPB
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49 |
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50 | PORT radio1_shdn = "", DIR = O
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51 | PORT radio1_txen = "", DIR = O
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52 | PORT radio1_rxen = "", DIR = O
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53 | PORT radio1_rxhp = "", DIR = O
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54 | PORT radio1_ld = "", DIR = I
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55 | PORT radio1_24pa = "", DIR = O
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56 | PORT radio1_5pa = "", DIR = O
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57 | PORT radio1_antsw = "", DIR = O, VEC = [0:1]
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58 | PORT radio1_led = "", DIR = O, VEC = [0:2]
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59 | PORT radio2_shdn = "", DIR = O
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60 | PORT radio2_txen = "", DIR = O
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61 | PORT radio2_rxen = "", DIR = O
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62 | PORT radio2_rxhp = "", DIR = O
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63 | PORT radio2_ld = "", DIR = I
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64 | PORT radio2_24pa = "", DIR = O
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65 | PORT radio2_5pa = "", DIR = O
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66 | PORT radio2_antsw = "", DIR = O, VEC = [0:1]
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67 | PORT radio2_led = "", DIR = O, VEC = [0:2]
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68 | PORT radio3_shdn = "", DIR = O
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69 | PORT radio3_txen = "", DIR = O
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70 | PORT radio3_rxen = "", DIR = O
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71 | PORT radio3_rxhp = "", DIR = O
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72 | PORT radio3_ld = "", DIR = I
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73 | PORT radio3_24pa = "", DIR = O
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74 | PORT radio3_5pa = "", DIR = O
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75 | PORT radio3_antsw = "", DIR = O, VEC = [0:1]
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76 | PORT radio3_led = "", DIR = O, VEC = [0:2]
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77 | PORT radio4_shdn = "", DIR = O
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78 | PORT radio4_txen = "", DIR = O
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79 | PORT radio4_rxen = "", DIR = O
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80 | PORT radio4_rxhp = "", DIR = O
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81 | PORT radio4_ld = "", DIR = I
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82 | PORT radio4_24pa = "", DIR = O
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83 | PORT radio4_5pa = "", DIR = O
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84 | PORT radio4_antsw = "", DIR = O, VEC = [0:1]
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85 | PORT radio4_led = "", DIR = O, VEC = [0:2]
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86 |
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87 |
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88 | END
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