1 | TABLE OF CONTENTS |
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2 | 1) Peripheral Summary |
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3 | 2) Description of Generated Files |
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4 | 3) Description of Used IPIC Signals |
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5 | 4) Description of Top Level Generics |
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6 | |
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7 | |
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8 | ================================================================================ |
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9 | * 1) Peripheral Summary * |
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10 | ================================================================================ |
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11 | Peripheral summary |
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12 | |
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13 | XPS project / EDK repository : C:\edk_user_repository\MyProcessorIPLib |
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14 | logical library name : radio_controller_v1_01_a |
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15 | top name : radio_controller |
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16 | version : 1.01.a |
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17 | type : OPB slave |
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18 | features : slave attachement |
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19 | user s/w registers |
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20 | |
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21 | Address Block for User Logic and IPIF Predefined Services |
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22 | |
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23 | User logic slave space service : C_BASEADDR + 0x00000000 |
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24 | : C_BASEADDR + 0x000000FF |
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25 | |
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26 | |
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27 | ================================================================================ |
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28 | * 2) Description of Generated Files * |
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29 | ================================================================================ |
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30 | - HDL source file(s) |
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31 | C:\edk_user_repository\MyProcessorIPLib\pcores\radio_controller_v1_01_a\hdl |
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32 | |
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33 | vhdl/radio_controller.vhd |
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34 | |
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35 | This is the template file for your peripheral's top design entity. It |
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36 | configures and instantiates the corresponding IPIF unit in the way you |
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37 | indicated in the wizard GUI and hooks it up to the stub user logic where |
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38 | the actual functionalites should get implemented. You are not expected to |
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39 | modify this template file except certain marked places for adding user |
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40 | specific generics and ports. |
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41 | |
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42 | verilog/user_logic.v |
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43 | |
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44 | This is the template file for the stub user logic design entity, either in |
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45 | VHDL or Verilog, where the actual functionalities should get implemented. |
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46 | Some sample code snippet may be provided for demonstration purpose. |
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47 | |
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48 | |
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49 | - XPS interface file(s) |
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50 | C:\edk_user_repository\MyProcessorIPLib\pcores\radio_controller_v1_01_a\data |
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51 | |
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52 | radio_controller_v2_1_0.mpd |
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53 | |
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54 | This Microprocessor Peripheral Description file contains information of the |
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55 | interface of your peripheral, so that other EDK tools can recognize your |
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56 | peripheral. |
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57 | |
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58 | radio_controller_v2_1_0.pao |
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59 | |
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60 | This Peripheral Analysis Order file defines the analysis order of all the HDL |
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61 | source files that are used to compile your peripheral. |
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62 | |
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63 | |
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64 | - ISE project file(s) |
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65 | C:\edk_user_repository\MyProcessorIPLib\pcores\radio_controller_v1_01_a\devl\projnav |
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66 | |
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67 | radio_controller.npl |
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68 | |
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69 | This is the ProjNavigator project file. It sets up the needed logical |
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70 | libraries and dependent library files for you to help you develop your |
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71 | peripheral using ProjNavigator. |
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72 | |
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73 | radio_controller.cli |
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74 | |
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75 | This is the TCL command line file used to generate the .npl file. |
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76 | |
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77 | |
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78 | - XST synthesis file(s) |
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79 | C:\edk_user_repository\MyProcessorIPLib\pcores\radio_controller_v1_01_a\devl\synthesis |
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80 | |
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81 | radio_controller_xst.scr |
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82 | |
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83 | This is the XST synthesis script file to compile your peripheral. |
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84 | Note: you may want to modify the device part option for your target. |
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85 | |
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86 | radio_controller_xst.prj |
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87 | |
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88 | This is the XST synthesis project file used by the above script file to |
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89 | compile your peripheral. |
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90 | |
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91 | |
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92 | - Driver source file(s) |
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93 | C:\edk_user_repository\MyProcessorIPLib\drivers\radio_controller_v1_01_a\src |
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94 | |
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95 | radio_controller.h |
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96 | |
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97 | This is the software driver header template file, which contains address offset of |
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98 | software addressable registers in your peripheral, as well as some common masks and |
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99 | simple register access macros or function declaration. |
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100 | |
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101 | radio_controller.c |
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102 | |
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103 | This is the software driver source template file, to define all applicable driver |
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104 | functions. |
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105 | |
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106 | radio_controller_selftest.c |
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107 | |
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108 | This is the software driver self test example file, which contain self test example |
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109 | code to test various hardware features of your peripheral. |
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110 | |
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111 | Makefile |
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112 | |
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113 | This is the software driver makefile to compile drivers. |
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114 | |
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115 | |
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116 | - Driver interface file(s) |
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117 | C:\edk_user_repository\MyProcessorIPLib\drivers\radio_controller_v1_01_a\data |
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118 | |
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119 | radio_controller_v2_1_0.mdd |
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120 | |
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121 | This is the Microprocessor Driver Definition file. |
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122 | |
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123 | radio_controller_v2_1_0.tcl |
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124 | |
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125 | This is the Microprocessor Driver Command file. |
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126 | |
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127 | |
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128 | - Other misc file(s) |
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129 | C:\edk_user_repository\MyProcessorIPLib\pcores\radio_controller_v1_01_a\devl |
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130 | |
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131 | ipwiz.opt |
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132 | |
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133 | This is the option setting file for the wizard batch mode, which should |
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134 | generate the same result as the wizard GUI mode. |
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135 | |
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136 | README.txt |
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137 | |
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138 | This README file for your peripheral. |
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139 | |
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140 | ipwiz.log |
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141 | |
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142 | This is the log file by operating on this wizard. |
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143 | |
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144 | |
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145 | ================================================================================ |
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146 | * 3) Description of Used IPIC Signals * |
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147 | ================================================================================ |
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148 | For more information (usage, timing diagrams, etc.) regarding the IPIC signals |
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149 | used in the templates, please refer to the following specifications (under |
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150 | %XILINX_EDK%\doc for windows or $XILINX_EDK/doc for solaris and linux): |
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151 | proc_ip_ref_guide.pdf - Processor IP Reference Guide (chapter 4 IPIF) |
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152 | user_core_templates_ref_guide.pdf - User Core Templates Reference Guide |
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153 | |
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154 | Bus2IP_Clk |
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155 | This is the clock input to the user logic. All IPIC signals are synchronous |
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156 | to this clock. It is identical to the <bus>_Clk signal that is an input to |
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157 | the user core. In an OPB core, Bus2IP_Clk is the same as OPB_Clk, and in a |
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158 | PLB core, it is the same as PLB_Clk. No additional buffering is provided on |
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159 | the clock; it is passed through as is. |
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160 | |
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161 | Bus2IP_Reset |
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162 | Signal to reset the User Logic; asserts whenever the <bus>_Rst signal does |
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163 | and, if the Reset block is included, whenever there is a software-programmed |
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164 | reset. |
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165 | |
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166 | Bus2IP_Data |
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167 | This is the data bus from the IPIF to the user logic; it is used for both |
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168 | master and slave transactions. It is used to access user logic registers. |
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169 | |
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170 | Bus2IP_BE |
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171 | The Bus2IP_BE is a bus of Byte Enable qualifiers from the IPIF to the user |
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172 | logic. A bit in the Bus2IP_BE set to '1' indicates that the associated byte |
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173 | lane contains valid data. For example, if Bus2IP_BE = 0011, this indicates |
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174 | that byte lanes 2 and 3 contains valid data. |
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175 | |
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176 | Bus2IP_RdCE |
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177 | The Bus2IP_RdCE bus is an input to the user logic. It is Bus2IP_CE qualified |
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178 | by a read transaction. |
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179 | |
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180 | Bus2IP_WrCE |
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181 | The Bus2IP_WrCE bus is an input to the user logic. It is Bus2IP_CE qualified |
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182 | by a write transaction. |
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183 | |
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184 | IP2Bus_Data |
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185 | This is the data bus from the user logic to the IPIF; it is used for both |
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186 | master and slave transactions. It is used to access user logic registers. |
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187 | |
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188 | IP2Bus_Ack |
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189 | The IP2Bus_Ack signal provide the read/write acknowledgement from the user |
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190 | logic to the IPIF. For writes, it indicates the data has been taken by the |
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191 | user logic. For reads, it indicates that valid data is available. For |
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192 | immediate acknowledgement (such as for a register read/write), this signal |
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193 | can be tied to '1'. Wait states can be inserted in the transaction by |
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194 | delaying the assertion of the acknowledgement. If the IP2Bus_Ack for OPB |
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195 | cores will be delayed more than 8 clocks, then the IP2Bus_ToutSup (timeout |
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196 | suppress) signal must also be asserted to prevent a timeout on the host bus. |
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197 | |
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198 | IP2Bus_Retry |
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199 | IP2Bus_Retry is a response from the user logic to the IPIF that indicates |
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200 | the currently requested transaction cannot be completed at this time and |
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201 | that the requesting master should retry the operation. If the IP2Bus_Retry |
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202 | signal will be delayed more than 8 clocks, then the IP2Bus_ToutSup (timeout |
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203 | suppress) signal must also be asserted to prevent a timeout on the host bus. |
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204 | Note: this signal is unused by PLB IPIF. |
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205 | |
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206 | IP2Bus_Error |
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207 | This signal from the user logic to the IPIF indicates an error has occurred |
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208 | during the current transaction. It is valid when IP2Bus_Ack is asserted. |
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209 | |
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210 | IP2Bus_ToutSup |
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211 | The IP2Bus_ToutSup must be asserted by the user logic whenever its |
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212 | acknowledgement or retry response will take longer than 8 clock cycles. |
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213 | |
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214 | ================================================================================ |
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215 | * 4) Description of Top Level Generics * |
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216 | ================================================================================ |
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217 | C_BASEADDR/C_HIGHADDR |
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218 | These two generics are used to define the memory mapped address space for |
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219 | the peripheral registers, including Reset/MIR register, Interrupt Source |
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220 | Controller registers, Read/Write FIFO control/data registers, user logic |
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221 | software accessible registers and etc., but excluding those user logic |
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222 | address ranges if ever used. When instantiation, the address space size |
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223 | determined by these two generics must be a power of 2 (e.g. 2^k = |
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224 | C_HIGHADDR - C_BASEADDR + 1), a factor of C_BASEADDR and larger than the |
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225 | minimum size as indicated in the template. |
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226 | |
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227 | C_OPB_DWIDTH |
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228 | This is the data bus width for On-chip Peripheral Bus (OPB). It should |
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229 | always be set to 32 as of today. |
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230 | |
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231 | C_OPB_AWIDTH |
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232 | This is the address bus width for On-chip Peripheral Bus (OPB). It should |
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233 | always be set to 32 as of today. |
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234 | |
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235 | C_FAMILY |
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236 | This is to set the target FPGA architecture, s.t. virtex2, virtex2p, etc. |
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237 | |
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