source: PlatformSupport/Deprecated/pcores/radio_controller_v1_01_a/devl/synthesis/radio_controller_xst.prj

Last change on this file was 35, checked in by snovich, 19 years ago

Working new radio controller and working spi controller
File size: 4.6 KB
Line 
1vhdl proc_common_v2_00_a C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\proc_common_pkg.vhd
2vhdl proc_common_v2_00_a C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\family.vhd
3vhdl proc_common_v2_00_a C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\or_muxcy.vhd
4vhdl proc_common_v2_00_a C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\or_gate.vhd
5vhdl proc_common_v2_00_a C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\counter_bit.vhd
6vhdl proc_common_v2_00_a C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\counter.vhd
7vhdl proc_common_v2_00_a C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\inferred_lut4.vhd
8vhdl proc_common_v2_00_a C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\srl_fifo2.vhd
9vhdl proc_common_v2_00_a C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_counter_bit.vhd
10vhdl proc_common_v2_00_a C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_counter.vhd
11vhdl proc_common_v2_00_a C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_counter_top.vhd
12vhdl proc_common_v2_00_a C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_occ_counter.vhd
13vhdl proc_common_v2_00_a C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_occ_counter_top.vhd
14vhdl proc_common_v2_00_a C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_adder_bit.vhd
15vhdl proc_common_v2_00_a C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_adder.vhd
16vhdl proc_common_v2_00_a C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_dpram_select.vhd
17vhdl proc_common_v2_00_a C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\srl16_fifo.vhd
18vhdl proc_common_v2_00_a C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pselect.vhd
19vhdl proc_common_v2_00_a C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\valid_be.vhd
20vhdl proc_common_v2_00_a C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\ld_arith_reg.vhd
21vhdl proc_common_v2_00_a C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\mux_onehot.vhd
22vhdl proc_common_v2_00_a C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\down_counter.vhd
23vhdl proc_common_v2_00_a C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\ipif_pkg.vhd
24vhdl proc_common_v2_00_a C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\ipif_steer.vhd
25vhdl proc_common_v2_00_a C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\direct_path_cntr_ai.vhd
26vhdl interrupt_control_v1_00_a C:\EDK\\hw\XilinxProcessorIPLib\pcores\interrupt_control_v1_00_a\hdl\vhdl\interrupt_control.vhd
27vhdl wrpfifo_v1_01_b C:\EDK\\hw\XilinxProcessorIPLib\pcores\wrpfifo_v1_01_b\hdl\vhdl\pf_dly1_mux.vhd
28vhdl wrpfifo_v1_01_b C:\EDK\\hw\XilinxProcessorIPLib\pcores\wrpfifo_v1_01_b\hdl\vhdl\ipif_control_wr.vhd
29vhdl wrpfifo_v1_01_b C:\EDK\\hw\XilinxProcessorIPLib\pcores\wrpfifo_v1_01_b\hdl\vhdl\wrpfifo_dp_cntl.vhd
30vhdl wrpfifo_v1_01_b C:\EDK\\hw\XilinxProcessorIPLib\pcores\wrpfifo_v1_01_b\hdl\vhdl\wrpfifo_top.vhd
31vhdl rdpfifo_v1_01_b C:\EDK\\hw\XilinxProcessorIPLib\pcores\rdpfifo_v1_01_b\hdl\vhdl\ipif_control_rd.vhd
32vhdl rdpfifo_v1_01_b C:\EDK\\hw\XilinxProcessorIPLib\pcores\rdpfifo_v1_01_b\hdl\vhdl\rdpfifo_dp_cntl.vhd
33vhdl rdpfifo_v1_01_b C:\EDK\\hw\XilinxProcessorIPLib\pcores\rdpfifo_v1_01_b\hdl\vhdl\rdpfifo_top.vhd
34vhdl opb_ipif_v3_01_a C:\EDK\\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\reset_mir.vhd
35vhdl opb_ipif_v3_01_a C:\EDK\\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\brst_addr_cntr.vhd
36vhdl opb_ipif_v3_01_a C:\EDK\\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\opb_flex_addr_cntr.vhd
37vhdl opb_ipif_v3_01_a C:\EDK\\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\brst_addr_cntr_reg.vhd
38vhdl opb_ipif_v3_01_a C:\EDK\\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\opb_be_gen.vhd
39vhdl opb_ipif_v3_01_a C:\EDK\\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\srl_fifo3.vhd
40vhdl opb_ipif_v3_01_a C:\EDK\\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\write_buffer.vhd
41vhdl opb_ipif_v3_01_a C:\EDK\\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\opb_bam.vhd
42vhdl opb_ipif_v3_01_a C:\EDK\\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\opb_ipif.vhd
43verilog radio_controller_v1_01_a ..\..\hdl\verilog\user_logic.v
44vhdl radio_controller_v1_01_a ..\..\hdl\vhdl\radio_controller.vhd
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