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source: PlatformSupport/Deprecated/pcores/radio_controller_v1_01_a/hdl/vhdl/radio_controller.vhd

Last change on this file was 35, checked in by snovich, 19 years ago
Working new radio controller and working spi controller
File size: 25.7 KB

Line
1	------------------------------------------------------------------------------
2	-- radio_controller.vhd - entity/architecture pair
3	------------------------------------------------------------------------------
4	-- IMPORTANT:
5	-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
6	--
7	-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
8	--
9	-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
10	-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
11	-- OF THE USER_LOGIC ENTITY.
12	------------------------------------------------------------------------------
13	--
14	-- ***************************************************************************
15	-- Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
16	--
17	-- Xilinx, Inc.
18	-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
19	-- AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
20	-- SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
21	-- OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
22	-- APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
23	-- THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
24	-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
25	-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
26	-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
27	-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
28	-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
29	-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
30	-- FOR A PARTICULAR PURPOSE.
31	--
32	-- YOU MAY COPY AND MODIFY THESE FILES FOR YOUR OWN INTERNAL USE SOLELY
33	-- WITH XILINX PROGRAMMABLE LOGIC DEVICES AND XILINX EDK SYSTEM OR
34	-- CREATE IP MODULES SOLELY FOR XILINX PROGRAMMABLE LOGIC DEVICES AND
35	-- XILINX EDK SYSTEM. NO RIGHTS ARE GRANTED TO DISTRIBUTE ANY FILES
36	-- UNLESS THEY ARE DISTRIBUTED IN XILINX PROGRAMMABLE LOGIC DEVICES.
37	--
38	-- ***************************************************************************
39	--
40	------------------------------------------------------------------------------
41	-- Filename: radio_controller.vhd
42	-- Version: 1.01.a
43	-- Description: Top level design, instantiates IPIF and user logic.
44	-- Date: Thu Jul 07 16:33:45 2005 (by Create and Import Peripheral Wizard)
45	-- VHDL Standard: VHDL'93
46	------------------------------------------------------------------------------
47	-- Naming Conventions:
48	-- active low signals: "*_n"
49	-- clock signals: "clk", "clk_div#", "clk_#x"
50	-- reset signals: "rst", "rst_n"
51	-- generics: "C_*"
52	-- user defined types: "*_TYPE"
53	-- state machine next state: "*_ns"
54	-- state machine current state: "*_cs"
55	-- combinatorial signals: "*_com"
56	-- pipelined or register delay signals: "*_d#"
57	-- counter signals: "cnt"
58	-- clock enable signals: "*_ce"
59	-- internal version of output port: "*_i"
60	-- device pins: "*_pin"
61	-- ports: "- Names begin with Uppercase"
62	-- processes: "*_PROCESS"
63	-- component instantiations: "<ENTITY_>I_<#\|FUNC>"
64	------------------------------------------------------------------------------
65
66	library ieee;
67	use ieee.std_logic_1164.all;
68	use ieee.std_logic_arith.all;
69	use ieee.std_logic_unsigned.all;
70
71	library proc_common_v2_00_a;
72	use proc_common_v2_00_a.proc_common_pkg.all;
73	use proc_common_v2_00_a.ipif_pkg.all;
74	library opb_ipif_v3_01_a;
75	use opb_ipif_v3_01_a.all;
76
77	library radio_controller_v1_01_a;
78	use radio_controller_v1_01_a.all;
79
80	------------------------------------------------------------------------------
81	-- Entity section
82	------------------------------------------------------------------------------
83	-- Definition of Generics:
84	-- C_BASEADDR -- User logic base address
85	-- C_HIGHADDR -- User logic high address
86	-- C_OPB_AWIDTH -- OPB address bus width
87	-- C_OPB_DWIDTH -- OPB data bus width
88	-- C_FAMILY -- Target FPGA architecture
89	--
90	-- Definition of Ports:
91	-- OPB_Clk -- OPB Clock
92	-- OPB_Rst -- OPB Reset
93	-- Sl_DBus -- Slave data bus
94	-- Sl_errAck -- Slave error acknowledge
95	-- Sl_retry -- Slave retry
96	-- Sl_toutSup -- Slave timeout suppress
97	-- Sl_xferAck -- Slave transfer acknowledge
98	-- OPB_ABus -- OPB address bus
99	-- OPB_BE -- OPB byte enable
100	-- OPB_DBus -- OPB data bus
101	-- OPB_RNW -- OPB read/not write
102	-- OPB_select -- OPB select
103	-- OPB_seqAddr -- OPB sequential address
104	------------------------------------------------------------------------------
105
106	entity radio_controller is
107	generic
108	(
109	-- ADD USER GENERICS BELOW THIS LINE ---------------
110	--USER generics added here
111	-- ADD USER GENERICS ABOVE THIS LINE ---------------
112
113	-- DO NOT EDIT BELOW THIS LINE ---------------------
114	-- Bus protocol parameters, do not add to or delete
115	C_BASEADDR : std_logic_vector := X"00000000";
116	C_HIGHADDR : std_logic_vector := X"0000FFFF";
117	C_OPB_AWIDTH : integer := 32;
118	C_OPB_DWIDTH : integer := 32;
119	C_FAMILY : string := "virtex2p"
120	-- DO NOT EDIT ABOVE THIS LINE ---------------------
121	);
122	port
123	(
124	-- ADD USER PORTS BELOW THIS LINE ------------------
125	--USER ports added here
126
127	radio1_shdn : out std_logic;
128	radio1_txen : out std_logic;
129	radio1_rxen : out std_logic;
130	radio1_rxhp : out std_logic;
131	radio1_ld : in std_logic;
132	radio1_24pa : out std_logic;
133	radio1_5pa : out std_logic;
134	radio1_antsw : out std_logic_vector(0 to 1);
135	radio1_led : out std_logic_vector(0 to 2);
136	radio2_shdn : out std_logic;
137	radio2_txen : out std_logic;
138	radio2_rxen : out std_logic;
139	radio2_rxhp : out std_logic;
140	radio2_ld : in std_logic;
141	radio2_24pa : out std_logic;
142	radio2_5pa : out std_logic;
143	radio2_antsw : out std_logic_vector(0 to 1);
144	radio2_led : out std_logic_vector(0 to 2);
145	radio3_shdn : out std_logic;
146	radio3_txen : out std_logic;
147	radio3_rxen : out std_logic;
148	radio3_rxhp : out std_logic;
149	radio3_ld : in std_logic;
150	radio3_24pa : out std_logic;
151	radio3_5pa : out std_logic;
152	radio3_antsw : out std_logic_vector(0 to 1);
153	radio3_led : out std_logic_vector(0 to 2);
154	radio4_shdn : out std_logic;
155	radio4_txen : out std_logic;
156	radio4_rxen : out std_logic;
157	radio4_rxhp : out std_logic;
158	radio4_ld : in std_logic;
159	radio4_24pa : out std_logic;
160	radio4_5pa : out std_logic;
161	radio4_antsw : out std_logic_vector(0 to 1);
162	radio4_led : out std_logic_vector(0 to 2);
163
164
165	-- ADD USER PORTS ABOVE THIS LINE ------------------
166
167	-- DO NOT EDIT BELOW THIS LINE ---------------------
168	-- Bus protocol ports, do not add to or delete
169	OPB_Clk : in std_logic;
170	OPB_Rst : in std_logic;
171	Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
172	Sl_errAck : out std_logic;
173	Sl_retry : out std_logic;
174	Sl_toutSup : out std_logic;
175	Sl_xferAck : out std_logic;
176	OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
177	OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
178	OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
179	OPB_RNW : in std_logic;
180	OPB_select : in std_logic;
181	OPB_seqAddr : in std_logic
182	-- DO NOT EDIT ABOVE THIS LINE ---------------------
183	);
184
185	attribute SIGIS : string;
186	attribute SIGIS of OPB_Clk : signal is "Clk";
187	attribute SIGIS of OPB_Rst : signal is "Rst";
188
189	end entity radio_controller;
190
191	------------------------------------------------------------------------------
192	-- Architecture section
193	------------------------------------------------------------------------------
194
195	architecture IMP of radio_controller is
196
197	------------------------------------------
198	-- Constant: array of address range identifiers
199	------------------------------------------
200	constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE :=
201	(
202	0 => USER_00 -- user logic S/W register address space
203	);
204
205	------------------------------------------
206	-- Constant: array of address pairs for each address range
207	------------------------------------------
208	constant ZERO_ADDR_PAD : std_logic_vector(0 to 64-C_OPB_AWIDTH-1) := (others => '0');
209
210	constant USER_BASEADDR : std_logic_vector := C_BASEADDR;
211	constant USER_HIGHADDR : std_logic_vector := C_HIGHADDR;
212
213	constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
214	(
215	ZERO_ADDR_PAD & USER_BASEADDR, -- user logic base address
216	ZERO_ADDR_PAD & USER_HIGHADDR -- user logic high address
217	);
218
219	------------------------------------------
220	-- Constant: array of data widths for each target address range
221	------------------------------------------
222	constant USER_DWIDTH : integer := 32;
223
224	constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
225	(
226	0 => USER_DWIDTH -- user logic data width
227	);
228
229	------------------------------------------
230	-- Constant: array of desired number of chip enables for each address range
231	------------------------------------------
232	constant USER_NUM_CE : integer := 4;
233
234	constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
235	(
236	0 => pad_power2(USER_NUM_CE) -- user logic number of CEs
237	);
238
239	------------------------------------------
240	-- Constant: array of unique properties for each address range
241	------------------------------------------
242	constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE :=
243	(
244	0 => (others => 0) -- user logic slave space dependent properties (none defined)
245	);
246
247	------------------------------------------
248	-- Constant: pipeline mode
249	-- 1 = include OPB-In pipeline registers
250	-- 2 = include IP pipeline registers
251	-- 3 = include OPB-In and IP pipeline registers
252	-- 4 = include OPB-Out pipeline registers
253	-- 5 = include OPB-In and OPB-Out pipeline registers
254	-- 6 = include IP and OPB-Out pipeline registers
255	-- 7 = include OPB-In, IP, and OPB-Out pipeline registers
256	-- Note:
257	-- only mode 4, 5, 7 are supported for this release
258	------------------------------------------
259	constant PIPELINE_MODEL : integer := 5;
260
261	------------------------------------------
262	-- Constant: user core ID code
263	------------------------------------------
264	constant DEV_BLK_ID : integer := 0;
265
266	------------------------------------------
267	-- Constant: enable MIR/Reset register
268	------------------------------------------
269	constant DEV_MIR_ENABLE : integer := 0;
270
271	------------------------------------------
272	-- Constant: array of IP interrupt mode
273	-- 1 = Active-high interrupt condition
274	-- 2 = Active-low interrupt condition
275	-- 3 = Active-high pulse interrupt event
276	-- 4 = Active-low pulse interrupt event
277	-- 5 = Positive-edge interrupt event
278	-- 6 = Negative-edge interrupt event
279	------------------------------------------
280	constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
281	(
282	0 => 0 -- not used
283	);
284
285	------------------------------------------
286	-- Constant: enable device burst
287	------------------------------------------
288	constant DEV_BURST_ENABLE : integer := 0;
289
290	------------------------------------------
291	-- Constant: include address counter for burst transfers
292	------------------------------------------
293	constant INCLUDE_ADDR_CNTR : integer := 0;
294
295	------------------------------------------
296	-- Constant: include write buffer that decouples OPB and IPIC write transactions
297	------------------------------------------
298	constant INCLUDE_WR_BUF : integer := 0;
299
300	------------------------------------------
301	-- Constant: index for CS/CE
302	------------------------------------------
303	constant USER00_CS_INDEX : integer := get_id_index(ARD_ID_ARRAY, USER_00);
304
305	constant USER00_CE_INDEX : integer := calc_start_ce_index(ARD_NUM_CE_ARRAY, USER00_CS_INDEX);
306
307	------------------------------------------
308	-- IP Interconnect (IPIC) signal declarations -- do not delete
309	-- prefix 'i' stands for IPIF while prefix 'u' stands for user logic
310	-- typically user logic will be hooked up to IPIF directly via i<sig>
311	-- unless signal slicing and muxing are needed via u<sig>
312	------------------------------------------
313	signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
314	signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
315	signal iBus2IP_Data : std_logic_vector(0 to C_OPB_DWIDTH-1);
316	signal iBus2IP_BE : std_logic_vector(0 to C_OPB_DWIDTH/8-1);
317	signal iIP2Bus_Data : std_logic_vector(0 to C_OPB_DWIDTH-1) := (others => '0');
318	signal iIP2Bus_Ack : std_logic := '0';
319	signal iIP2Bus_Error : std_logic := '0';
320	signal iIP2Bus_Retry : std_logic := '0';
321	signal iIP2Bus_ToutSup : std_logic := '0';
322	signal ZERO_IP2Bus_PostedWrInh : std_logic_vector(0 to ARD_ID_ARRAY'length-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
323	signal ZERO_IP2RFIFO_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_RDFIFO_DATA))-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
324	signal ZERO_WFIFO2IP_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_WRFIFO_DATA))-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
325	signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
326	signal iBus2IP_Clk : std_logic;
327	signal iBus2IP_Reset : std_logic;
328	signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1);
329	signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1);
330	signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1);
331	signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1);
332	signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1);
333
334	------------------------------------------
335	-- Component declaration for verilog user logic
336	------------------------------------------
337	component user_logic is
338	generic
339	(
340	-- ADD USER GENERICS BELOW THIS LINE ---------------
341	--USER generics added here
342	-- ADD USER GENERICS ABOVE THIS LINE ---------------
343
344	-- DO NOT EDIT BELOW THIS LINE ---------------------
345	-- Bus protocol parameters, do not add to or delete
346	C_DWIDTH : integer := 32;
347	C_NUM_CE : integer := 4
348	-- DO NOT EDIT ABOVE THIS LINE ---------------------
349	);
350	port
351	(
352	-- ADD USER PORTS BELOW THIS LINE ------------------
353	--USER ports added here
354
355	Radio1_SHDN : out std_logic;
356	Radio1_TxEn : out std_logic;
357	Radio1_RxEn : out std_logic;
358	Radio1_RxHP : out std_logic;
359	Radio1_LD : in std_logic;
360	Radio1_24PA : out std_logic;
361	Radio1_5PA : out std_logic;
362	Radio1_ANTSW : out std_logic_vector(0 to 1);
363	Radio1_LED : out std_logic_vector(0 to 2);
364	Radio2_SHDN : out std_logic;
365	Radio2_TxEn : out std_logic;
366	Radio2_RxEn : out std_logic;
367	Radio2_RxHP : out std_logic;
368	Radio2_LD : in std_logic;
369	Radio2_24PA : out std_logic;
370	Radio2_5PA : out std_logic;
371	Radio2_ANTSW : out std_logic_vector(0 to 1);
372	Radio2_LED : out std_logic_vector(0 to 2);
373	Radio3_SHDN : out std_logic;
374	Radio3_TxEn : out std_logic;
375	Radio3_RxEn : out std_logic;
376	Radio3_RxHP : out std_logic;
377	Radio3_LD : in std_logic;
378	Radio3_24PA : out std_logic;
379	Radio3_5PA : out std_logic;
380	Radio3_ANTSW : out std_logic_vector(0 to 1);
381	Radio3_LED : out std_logic_vector(0 to 2);
382	Radio4_SHDN : out std_logic;
383	Radio4_TxEn : out std_logic;
384	Radio4_RxEn : out std_logic;
385	Radio4_RxHP : out std_logic;
386	Radio4_LD : in std_logic;
387	Radio4_24PA : out std_logic;
388	Radio4_5PA : out std_logic;
389	Radio4_ANTSW : out std_logic_vector(0 to 1);
390	Radio4_LED : out std_logic_vector(0 to 2);
391
392
393	-- ADD USER PORTS ABOVE THIS LINE ------------------
394
395	-- DO NOT EDIT BELOW THIS LINE ---------------------
396	-- Bus protocol ports, do not add to or delete
397	Bus2IP_Clk : in std_logic;
398	Bus2IP_Reset : in std_logic;
399	Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
400	Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
401	Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1);
402	Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1);
403	IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
404	IP2Bus_Ack : out std_logic;
405	IP2Bus_Retry : out std_logic;
406	IP2Bus_Error : out std_logic;
407	IP2Bus_ToutSup : out std_logic
408	-- DO NOT EDIT ABOVE THIS LINE ---------------------
409	);
410	end component user_logic;
411
412	begin
413
414	------------------------------------------
415	-- instantiate the OPB IPIF
416	------------------------------------------
417	OPB_IPIF_I : entity opb_ipif_v3_01_a.opb_ipif
418	generic map
419	(
420	C_ARD_ID_ARRAY => ARD_ID_ARRAY,
421	C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
422	C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY,
423	C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
424	C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY,
425	C_PIPELINE_MODEL => PIPELINE_MODEL,
426	C_DEV_BLK_ID => DEV_BLK_ID,
427	C_DEV_MIR_ENABLE => DEV_MIR_ENABLE,
428	C_OPB_AWIDTH => C_OPB_AWIDTH,
429	C_OPB_DWIDTH => C_OPB_DWIDTH,
430	C_FAMILY => C_FAMILY,
431	C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
432	C_DEV_BURST_ENABLE => DEV_BURST_ENABLE,
433	C_INCLUDE_ADDR_CNTR => INCLUDE_ADDR_CNTR,
434	C_INCLUDE_WR_BUF => INCLUDE_WR_BUF
435	)
436	port map
437	(
438	OPB_select => OPB_select,
439	OPB_DBus => OPB_DBus,
440	OPB_ABus => OPB_ABus,
441	OPB_BE => OPB_BE,
442	OPB_RNW => OPB_RNW,
443	OPB_seqAddr => OPB_seqAddr,
444	Sln_DBus => Sl_DBus,
445	Sln_xferAck => Sl_xferAck,
446	Sln_errAck => Sl_errAck,
447	Sln_retry => Sl_retry,
448	Sln_toutSup => Sl_toutSup,
449	Bus2IP_CS => open,
450	Bus2IP_CE => open,
451	Bus2IP_RdCE => iBus2IP_RdCE,
452	Bus2IP_WrCE => iBus2IP_WrCE,
453	Bus2IP_Data => iBus2IP_Data,
454	Bus2IP_Addr => open,
455	Bus2IP_AddrValid => open,
456	Bus2IP_BE => iBus2IP_BE,
457	Bus2IP_RNW => open,
458	Bus2IP_Burst => open,
459	IP2Bus_Data => iIP2Bus_Data,
460	IP2Bus_Ack => iIP2Bus_Ack,
461	IP2Bus_AddrAck => '0',
462	IP2Bus_Error => iIP2Bus_Error,
463	IP2Bus_Retry => iIP2Bus_Retry,
464	IP2Bus_ToutSup => iIP2Bus_ToutSup,
465	IP2Bus_PostedWrInh => ZERO_IP2Bus_PostedWrInh,
466	IP2RFIFO_Data => ZERO_IP2RFIFO_Data,
467	IP2RFIFO_WrMark => '0',
468	IP2RFIFO_WrRelease => '0',
469	IP2RFIFO_WrReq => '0',
470	IP2RFIFO_WrRestore => '0',
471	RFIFO2IP_AlmostFull => open,
472	RFIFO2IP_Full => open,
473	RFIFO2IP_Vacancy => open,
474	RFIFO2IP_WrAck => open,
475	IP2WFIFO_RdMark => '0',
476	IP2WFIFO_RdRelease => '0',
477	IP2WFIFO_RdReq => '0',
478	IP2WFIFO_RdRestore => '0',
479	WFIFO2IP_AlmostEmpty => open,
480	WFIFO2IP_Data => ZERO_WFIFO2IP_Data,
481	WFIFO2IP_Empty => open,
482	WFIFO2IP_Occupancy => open,
483	WFIFO2IP_RdAck => open,
484	IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent,
485	IP2INTC_Irpt => open,
486	Freeze => '0',
487	Bus2IP_Freeze => open,
488	OPB_Clk => OPB_Clk,
489	Bus2IP_Clk => iBus2IP_Clk,
490	IP2Bus_Clk => '0',
491	Reset => OPB_Rst,
492	Bus2IP_Reset => iBus2IP_Reset
493	);
494
495	------------------------------------------
496	-- instantiate the User Logic
497	------------------------------------------
498	USER_LOGIC_I : component user_logic
499	generic map
500	(
501	-- MAP USER GENERICS BELOW THIS LINE ---------------
502	--USER generics mapped here
503	-- MAP USER GENERICS ABOVE THIS LINE ---------------
504
505	C_DWIDTH => USER_DWIDTH,
506	C_NUM_CE => USER_NUM_CE
507	)
508	port map
509	(
510	-- MAP USER PORTS BELOW THIS LINE ------------------
511	--USER ports mapped here
512
513	Radio1_SHDN => radio1_shdn,
514	Radio1_TxEn => radio1_txen,
515	Radio1_RxEn => radio1_rxen,
516	Radio1_RxHP => radio1_rxhp,
517	Radio1_LD => radio1_ld,
518	Radio1_24PA => radio1_24pa,
519	Radio1_5PA => radio1_5pa,
520	Radio1_ANTSW => radio1_antsw,
521	Radio1_LED => radio1_led,
522	Radio2_SHDN => radio2_shdn,
523	Radio2_TxEn => radio2_txen,
524	Radio2_RxEn => radio2_rxen,
525	Radio2_RxHP => radio2_rxhp,
526	Radio2_LD => radio2_ld,
527	Radio2_24PA => radio2_24pa,
528	Radio2_5PA => radio2_5pa,
529	Radio2_ANTSW => radio2_antsw,
530	Radio2_LED => radio2_led,
531	Radio3_SHDN => radio3_shdn,
532	Radio3_TxEn => radio3_txen,
533	Radio3_RxEn => radio3_rxen,
534	Radio3_RxHP => radio3_rxhp,
535	Radio3_LD => radio3_ld,
536	Radio3_24PA => radio3_24pa,
537	Radio3_5PA => radio3_5pa,
538	Radio3_ANTSW => radio3_antsw,
539	Radio3_LED => radio3_led,
540	Radio4_SHDN => radio4_shdn,
541	Radio4_TxEn => radio4_txen,
542	Radio4_RxEn => radio4_rxen,
543	Radio4_RxHP => radio4_rxhp,
544	Radio4_LD => radio4_ld,
545	Radio4_24PA => radio4_24pa,
546	Radio4_5PA => radio4_5pa,
547	Radio4_ANTSW => radio4_antsw,
548	Radio4_LED => radio4_led,
549
550
551	-- MAP USER PORTS ABOVE THIS LINE ------------------
552
553	Bus2IP_Clk => iBus2IP_Clk,
554	Bus2IP_Reset => iBus2IP_Reset,
555	Bus2IP_Data => uBus2IP_Data,
556	Bus2IP_BE => uBus2IP_BE,
557	Bus2IP_RdCE => uBus2IP_RdCE,
558	Bus2IP_WrCE => uBus2IP_WrCE,
559	IP2Bus_Data => uIP2Bus_Data,
560	IP2Bus_Ack => iIP2Bus_Ack,
561	IP2Bus_Retry => iIP2Bus_Retry,
562	IP2Bus_Error => iIP2Bus_Error,
563	IP2Bus_ToutSup => iIP2Bus_ToutSup
564	);
565
566	------------------------------------------
567	-- hooking up signal slicing
568	------------------------------------------
569	uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1);
570	uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1);
571	uBus2IP_RdCE <= iBus2IP_RdCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1);
572	uBus2IP_WrCE <= iBus2IP_WrCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1);
573	iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data;
574
575	end IMP;

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