1 | |
---|
2 | ---------------------------------------------------------------------------- |
---|
3 | -- Design Analysis -- |
---|
4 | ---------------------------------------------------------------------------- |
---|
5 | Analyze pcore radio_controller ... |
---|
6 | |
---|
7 | |
---|
8 | ---------------------------------------------------------------------------- |
---|
9 | -- File Generation -- |
---|
10 | ---------------------------------------------------------------------------- |
---|
11 | Creating HDL source directory ... |
---|
12 | Generating top peripheral VHDL template ... |
---|
13 | Generating stub user logic Verilog template ... |
---|
14 | HDL templates successfully generated ... |
---|
15 | Creating data directory ... |
---|
16 | Generating XPS inteface files ... |
---|
17 | WARNING:HDLParsers:3497 - Ignoring Verilog File |
---|
18 | "C:\edk_user_repository\MyProcessorIPLib\pcores\radio_controller_v1_02_a\data |
---|
19 | /..\hdl\verilog\user_logic.v" |
---|
20 | Compiling vhdl file |
---|
21 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/inferred_lu |
---|
22 | t4.vhd" in Library proc_common_v2_00_a. |
---|
23 | Entity <inferred_lut4> compiled. |
---|
24 | Entity <inferred_lut4> (Architecture <implementation>) compiled. |
---|
25 | Compiling vhdl file |
---|
26 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_ |
---|
27 | bit.vhd" in Library proc_common_v2_00_a. |
---|
28 | Entity <pf_counter_bit> compiled. |
---|
29 | Entity <pf_counter_bit> (Architecture <implementation>) compiled. |
---|
30 | Compiling vhdl file |
---|
31 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder_bi |
---|
32 | t.vhd" in Library proc_common_v2_00_a. |
---|
33 | Entity <pf_adder_bit> compiled. |
---|
34 | Entity <pf_adder_bit> (Architecture <implementation>) compiled. |
---|
35 | Compiling vhdl file |
---|
36 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter. |
---|
37 | vhd" in Library proc_common_v2_00_a. |
---|
38 | Entity <pf_counter> compiled. |
---|
39 | Entity <pf_counter> (Architecture <implementation>) compiled. |
---|
40 | Compiling vhdl file |
---|
41 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_coun |
---|
42 | ter.vhd" in Library proc_common_v2_00_a. |
---|
43 | Entity <pf_occ_counter> compiled. |
---|
44 | Entity <pf_occ_counter> (Architecture <implementation>) compiled. |
---|
45 | Compiling vhdl file |
---|
46 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_coun |
---|
47 | ter_top.vhd" in Library proc_common_v2_00_a. |
---|
48 | Entity <pf_occ_counter_top> compiled. |
---|
49 | Entity <pf_occ_counter_top> (Architecture <implementation>) compiled. |
---|
50 | Compiling vhdl file |
---|
51 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_ |
---|
52 | top.vhd" in Library proc_common_v2_00_a. |
---|
53 | Entity <pf_counter_top> compiled. |
---|
54 | Entity <pf_counter_top> (Architecture <implementation>) compiled. |
---|
55 | Compiling vhdl file |
---|
56 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder.vh |
---|
57 | d" in Library proc_common_v2_00_a. |
---|
58 | Entity <pf_adder> compiled. |
---|
59 | Entity <pf_adder> (Architecture <implementation>) compiled. |
---|
60 | Compiling vhdl file |
---|
61 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/pf_dly1_mux.vhd |
---|
62 | " in Library wrpfifo_v1_01_b. |
---|
63 | Entity <pf_dly1_mux> compiled. |
---|
64 | Entity <pf_dly1_mux> (Architecture <implementation>) compiled. |
---|
65 | Compiling vhdl file |
---|
66 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/proc_common |
---|
67 | _pkg.vhd" in Library proc_common_v2_00_a. |
---|
68 | Package <proc_common_pkg> compiled. |
---|
69 | Package body <proc_common_pkg> compiled. |
---|
70 | Compiling vhdl file |
---|
71 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter_bit |
---|
72 | .vhd" in Library proc_common_v2_00_a. |
---|
73 | Entity <counter_bit> compiled. |
---|
74 | Entity <counter_bit> (Architecture <imp>) compiled. |
---|
75 | Compiling vhdl file |
---|
76 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/ipif_control_wr |
---|
77 | .vhd" in Library wrpfifo_v1_01_b. |
---|
78 | Entity <ipif_control_wr> compiled. |
---|
79 | Entity <ipif_control_wr> (Architecture <implementation>) compiled. |
---|
80 | Compiling vhdl file |
---|
81 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_dp_cntl |
---|
82 | .vhd" in Library wrpfifo_v1_01_b. |
---|
83 | Entity <wrpfifo_dp_cntl> compiled. |
---|
84 | Entity <wrpfifo_dp_cntl> (Architecture <implementation>) compiled. |
---|
85 | Compiling vhdl file |
---|
86 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_dpram_se |
---|
87 | lect.vhd" in Library proc_common_v2_00_a. |
---|
88 | Entity <pf_dpram_select> compiled. |
---|
89 | Entity <pf_dpram_select> (Architecture <implementation>) compiled. |
---|
90 | Compiling vhdl file |
---|
91 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl16_fifo. |
---|
92 | vhd" in Library proc_common_v2_00_a. |
---|
93 | Entity <srl16_fifo> compiled. |
---|
94 | Entity <srl16_fifo> (Architecture <implementation>) compiled. |
---|
95 | Compiling vhdl file |
---|
96 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/ipif_control_rd |
---|
97 | .vhd" in Library rdpfifo_v1_01_b. |
---|
98 | Entity <ipif_control_rd> compiled. |
---|
99 | Entity <ipif_control_rd> (Architecture <implementation>) compiled. |
---|
100 | Compiling vhdl file |
---|
101 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_dp_cntl |
---|
102 | .vhd" in Library rdpfifo_v1_01_b. |
---|
103 | Entity <rdpfifo_dp_cntl> compiled. |
---|
104 | Entity <rdpfifo_dp_cntl> (Architecture <implementation>) compiled. |
---|
105 | Compiling vhdl file |
---|
106 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_pkg.vh |
---|
107 | d" in Library proc_common_v2_00_a. |
---|
108 | Package <ipif_pkg> compiled. |
---|
109 | Package body <ipif_pkg> compiled. |
---|
110 | Compiling vhdl file |
---|
111 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_a/hdl/vhdl/srl_fifo3.vhd" |
---|
112 | in Library opb_ipif_v3_01_a. |
---|
113 | Entity <srl_fifo3> compiled. |
---|
114 | Entity <srl_fifo3> (Architecture <imp>) compiled. |
---|
115 | Compiling vhdl file |
---|
116 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter.vhd |
---|
117 | " in Library proc_common_v2_00_a. |
---|
118 | Entity <Counter> compiled. |
---|
119 | Entity <Counter> (Architecture <imp>) compiled. |
---|
120 | Compiling vhdl file |
---|
121 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_a/hdl/vhdl/opb_flex_addr_ |
---|
122 | cntr.vhd" in Library opb_ipif_v3_01_a. |
---|
123 | Entity <opb_flex_addr_cntr> compiled. |
---|
124 | Entity <opb_flex_addr_cntr> (Architecture <implementation>) compiled. |
---|
125 | Compiling vhdl file |
---|
126 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/direct_path |
---|
127 | _cntr_ai.vhd" in Library proc_common_v2_00_a. |
---|
128 | Entity <direct_path_cntr_ai> compiled. |
---|
129 | Entity <direct_path_cntr_ai> (Architecture <imp>) compiled. |
---|
130 | Compiling vhdl file |
---|
131 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd |
---|
132 | " in Library proc_common_v2_00_a. |
---|
133 | Entity <pselect> compiled. |
---|
134 | Entity <pselect> (Architecture <imp>) compiled. |
---|
135 | Compiling vhdl file |
---|
136 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_a/hdl/vhdl/opb_be_gen.vhd |
---|
137 | " in Library opb_ipif_v3_01_a. |
---|
138 | Entity <opb_be_gen> compiled. |
---|
139 | Entity <opb_be_gen> (Architecture <implementation>) compiled. |
---|
140 | Compiling vhdl file |
---|
141 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_a/hdl/vhdl/brst_addr_cntr |
---|
142 | .vhd" in Library opb_ipif_v3_01_a. |
---|
143 | Entity <brst_addr_cntr> compiled. |
---|
144 | Entity <brst_addr_cntr> (Architecture <implementation>) compiled. |
---|
145 | Compiling vhdl file |
---|
146 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_a/hdl/vhdl/brst_addr_cntr |
---|
147 | _reg.vhd" in Library opb_ipif_v3_01_a. |
---|
148 | Entity <brst_addr_cntr_reg> compiled. |
---|
149 | Entity <brst_addr_cntr_reg> (Architecture <implementation>) compiled. |
---|
150 | Compiling vhdl file |
---|
151 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_a/hdl/vhdl/write_buffer.v |
---|
152 | hd" in Library opb_ipif_v3_01_a. |
---|
153 | Entity <write_buffer> compiled. |
---|
154 | Entity <write_buffer> (Architecture <implementation>) compiled. |
---|
155 | Compiling vhdl file |
---|
156 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_muxcy.vh |
---|
157 | d" in Library proc_common_v2_00_a. |
---|
158 | Entity <or_muxcy> compiled. |
---|
159 | Entity <or_muxcy> (Architecture <implementation>) compiled. |
---|
160 | Compiling vhdl file |
---|
161 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_steer. |
---|
162 | vhd" in Library proc_common_v2_00_a. |
---|
163 | Entity <IPIF_Steer> compiled. |
---|
164 | Entity <IPIF_Steer> (Architecture <IMP>) compiled. |
---|
165 | Compiling vhdl file |
---|
166 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_a/hdl/vhdl/reset_mir.vhd" |
---|
167 | in Library opb_ipif_v3_01_a. |
---|
168 | Entity <reset_mir> compiled. |
---|
169 | Entity <reset_mir> (Architecture <implementation>) compiled. |
---|
170 | Compiling vhdl file |
---|
171 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/interrupt_control_v1_00_a/hdl/vhdl/inter |
---|
172 | rupt_control.vhd" in Library interrupt_control_v1_00_a. |
---|
173 | Entity <interrupt_control> compiled. |
---|
174 | Entity <interrupt_control> (Architecture <implementation>) compiled. |
---|
175 | Compiling vhdl file |
---|
176 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_top.vhd |
---|
177 | " in Library rdpfifo_v1_01_b. |
---|
178 | Entity <rdpfifo_top> compiled. |
---|
179 | Entity <rdpfifo_top> (Architecture <implementation>) compiled. |
---|
180 | Compiling vhdl file |
---|
181 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_top.vhd |
---|
182 | " in Library wrpfifo_v1_01_b. |
---|
183 | Entity <wrpfifo_top> compiled. |
---|
184 | Entity <wrpfifo_top> (Architecture <implementation>) compiled. |
---|
185 | Compiling vhdl file |
---|
186 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/family.vhd" |
---|
187 | in Library proc_common_v2_00_a. |
---|
188 | Package <family> compiled. |
---|
189 | Package body <family> compiled. |
---|
190 | Compiling vhdl file |
---|
191 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_a/hdl/vhdl/opb_bam.vhd" |
---|
192 | in Library opb_ipif_v3_01_a. |
---|
193 | Entity <opb_bam> compiled. |
---|
194 | Entity <opb_bam> (Architecture <implementation>) compiled. |
---|
195 | Compiling vhdl file |
---|
196 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_a/hdl/vhdl/opb_ipif.vhd" |
---|
197 | in Library opb_ipif_v3_01_a. |
---|
198 | Entity <opb_ipif> compiled. |
---|
199 | Entity <opb_ipif> (Architecture <imp>) compiled. |
---|
200 | Compiling vhdl file |
---|
201 | "C:/edk_user_repository/MyProcessorIPLib/pcores/radio_controller_v1_02_a/data/.. |
---|
202 | /hdl/vhdl/radio_controller.vhd" in Library radio_controller_v1_02_a. |
---|
203 | Entity <radio_controller> compiled. |
---|
204 | Entity <radio_controller> (Architecture <IMP>) compiled. |
---|
205 | Compiling vhdl file |
---|
206 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/down_counte |
---|
207 | r.vhd" in Library proc_common_v2_00_a. |
---|
208 | Entity <down_counter> compiled. |
---|
209 | Entity <down_counter> (Architecture <simulation>) compiled. |
---|
210 | Compiling vhdl file |
---|
211 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/mux_onehot. |
---|
212 | vhd" in Library proc_common_v2_00_a. |
---|
213 | Entity <mux_onehot> compiled. |
---|
214 | Entity <mux_onehot> (Architecture <imp>) compiled. |
---|
215 | Compiling vhdl file |
---|
216 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ld_arith_re |
---|
217 | g.vhd" in Library proc_common_v2_00_a. |
---|
218 | Entity <ld_arith_reg> compiled. |
---|
219 | Entity <ld_arith_reg> (Architecture <imp>) compiled. |
---|
220 | Compiling vhdl file |
---|
221 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/valid_be.vh |
---|
222 | d" in Library proc_common_v2_00_a. |
---|
223 | Entity <valid_be> compiled. |
---|
224 | Entity <valid_be> (Architecture <implementation>) compiled. |
---|
225 | Compiling vhdl file |
---|
226 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl_fifo2.v |
---|
227 | hd" in Library proc_common_v2_00_a. |
---|
228 | Entity <srl_fifo2> compiled. |
---|
229 | Entity <srl_fifo2> (Architecture <imp>) compiled. |
---|
230 | Compiling vhdl file |
---|
231 | "C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_gate.vhd |
---|
232 | " in Library proc_common_v2_00_a. |
---|
233 | Entity <or_gate> compiled. |
---|
234 | Entity <or_gate> (Architecture <imp>) compiled. |
---|
235 | |
---|
236 | |
---|
237 | Analyzing HDL attributes ... |
---|
238 | INFO:MDT - IPTYPE set to value : PERIPHERAL |
---|
239 | INFO:MDT - IMP_NETLIST set to value : TRUE |
---|
240 | INFO:MDT - HDL set to value : VHDL |
---|
241 | XPS interface files successfully generated ... |
---|
242 | Creating development directory ... |
---|
243 | Generating command option file ... |
---|
244 | Generating readme file ... |
---|
245 | Development misc files successfully generated ... |
---|
246 | Creating projnav directory ... |
---|
247 | Generating ProjNav support files ... |
---|
248 | ProjNav support files successfully generated ... |
---|
249 | Creating synthesis directory ... |
---|
250 | Generating XST synthesis support files ... |
---|
251 | XST synthesis support files successfully generated ... |
---|
252 | No BFM simulation files will be generated at this time ... |
---|
253 | Creating software driver data directory ... |
---|
254 | Generating software driver XPS interface (mdd/tcl) files ... |
---|
255 | Software driver data definition file (.mdd) successfully generated ... |
---|
256 | Software driver data generation file (.tcl) successfully generated ... |
---|
257 | Creating software driver src directory ... |
---|
258 | Generating software driver template files ... |
---|
259 | Software driver compile file (Makefile) successfully generated ... |
---|
260 | output user slave register(s) offset to software driver header ... |
---|
261 | Software driver header file (.h) successfully generated ... |
---|
262 | Software driver source file (.c) successfully generated ... |
---|
263 | Software driver SelfTest file (.c) successfully generated ... |
---|
264 | Software driver template files successfully generated ... |
---|
265 | |
---|
266 | ---------------------------------------------------------------------------- |
---|
267 | -- Final Report -- |
---|
268 | ---------------------------------------------------------------------------- |
---|
269 | Thank you for using Create and Import Peripheral Wizard! |
---|
270 | |
---|
271 | Peripheral summary |
---|
272 | |
---|
273 | top name : radio_controller |
---|
274 | version : 1.02.a |
---|
275 | type : OPB slave |
---|
276 | features : slave attachement |
---|
277 | user s/w registers |
---|
278 | |
---|
279 | Address Block Summary |
---|
280 | |
---|
281 | user logic slv : C_BASEADDR + 0x00000000 |
---|
282 | : C_BASEADDR + 0x000000FF |
---|
283 | |
---|
284 | File Summary |
---|
285 | |
---|
286 | - HDL source - |
---|
287 | C:\edk_user_repository\MyProcessorIPLib/pcores/radio_controller_v1_02_a/hdl |
---|
288 | top entity : vhdl/radio_controller.vhd |
---|
289 | user logic : verilog/user_logic.v |
---|
290 | |
---|
291 | - XPS interface - |
---|
292 | C:\edk_user_repository\MyProcessorIPLib/pcores/radio_controller_v1_02_a/data |
---|
293 | mpd : radio_controller_v2_1_0.mpd |
---|
294 | pao : radio_controller_v2_1_0.pao |
---|
295 | |
---|
296 | - ISE project - |
---|
297 | C:\edk_user_repository\MyProcessorIPLib/pcores/radio_controller_v1_02_a/devl/pro |
---|
298 | jnav |
---|
299 | ise project : radio_controller.npl |
---|
300 | cli command : radio_controller.cli |
---|
301 | |
---|
302 | |
---|
303 | - XST synthesis - |
---|
304 | C:\edk_user_repository\MyProcessorIPLib/pcores/radio_controller_v1_02_a/devl/syn |
---|
305 | thesis |
---|
306 | xst script : radio_controller_xst.scr |
---|
307 | xst project : radio_controller_xst.prj |
---|
308 | |
---|
309 | - Misc file - |
---|
310 | C:\edk_user_repository\MyProcessorIPLib/pcores/radio_controller_v1_02_a/devl |
---|
311 | help : README.txt |
---|
312 | option : ipwiz.opt |
---|
313 | log : ipwiz.log |
---|
314 | |
---|
315 | - Driver source - |
---|
316 | C:\edk_user_repository\MyProcessorIPLib/drivers/radio_controller_v1_02_a/src |
---|
317 | makefile : Makefile |
---|
318 | header : radio_controller.h |
---|
319 | source : radio_controller.c |
---|
320 | selftest : radio_controller_selftest.c |
---|
321 | |
---|
322 | - Driver interface - |
---|
323 | C:\edk_user_repository\MyProcessorIPLib/drivers/radio_controller_v1_02_a/data |
---|
324 | mdd : radio_controller_v2_1_0.mdd |
---|
325 | tcl : radio_controller_v2_1_0.tcl |
---|
326 | |
---|
327 | |
---|