source: PlatformSupport/Deprecated/pcores/radio_controller_v1_02_a/devl/projnav/radio_controller.cli

Last change on this file was 80, checked in by sgupta, 19 years ago

This is the new radio controller. It has support for more RSSI, DAC and ADC parameters.
File size: 10.7 KB
Line 
1NewProject(C:\edk_user_repository\MyProcessorIPLib\pcores\radio_controller_v1_02_a\devl\projnav\radio_controller.npl)
2SetProperty(Top-Level Module Type, HDL)
3SetProperty(Synthesis Tool, XST (VHDL/Verilog))
4SetProperty(Simulator, ModelSim)
5SetPreference(PathType, Absolute)
6AddLibrary(radio_controller_v1_02_a, C:\edk_user_repository\MyProcessorIPLib\pcores, TRUE)
7AddSource(C:\edk_user_repository\MyProcessorIPLib\pcores\radio_controller_v1_02_a\hdl\vhdl\radio_controller.vhd, VHDL Design File)
8MoveToLibrary(C:\edk_user_repository\MyProcessorIPLib\pcores\radio_controller_v1_02_a\hdl\vhdl\radio_controller.vhd, radio_controller_v1_02_a)
9AddSource(C:\edk_user_repository\MyProcessorIPLib\pcores\radio_controller_v1_02_a\hdl\verilog\user_logic.v, Verilog Design File)
10AddLibrary(proc_common_v2_00_a, C:\EDK\\hw\XilinxProcessorIPLib\pcores, TRUE)
11AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\proc_common_pkg.vhd, VHDL Design File)
12MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\proc_common_pkg.vhd, proc_common_v2_00_a)
13AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\family.vhd, VHDL Design File)
14MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\family.vhd, proc_common_v2_00_a)
15AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\or_muxcy.vhd, VHDL Design File)
16MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\or_muxcy.vhd, proc_common_v2_00_a)
17AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\or_gate.vhd, VHDL Design File)
18MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\or_gate.vhd, proc_common_v2_00_a)
19AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\counter_bit.vhd, VHDL Design File)
20MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\counter_bit.vhd, proc_common_v2_00_a)
21AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\counter.vhd, VHDL Design File)
22MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\counter.vhd, proc_common_v2_00_a)
23AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\inferred_lut4.vhd, VHDL Design File)
24MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\inferred_lut4.vhd, proc_common_v2_00_a)
25AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\srl_fifo2.vhd, VHDL Design File)
26MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\srl_fifo2.vhd, proc_common_v2_00_a)
27AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_counter_bit.vhd, VHDL Design File)
28MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_counter_bit.vhd, proc_common_v2_00_a)
29AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_counter.vhd, VHDL Design File)
30MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_counter.vhd, proc_common_v2_00_a)
31AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_counter_top.vhd, VHDL Design File)
32MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_counter_top.vhd, proc_common_v2_00_a)
33AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_occ_counter.vhd, VHDL Design File)
34MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_occ_counter.vhd, proc_common_v2_00_a)
35AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_occ_counter_top.vhd, VHDL Design File)
36MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_occ_counter_top.vhd, proc_common_v2_00_a)
37AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_adder_bit.vhd, VHDL Design File)
38MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_adder_bit.vhd, proc_common_v2_00_a)
39AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_adder.vhd, VHDL Design File)
40MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_adder.vhd, proc_common_v2_00_a)
41AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_dpram_select.vhd, VHDL Design File)
42MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_dpram_select.vhd, proc_common_v2_00_a)
43AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\srl16_fifo.vhd, VHDL Design File)
44MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\srl16_fifo.vhd, proc_common_v2_00_a)
45AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pselect.vhd, VHDL Design File)
46MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pselect.vhd, proc_common_v2_00_a)
47AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\valid_be.vhd, VHDL Design File)
48MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\valid_be.vhd, proc_common_v2_00_a)
49AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\ld_arith_reg.vhd, VHDL Design File)
50MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\ld_arith_reg.vhd, proc_common_v2_00_a)
51AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\mux_onehot.vhd, VHDL Design File)
52MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\mux_onehot.vhd, proc_common_v2_00_a)
53AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\down_counter.vhd, VHDL Design File)
54MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\down_counter.vhd, proc_common_v2_00_a)
55AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\ipif_pkg.vhd, VHDL Design File)
56MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\ipif_pkg.vhd, proc_common_v2_00_a)
57AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\ipif_steer.vhd, VHDL Design File)
58MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\ipif_steer.vhd, proc_common_v2_00_a)
59AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\direct_path_cntr_ai.vhd, VHDL Design File)
60MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\direct_path_cntr_ai.vhd, proc_common_v2_00_a)
61AddLibrary(interrupt_control_v1_00_a, C:\EDK\\hw\XilinxProcessorIPLib\pcores, TRUE)
62AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\interrupt_control_v1_00_a\hdl\vhdl\interrupt_control.vhd, VHDL Design File)
63MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\interrupt_control_v1_00_a\hdl\vhdl\interrupt_control.vhd, interrupt_control_v1_00_a)
64AddLibrary(wrpfifo_v1_01_b, C:\EDK\\hw\XilinxProcessorIPLib\pcores, TRUE)
65AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\wrpfifo_v1_01_b\hdl\vhdl\pf_dly1_mux.vhd, VHDL Design File)
66MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\wrpfifo_v1_01_b\hdl\vhdl\pf_dly1_mux.vhd, wrpfifo_v1_01_b)
67AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\wrpfifo_v1_01_b\hdl\vhdl\ipif_control_wr.vhd, VHDL Design File)
68MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\wrpfifo_v1_01_b\hdl\vhdl\ipif_control_wr.vhd, wrpfifo_v1_01_b)
69AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\wrpfifo_v1_01_b\hdl\vhdl\wrpfifo_dp_cntl.vhd, VHDL Design File)
70MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\wrpfifo_v1_01_b\hdl\vhdl\wrpfifo_dp_cntl.vhd, wrpfifo_v1_01_b)
71AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\wrpfifo_v1_01_b\hdl\vhdl\wrpfifo_top.vhd, VHDL Design File)
72MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\wrpfifo_v1_01_b\hdl\vhdl\wrpfifo_top.vhd, wrpfifo_v1_01_b)
73AddLibrary(rdpfifo_v1_01_b, C:\EDK\\hw\XilinxProcessorIPLib\pcores, TRUE)
74AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\rdpfifo_v1_01_b\hdl\vhdl\ipif_control_rd.vhd, VHDL Design File)
75MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\rdpfifo_v1_01_b\hdl\vhdl\ipif_control_rd.vhd, rdpfifo_v1_01_b)
76AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\rdpfifo_v1_01_b\hdl\vhdl\rdpfifo_dp_cntl.vhd, VHDL Design File)
77MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\rdpfifo_v1_01_b\hdl\vhdl\rdpfifo_dp_cntl.vhd, rdpfifo_v1_01_b)
78AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\rdpfifo_v1_01_b\hdl\vhdl\rdpfifo_top.vhd, VHDL Design File)
79MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\rdpfifo_v1_01_b\hdl\vhdl\rdpfifo_top.vhd, rdpfifo_v1_01_b)
80AddLibrary(opb_ipif_v3_01_a, C:\EDK\\hw\XilinxProcessorIPLib\pcores, TRUE)
81AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\reset_mir.vhd, VHDL Design File)
82MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\reset_mir.vhd, opb_ipif_v3_01_a)
83AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\brst_addr_cntr.vhd, VHDL Design File)
84MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\brst_addr_cntr.vhd, opb_ipif_v3_01_a)
85AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\opb_flex_addr_cntr.vhd, VHDL Design File)
86MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\opb_flex_addr_cntr.vhd, opb_ipif_v3_01_a)
87AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\brst_addr_cntr_reg.vhd, VHDL Design File)
88MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\brst_addr_cntr_reg.vhd, opb_ipif_v3_01_a)
89AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\opb_be_gen.vhd, VHDL Design File)
90MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\opb_be_gen.vhd, opb_ipif_v3_01_a)
91AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\srl_fifo3.vhd, VHDL Design File)
92MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\srl_fifo3.vhd, opb_ipif_v3_01_a)
93AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\write_buffer.vhd, VHDL Design File)
94MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\write_buffer.vhd, opb_ipif_v3_01_a)
95AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\opb_bam.vhd, VHDL Design File)
96MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\opb_bam.vhd, opb_ipif_v3_01_a)
97AddSource(C:\EDK\\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\opb_ipif.vhd, VHDL Design File)
98MoveToLibrary(C:\EDK\\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\opb_ipif.vhd, opb_ipif_v3_01_a)
99CloseProject()
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