1 | //Register bit masks for reading |
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2 | #define RADIO_RSSI_ADC_D 0x3ff //Bits [9:0] |
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3 | #define RADIO_TX_DAC_RESET 0x400 //Bit 10 |
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4 | #define RADIO_TX_DAC_PLL_LOCK 0x800 //Bit 11 |
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5 | #define RADIO_RSSI_ADC_OTR 0x1000 //Bit 12 |
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6 | #define RADIO_DIPSW 0x1E000 //Bits [16:13] |
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7 | #define RADIO_ADC_RX_PWDNB 0x20000 //Bit 17 |
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8 | #define RADIO_ADC_RX_PWDNA 0x40000 //Bit 18 |
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9 | #define RADIO_ADC_RX_OTRB 0x80000 //Bit 19 |
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10 | #define RADIO_ADC_RX_OTRA 0x100000 //Bit 20 |
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11 | #define RADIO_ADC_RX_DFS 0x200000 //Bit 21 |
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12 | #define RADIO_ADC_RX_DCS 0x400000 //Bit 22 |
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13 | #define RADIO_ANTSW 0x1800000 //Bits [24:23] |
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14 | #define RADIO_5PA 0x2000000 //Bit 25 |
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15 | #define RADIO_24PA 0x4000000 //Bit 26 |
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16 | #define RADIO_LD 0x8000000 //Bit 27 |
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17 | #define RADIO_RXHP 0x10000000 //Bit 28 |
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18 | #define RADIO_RXEN 0x20000000 //Bit 29 |
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19 | #define RADIO_TXEN 0x40000000 //Bit 30 |
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20 | #define RADIO_SHDN 0x80000000 //Bit 31 |
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21 | |
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22 | //Register bit masks for writing |
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23 | #define RADIO_TX_DAC_RESET 0x400 //Bit 10 |
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24 | #define RSSI_ADC_SLEEP 0x10000 //Bit 16 |
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25 | #define RADIO_ADC_RX_PWDNB 0x20000 //Bit 17 |
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26 | #define RADIO_ADC_RX_PWDNA 0x40000 //Bit 18 |
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27 | #define RADIO_LED0 0x80000 //Bit 19 |
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28 | #define RADIO_LED1 0x100000 //Bit 20 |
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29 | #define RADIO_LED2 0x200000 //Bit 21 |
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30 | #define RADIO_ADC_RX_DCS 0x400000 //Bit 22 |
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31 | #define RADIO_ANTSW 0x1800000 //Bits [24:23] |
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32 | #define RADIO_5PA 0x2000000 //Bit 25 |
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33 | #define RADIO_24PA 0x4000000 //Bit 26 |
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34 | #define RADIO_RXHP 0x10000000 //Bit 28 |
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35 | #define RADIO_RXEN 0x20000000 //Bit 29 |
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36 | #define RADIO_TXEN 0x40000000 //Bit 30 |
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37 | #define RADIO_SHDN 0x80000000 //Bit 31 |
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