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user_logic.v

Last change on this file was 83, checked in by murphpo, 18 years ago
adding header for radio controller driver
File size: 20.2 KB

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1	//----------------------------------------------------------------------------
2	// user_logic.v - module
3	//----------------------------------------------------------------------------
4	//
5	// ***************************************************************************
6	// Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
7	//
8	// Xilinx, Inc.
9	// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
10	// AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
11	// SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
12	// OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
13	// APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
14	// THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
15	// AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
16	// FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
17	// WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
18	// IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
19	// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
20	// INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
21	// FOR A PARTICULAR PURPOSE.
22	//
23	// YOU MAY COPY AND MODIFY THESE FILES FOR YOUR OWN INTERNAL USE SOLELY
24	// WITH XILINX PROGRAMMABLE LOGIC DEVICES AND XILINX EDK SYSTEM OR
25	// CREATE IP MODULES SOLELY FOR XILINX PROGRAMMABLE LOGIC DEVICES AND
26	// XILINX EDK SYSTEM. NO RIGHTS ARE GRANTED TO DISTRIBUTE ANY FILES
27	// UNLESS THEY ARE DISTRIBUTED IN XILINX PROGRAMMABLE LOGIC DEVICES.
28	//
29	// ***************************************************************************
30	//
31	//----------------------------------------------------------------------------
32	// Filename: user_logic.v
33	// Version: 1.02.a
34	// Description: User logic module.
35	// Date: Mon Nov 21 15:11:06 2005 (by Create and Import Peripheral Wizard)
36	// Verilog Standard: Verilog-2001
37	//----------------------------------------------------------------------------
38	// Naming Conventions:
39	// active low signals: "*_n"
40	// clock signals: "clk", "clk_div#", "clk_#x"
41	// reset signals: "rst", "rst_n"
42	// generics: "C_*"
43	// user defined types: "*_TYPE"
44	// state machine next state: "*_ns"
45	// state machine current state: "*_cs"
46	// combinatorial signals: "*_com"
47	// pipelined or register delay signals: "*_d#"
48	// counter signals: "cnt"
49	// clock enable signals: "*_ce"
50	// internal version of output port: "*_i"
51	// device pins: "*_pin"
52	// ports: "- Names begin with Uppercase"
53	// processes: "*_PROCESS"
54	// component instantiations: "<ENTITY_>I_<#\|FUNC>"
55	//----------------------------------------------------------------------------
56
57	module user_logic
58	(
59	// -- ADD USER PORTS BELOW THIS LINE ---------------
60	// --USER ports added here
61
62	Radio1_SHDN,
63	Radio1_TxEn,
64	Radio1_RxEn,
65	Radio1_RxHP,
66	Radio1_LD,
67	Radio1_24PA,
68	Radio1_5PA,
69	Radio1_ANTSW,
70	Radio1_LED,
71	Radio1_ADC_RX_DCS,
72	Radio1_ADC_RX_DFS,
73	Radio1_ADC_RX_OTRA,
74	Radio1_ADC_RX_OTRB,
75	Radio1_ADC_RX_PWDNA,
76	Radio1_ADC_RX_PWDNB,
77	Radio1_DIPSW,
78	Radio1_RSSI_ADC_CLAMP,
79	Radio1_RSSI_ADC_HIZ,
80	Radio1_RSSI_ADC_OTR,
81	Radio1_RSSI_ADC_SLEEP,
82	Radio1_RSSI_ADC_D,
83	Radio1_TX_DAC_PLL_LOCK,
84	Radio1_TX_DAC_RESET,
85	Radio2_SHDN,
86	Radio2_TxEn,
87	Radio2_RxEn,
88	Radio2_RxHP,
89	Radio2_LD,
90	Radio2_24PA,
91	Radio2_5PA,
92	Radio2_ANTSW,
93	Radio2_LED,
94	Radio2_ADC_RX_DCS,
95	Radio2_ADC_RX_DFS,
96	Radio2_ADC_RX_OTRA,
97	Radio2_ADC_RX_OTRB,
98	Radio2_ADC_RX_PWDNA,
99	Radio2_ADC_RX_PWDNB,
100	Radio2_DIPSW,
101	Radio2_RSSI_ADC_CLAMP,
102	Radio2_RSSI_ADC_HIZ,
103	Radio2_RSSI_ADC_OTR,
104	Radio2_RSSI_ADC_SLEEP,
105	Radio2_RSSI_ADC_D,
106	Radio2_TX_DAC_PLL_LOCK,
107	Radio2_TX_DAC_RESET,
108	Radio3_SHDN,
109	Radio3_TxEn,
110	Radio3_RxEn,
111	Radio3_RxHP,
112	Radio3_LD,
113	Radio3_24PA,
114	Radio3_5PA,
115	Radio3_ANTSW,
116	Radio3_LED,
117	Radio3_ADC_RX_DCS,
118	Radio3_ADC_RX_DFS,
119	Radio3_ADC_RX_OTRA,
120	Radio3_ADC_RX_OTRB,
121	Radio3_ADC_RX_PWDNA,
122	Radio3_ADC_RX_PWDNB,
123	Radio3_DIPSW,
124	Radio3_RSSI_ADC_CLAMP,
125	Radio3_RSSI_ADC_HIZ,
126	Radio3_RSSI_ADC_OTR,
127	Radio3_RSSI_ADC_SLEEP,
128	Radio3_RSSI_ADC_D,
129	Radio3_TX_DAC_PLL_LOCK,
130	Radio3_TX_DAC_RESET,
131	Radio4_SHDN,
132	Radio4_TxEn,
133	Radio4_RxEn,
134	Radio4_RxHP,
135	Radio4_LD,
136	Radio4_24PA,
137	Radio4_5PA,
138	Radio4_ANTSW,
139	Radio4_LED,
140	Radio4_ADC_RX_DCS,
141	Radio4_ADC_RX_DFS,
142	Radio4_ADC_RX_OTRA,
143	Radio4_ADC_RX_OTRB,
144	Radio4_ADC_RX_PWDNA,
145	Radio4_ADC_RX_PWDNB,
146	Radio4_DIPSW,
147	Radio4_RSSI_ADC_CLAMP,
148	Radio4_RSSI_ADC_HIZ,
149	Radio4_RSSI_ADC_OTR,
150	Radio4_RSSI_ADC_SLEEP,
151	Radio4_RSSI_ADC_D,
152	Radio4_TX_DAC_PLL_LOCK,
153	Radio4_TX_DAC_RESET,
154
155
156	// -- ADD USER PORTS ABOVE THIS LINE ---------------
157
158	// -- DO NOT EDIT BELOW THIS LINE ------------------
159	// -- Bus protocol ports, do not add to or delete
160	Bus2IP_Clk, // Bus to IP clock
161	Bus2IP_Reset, // Bus to IP reset
162	Bus2IP_Data, // Bus to IP data bus for user logic
163	Bus2IP_BE, // Bus to IP byte enables for user logic
164	Bus2IP_RdCE, // Bus to IP read chip enable for user logic
165	Bus2IP_WrCE, // Bus to IP write chip enable for user logic
166	IP2Bus_Data, // IP to Bus data bus for user logic
167	IP2Bus_Ack, // IP to Bus acknowledgement
168	IP2Bus_Retry, // IP to Bus retry response
169	IP2Bus_Error, // IP to Bus error response
170	IP2Bus_ToutSup // IP to Bus timeout suppress
171	// -- DO NOT EDIT ABOVE THIS LINE ------------------
172	); // user_logic
173
174	// -- ADD USER PARAMETERS BELOW THIS LINE ------------
175	// --USER parameters added here
176	// -- ADD USER PARAMETERS ABOVE THIS LINE ------------
177
178	// -- DO NOT EDIT BELOW THIS LINE --------------------
179	// -- Bus protocol parameters, do not add to or delete
180	parameter C_DWIDTH = 32;
181	parameter C_NUM_CE = 4;
182	// -- DO NOT EDIT ABOVE THIS LINE --------------------
183
184	// -- ADD USER PORTS BELOW THIS LINE -----------------
185	// --USER ports added here
186
187	output Radio1_SHDN;
188	output Radio1_TxEn;
189	output Radio1_RxEn;
190	output Radio1_RxHP;
191	input Radio1_LD;
192	output Radio1_24PA;
193	output Radio1_5PA;
194	output [0 : 1] Radio1_ANTSW;
195	output [0 : 2] Radio1_LED;
196	output Radio1_ADC_RX_DCS;
197	output Radio1_ADC_RX_DFS;
198	input Radio1_ADC_RX_OTRA;
199	input Radio1_ADC_RX_OTRB;
200	output Radio1_ADC_RX_PWDNA;
201	output Radio1_ADC_RX_PWDNB;
202	input [0 : 3] Radio1_DIPSW;
203	output Radio1_RSSI_ADC_CLAMP;
204	output Radio1_RSSI_ADC_HIZ;
205	input Radio1_RSSI_ADC_OTR;
206	output Radio1_RSSI_ADC_SLEEP;
207	input [0 : 9] Radio1_RSSI_ADC_D;
208	input Radio1_TX_DAC_PLL_LOCK;
209	output Radio1_TX_DAC_RESET;
210	output Radio2_SHDN;
211	output Radio2_TxEn;
212	output Radio2_RxEn;
213	output Radio2_RxHP;
214	input Radio2_LD;
215	output Radio2_24PA;
216	output Radio2_5PA;
217	output [0 : 1] Radio2_ANTSW;
218	output [0 : 2] Radio2_LED;
219	output Radio2_ADC_RX_DCS;
220	output Radio2_ADC_RX_DFS;
221	input Radio2_ADC_RX_OTRA;
222	input Radio2_ADC_RX_OTRB;
223	output Radio2_ADC_RX_PWDNA;
224	output Radio2_ADC_RX_PWDNB;
225	input [0 : 3] Radio2_DIPSW;
226	output Radio2_RSSI_ADC_CLAMP;
227	output Radio2_RSSI_ADC_HIZ;
228	input Radio2_RSSI_ADC_OTR;
229	output Radio2_RSSI_ADC_SLEEP;
230	input [0 : 9] Radio2_RSSI_ADC_D;
231	input Radio2_TX_DAC_PLL_LOCK;
232	output Radio2_TX_DAC_RESET;
233	output Radio3_SHDN;
234	output Radio3_TxEn;
235	output Radio3_RxEn;
236	output Radio3_RxHP;
237	input Radio3_LD;
238	output Radio3_24PA;
239	output Radio3_5PA;
240	output [0 : 1] Radio3_ANTSW;
241	output [0 : 2] Radio3_LED;
242	output Radio3_ADC_RX_DCS;
243	output Radio3_ADC_RX_DFS;
244	input Radio3_ADC_RX_OTRA;
245	input Radio3_ADC_RX_OTRB;
246	output Radio3_ADC_RX_PWDNA;
247	output Radio3_ADC_RX_PWDNB;
248	input [0 : 3] Radio3_DIPSW;
249	output Radio3_RSSI_ADC_CLAMP;
250	output Radio3_RSSI_ADC_HIZ;
251	input Radio3_RSSI_ADC_OTR;
252	output Radio3_RSSI_ADC_SLEEP;
253	input [0 : 9] Radio3_RSSI_ADC_D;
254	input Radio3_TX_DAC_PLL_LOCK;
255	output Radio3_TX_DAC_RESET;
256	output Radio4_SHDN;
257	output Radio4_TxEn;
258	output Radio4_RxEn;
259	output Radio4_RxHP;
260	input Radio4_LD;
261	output Radio4_24PA;
262	output Radio4_5PA;
263	output [0 : 1] Radio4_ANTSW;
264	output [0 : 2] Radio4_LED; //
265	output Radio4_ADC_RX_DCS;
266	output Radio4_ADC_RX_DFS; // 1
267	input Radio4_ADC_RX_OTRA;
268	input Radio4_ADC_RX_OTRB;
269	output Radio4_ADC_RX_PWDNA;
270	output Radio4_ADC_RX_PWDNB;
271	input [0 : 3] Radio4_DIPSW;
272	output Radio4_RSSI_ADC_CLAMP; //
273	output Radio4_RSSI_ADC_HIZ; //
274	input Radio4_RSSI_ADC_OTR;
275	output Radio4_RSSI_ADC_SLEEP; //
276	input [0 : 9] Radio4_RSSI_ADC_D;
277	input Radio4_TX_DAC_PLL_LOCK;
278	output Radio4_TX_DAC_RESET;
279
280	// -- ADD USER PORTS ABOVE THIS LINE -----------------
281
282	// -- DO NOT EDIT BELOW THIS LINE --------------------
283	// -- Bus protocol ports, do not add to or delete
284	input Bus2IP_Clk;
285	input Bus2IP_Reset;
286	input [0 : C_DWIDTH-1] Bus2IP_Data;
287	input [0 : C_DWIDTH/8-1] Bus2IP_BE;
288	input [0 : C_NUM_CE-1] Bus2IP_RdCE;
289	input [0 : C_NUM_CE-1] Bus2IP_WrCE;
290	output [0 : C_DWIDTH-1] IP2Bus_Data;
291	output IP2Bus_Ack;
292	output IP2Bus_Retry;
293	output IP2Bus_Error;
294	output IP2Bus_ToutSup;
295	// -- DO NOT EDIT ABOVE THIS LINE --------------------
296
297	//----------------------------------------------------------------------------
298	// Implementation
299	//----------------------------------------------------------------------------
300
301	// --USER nets declarations added here, as needed for user logic
302
303	// Nets for user logic slave model s/w accessible register example
304	reg [0 : C_DWIDTH-1] slv_reg0;
305	reg [0 : C_DWIDTH-1] slv_reg1;
306	reg [0 : C_DWIDTH-1] slv_reg2;
307	reg [0 : C_DWIDTH-1] slv_reg3;
308	wire [0 : 3] slv_reg_write_select;
309	wire [0 : 3] slv_reg_read_select;
310	reg [0 : C_DWIDTH-1] slv_ip2bus_data;
311	wire slv_read_ack;
312	wire slv_write_ack;
313	integer byte_index, bit_index;
314
315	// --USER logic implementation added here
316
317	//All active low signals are inverted here so that levels for all
318	// control signals are consistent from the software side
319	// (RadioN_SHDN, RadioN_24PA and RadioN_5PA)
320	assign Radio1_SHDN = ~slv_reg0[31];
321	assign Radio1_TxEn = slv_reg0[30];
322	assign Radio1_RxEn = slv_reg0[29];
323	assign Radio1_RxHP = slv_reg0[28];
324	assign Radio1_24PA = ~slv_reg0[26];
325	assign Radio1_5PA = ~slv_reg0[25];
326	assign Radio1_ANTSW[0] = slv_reg0[24];
327	assign Radio1_ANTSW[1] = slv_reg0[23];
328	assign Radio1_ADC_RX_DCS = slv_reg0[22];
329	assign Radio1_LED[0] = slv_reg0[21];
330	assign Radio1_LED[1] = slv_reg0[20];
331	assign Radio1_LED[2] = slv_reg0[19];
332	assign Radio1_ADC_RX_PWDNA = slv_reg0[18];
333	assign Radio1_ADC_RX_PWDNB = slv_reg0[17];
334	assign Radio1_RSSI_ADC_SLEEP = slv_reg0[16];
335	assign Radio1_TX_DAC_RESET = slv_reg0[10];
336
337	assign Radio1_ADC_RX_DFS = 1'b1; //slv_reg0[18];
338	assign Radio1_RSSI_ADC_CLAMP = 1'b0; //slv_reg0[9];
339	assign Radio1_RSSI_ADC_HIZ = 1'b0; //slv_reg0[8];
340
341	assign Radio2_SHDN = ~slv_reg1[31];
342	assign Radio2_TxEn = slv_reg1[30];
343	assign Radio2_RxEn = slv_reg1[29];
344	assign Radio2_RxHP = slv_reg1[28];
345	assign Radio2_24PA = ~slv_reg1[26];
346	assign Radio2_5PA = ~slv_reg1[25];
347	assign Radio2_ANTSW[0] = slv_reg1[24];
348	assign Radio2_ANTSW[1] = slv_reg1[23];
349	assign Radio2_ADC_RX_DCS = slv_reg1[22];
350	assign Radio2_LED[0] = slv_reg1[21];
351	assign Radio2_LED[1] = slv_reg1[20];
352	assign Radio2_LED[2] = slv_reg1[19];
353	assign Radio2_ADC_RX_PWDNA = slv_reg1[18];
354	assign Radio2_ADC_RX_PWDNB = slv_reg1[17];
355	assign Radio2_RSSI_ADC_SLEEP = slv_reg1[16];
356	assign Radio2_TX_DAC_RESET = slv_reg1[10];
357
358	assign Radio2_ADC_RX_DFS = 1'b1; //slv_reg1[18];
359	assign Radio2_RSSI_ADC_CLAMP = 1'b0; //slv_reg1[9];
360	assign Radio2_RSSI_ADC_HIZ = 1'b0; //slv_reg1[8];
361
362	assign Radio3_SHDN = ~slv_reg2[31];
363	assign Radio3_TxEn = slv_reg2[30];
364	assign Radio3_RxEn = slv_reg2[29];
365	assign Radio3_RxHP = slv_reg2[28];
366	assign Radio3_24PA = ~slv_reg2[26];
367	assign Radio3_5PA = ~slv_reg2[25];
368	assign Radio3_ANTSW[0] = slv_reg2[24];
369	assign Radio3_ANTSW[1] = slv_reg2[23];
370	assign Radio3_ADC_RX_DCS = slv_reg2[22];
371	assign Radio3_LED[0] = slv_reg2[21];
372	assign Radio3_LED[1] = slv_reg2[20];
373	assign Radio3_LED[2] = slv_reg2[19];
374	assign Radio3_ADC_RX_PWDNA = slv_reg2[18];
375	assign Radio3_ADC_RX_PWDNB = slv_reg2[17];
376	assign Radio3_RSSI_ADC_SLEEP = slv_reg2[16];
377	assign Radio3_TX_DAC_RESET = slv_reg2[10];
378
379	assign Radio3_ADC_RX_DFS = 1'b1; //slv_reg2[18];
380	assign Radio3_RSSI_ADC_CLAMP = 1'b0; //slv_reg2[9];
381	assign Radio3_RSSI_ADC_HIZ = 1'b0; //slv_reg2[8];
382
383	assign Radio4_SHDN = ~slv_reg3[31];
384	assign Radio4_TxEn = slv_reg3[30];
385	assign Radio4_RxEn = slv_reg3[29];
386	assign Radio4_RxHP = slv_reg3[28];
387	assign Radio4_24PA = ~slv_reg3[26];
388	assign Radio4_5PA = ~slv_reg3[25];
389	assign Radio4_ANTSW[0] = slv_reg3[24];
390	assign Radio4_ANTSW[1] = slv_reg3[23];
391	assign Radio4_ADC_RX_DCS = slv_reg3[22];
392	assign Radio4_LED[0] = slv_reg3[21];
393	assign Radio4_LED[1] = slv_reg3[20];
394	assign Radio4_LED[2] = slv_reg3[19];
395	assign Radio4_ADC_RX_PWDNA = slv_reg3[18];
396	assign Radio4_ADC_RX_PWDNB = slv_reg3[17];
397	assign Radio4_RSSI_ADC_SLEEP = slv_reg3[16];
398	assign Radio4_TX_DAC_RESET = slv_reg3[10];
399
400	assign Radio4_ADC_RX_DFS = 1'b1; //slv_reg3[18];
401	assign Radio4_RSSI_ADC_CLAMP = 1'b0; //slv_reg3[9];
402	assign Radio4_RSSI_ADC_HIZ = 1'b0; //slv_reg3[8];
403
404
405
406	// ------------------------------------------------------
407	// Example code to read/write user logic slave model s/w accessible registers
408	//
409	// Note:
410	// The example code presented here is to show you one way of reading/writing
411	// software accessible registers implemented in the user logic slave model.
412	// Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
413	// to one software accessible register by the top level template. For example,
414	// if you have four 32 bit software accessible registers in the user logic, you
415	// are basically operating on the following memory mapped registers:
416	//
417	// Bus2IP_WrCE or Memory Mapped
418	// Bus2IP_RdCE Register
419	// "1000" C_BASEADDR + 0x0
420	// "0100" C_BASEADDR + 0x4
421	// "0010" C_BASEADDR + 0x8
422	// "0001" C_BASEADDR + 0xC
423	//
424	// ------------------------------------------------------
425
426	assign
427	slv_reg_write_select = Bus2IP_WrCE[0:3],
428	slv_reg_read_select = Bus2IP_RdCE[0:3],
429	slv_write_ack = Bus2IP_WrCE[0] \|\| Bus2IP_WrCE[1] \|\| Bus2IP_WrCE[2] \|\| Bus2IP_WrCE[3],
430	slv_read_ack = Bus2IP_RdCE[0] \|\| Bus2IP_RdCE[1] \|\| Bus2IP_RdCE[2] \|\| Bus2IP_RdCE[3];
431
432	// implement slave model register(s)
433	always @( posedge Bus2IP_Clk )
434	begin: SLAVE_REG_WRITE_PROC
435
436	if ( Bus2IP_Reset == 1 )
437	begin
438	slv_reg0 <= 0;
439	slv_reg1 <= 0;
440	slv_reg2 <= 0;
441	slv_reg3 <= 0;
442	end
443	else
444	case ( slv_reg_write_select )
445	4'b1000 :
446	for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
447	if ( Bus2IP_BE[byte_index] == 1 )
448	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
449	slv_reg0[bit_index] <= Bus2IP_Data[bit_index];
450	4'b0100 :
451	for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
452	if ( Bus2IP_BE[byte_index] == 1 )
453	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
454	slv_reg1[bit_index] <= Bus2IP_Data[bit_index];
455	4'b0010 :
456	for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
457	if ( Bus2IP_BE[byte_index] == 1 )
458	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
459	slv_reg2[bit_index] <= Bus2IP_Data[bit_index];
460	4'b0001 :
461	for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
462	if ( Bus2IP_BE[byte_index] == 1 )
463	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
464	slv_reg3[bit_index] <= Bus2IP_Data[bit_index];
465	default : ;
466	endcase
467
468	end // SLAVE_REG_WRITE_PROC
469
470	// implement slave model register read mux
471	always @( slv_reg_read_select or slv_reg0 or slv_reg1 or slv_reg2 or slv_reg3 )
472	begin: SLAVE_REG_READ_PROC
473
474	case ( slv_reg_read_select )
475	4'b1000 : slv_ip2bus_data <= {Radio1_RSSI_ADC_D[0:9],
476	slv_reg0[10],
477	Radio1_TX_DAC_PLL_LOCK,
478	Radio1_RSSI_ADC_OTR,
479	Radio1_DIPSW[0:3],
480	slv_reg0[17:18],
481	Radio1_ADC_RX_OTRB,
482	Radio1_ADC_RX_OTRA,
483	Radio1_ADC_RX_DFS,
484	slv_reg0[22:26],
485	Radio1_LD,
486	slv_reg0[28:31]};
487
488	4'b0100 : slv_ip2bus_data <= {Radio2_RSSI_ADC_D[0:9],
489	slv_reg1[10],
490	Radio2_TX_DAC_PLL_LOCK,
491	Radio2_RSSI_ADC_OTR,
492	Radio2_DIPSW[0:3],
493	slv_reg1[17:18],
494	Radio2_ADC_RX_OTRB,
495	Radio2_ADC_RX_OTRA,
496	Radio2_ADC_RX_DFS,
497	slv_reg1[22:26],
498	Radio2_LD,
499	slv_reg1[28:31]};
500
501	4'b0010 : slv_ip2bus_data <= {Radio3_RSSI_ADC_D[0:9],
502	slv_reg2[10],
503	Radio3_TX_DAC_PLL_LOCK,
504	Radio3_RSSI_ADC_OTR,
505	Radio3_DIPSW[0:3],
506	slv_reg2[17:18],
507	Radio3_ADC_RX_OTRB,
508	Radio3_ADC_RX_OTRA,
509	Radio3_ADC_RX_DFS,
510	slv_reg2[22:26],
511	Radio3_LD,
512	slv_reg2[28:31]};
513
514	4'b0001 : slv_ip2bus_data <= {Radio4_RSSI_ADC_D[0:9],
515	slv_reg3[10],
516	Radio4_TX_DAC_PLL_LOCK,
517	Radio4_RSSI_ADC_OTR,
518	Radio4_DIPSW[0:3],
519	slv_reg3[17:18],
520	Radio4_ADC_RX_OTRB,
521	Radio4_ADC_RX_OTRA,
522	Radio4_ADC_RX_DFS,
523	slv_reg3[22:26],
524	Radio4_LD,
525	slv_reg3[28:31]};
526
527	default : slv_ip2bus_data <= 0;
528	endcase
529
530	end // SLAVE_REG_READ_PROC
531
532	// ------------------------------------------------------------
533	// Example code to drive IP to Bus signals
534	// ------------------------------------------------------------
535
536	assign IP2Bus_Data = slv_ip2bus_data;
537	assign IP2Bus_Ack = slv_write_ack \|\| slv_read_ack;
538	assign IP2Bus_Error = 0;
539	assign IP2Bus_Retry = 0;
540	assign IP2Bus_ToutSup = 0;
541
542	endmodule

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source: PlatformSupport/Deprecated/pcores/radio_controller_v1_02_a/hdl/verilog/user_logic.v

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