Context Navigation

source: PlatformSupport/Deprecated/pcores/radio_controller_v1_04_a/hdl/verilog/user_logic.v

Last change on this file was 255, checked in by sgupta, 18 years ago
Added License to all necessary Radio Controller files
File size: 26.7 KB

Line
1	//----------------------------------------------------------------------------
2	// user_logic.v - module
3	//----------------------------------------------------------------------------
4	//
5	/* Copyright (c) 2006 Rice University */
6	/* All Rights Reserved */
7	/* This code is covered by the Rice-WARP license */
8	/* See http://warp.rice.edu/license/ for details */
9	//
10	//----------------------------------------------------------------------------
11	// Filename: user_logic.v
12	// Version: 1.04.a
13	// Description: User logic module.
14	// Date: Sat Apr 15 16:16:16 2006 (by Create and Import Peripheral Wizard)
15	// Verilog Standard: Verilog-2001
16	//----------------------------------------------------------------------------
17	// Naming Conventions:
18	// active low signals: "*_n"
19	// clock signals: "clk", "clk_div#", "clk_#x"
20	// reset signals: "rst", "rst_n"
21	// generics: "C_*"
22	// user defined types: "*_TYPE"
23	// state machine next state: "*_ns"
24	// state machine current state: "*_cs"
25	// combinatorial signals: "*_com"
26	// pipelined or register delay signals: "*_d#"
27	// counter signals: "cnt"
28	// clock enable signals: "*_ce"
29	// internal version of output port: "*_i"
30	// device pins: "*_pin"
31	// ports: "- Names begin with Uppercase"
32	// processes: "*_PROCESS"
33	// component instantiations: "<ENTITY_>I_<#\|FUNC>"
34	//----------------------------------------------------------------------------
35
36	module user_logic
37	(
38	// -- ADD USER PORTS BELOW THIS LINE ---------------
39	// --USER ports added here
40
41	spi_clk,
42	data_out,
43	Radio1_cs,
44	Radio2_cs,
45	Radio3_cs,
46	Radio4_cs,
47	Dac1_cs,
48	Dac2_cs,
49	Dac3_cs,
50	Dac4_cs,
51	Radio1_SHDN,
52	Radio1_TxEn,
53	Radio1_RxEn,
54	Radio1_RxHP,
55	Radio1_LD,
56	Radio1_24PA,
57	Radio1_5PA,
58	Radio1_ANTSW,
59	Radio1_LED,
60	Radio1_ADC_RX_DCS,
61	Radio1_ADC_RX_DFS,
62	Radio1_ADC_RX_OTRA,
63	Radio1_ADC_RX_OTRB,
64	Radio1_ADC_RX_PWDNA,
65	Radio1_ADC_RX_PWDNB,
66	Radio1_DIPSW,
67	Radio1_RSSI_ADC_CLAMP,
68	Radio1_RSSI_ADC_HIZ,
69	Radio1_RSSI_ADC_OTR,
70	Radio1_RSSI_ADC_SLEEP,
71	Radio1_RSSI_ADC_D,
72	Radio1_TX_DAC_PLL_LOCK,
73	Radio1_TX_DAC_RESET,
74	Radio1_RxHP_external,
75	Radio2_SHDN,
76	Radio2_TxEn,
77	Radio2_RxEn,
78	Radio2_RxHP,
79	Radio2_LD,
80	Radio2_24PA,
81	Radio2_5PA,
82	Radio2_ANTSW,
83	Radio2_LED,
84	Radio2_ADC_RX_DCS,
85	Radio2_ADC_RX_DFS,
86	Radio2_ADC_RX_OTRA,
87	Radio2_ADC_RX_OTRB,
88	Radio2_ADC_RX_PWDNA,
89	Radio2_ADC_RX_PWDNB,
90	Radio2_DIPSW,
91	Radio2_RSSI_ADC_CLAMP,
92	Radio2_RSSI_ADC_HIZ,
93	Radio2_RSSI_ADC_OTR,
94	Radio2_RSSI_ADC_SLEEP,
95	Radio2_RSSI_ADC_D,
96	Radio2_TX_DAC_PLL_LOCK,
97	Radio2_TX_DAC_RESET,
98	Radio2_RxHP_external,
99	Radio3_SHDN,
100	Radio3_TxEn,
101	Radio3_RxEn,
102	Radio3_RxHP,
103	Radio3_LD,
104	Radio3_24PA,
105	Radio3_5PA,
106	Radio3_ANTSW,
107	Radio3_LED,
108	Radio3_ADC_RX_DCS,
109	Radio3_ADC_RX_DFS,
110	Radio3_ADC_RX_OTRA,
111	Radio3_ADC_RX_OTRB,
112	Radio3_ADC_RX_PWDNA,
113	Radio3_ADC_RX_PWDNB,
114	Radio3_DIPSW,
115	Radio3_RSSI_ADC_CLAMP,
116	Radio3_RSSI_ADC_HIZ,
117	Radio3_RSSI_ADC_OTR,
118	Radio3_RSSI_ADC_SLEEP,
119	Radio3_RSSI_ADC_D,
120	Radio3_TX_DAC_PLL_LOCK,
121	Radio3_TX_DAC_RESET,
122	Radio3_RxHP_external,
123	Radio4_SHDN,
124	Radio4_TxEn,
125	Radio4_RxEn,
126	Radio4_RxHP,
127	Radio4_LD,
128	Radio4_24PA,
129	Radio4_5PA,
130	Radio4_ANTSW,
131	Radio4_LED,
132	Radio4_ADC_RX_DCS,
133	Radio4_ADC_RX_DFS,
134	Radio4_ADC_RX_OTRA,
135	Radio4_ADC_RX_OTRB,
136	Radio4_ADC_RX_PWDNA,
137	Radio4_ADC_RX_PWDNB,
138	Radio4_DIPSW,
139	Radio4_RSSI_ADC_CLAMP,
140	Radio4_RSSI_ADC_HIZ,
141	Radio4_RSSI_ADC_OTR,
142	Radio4_RSSI_ADC_SLEEP,
143	Radio4_RSSI_ADC_D,
144	Radio4_TX_DAC_PLL_LOCK,
145	Radio4_TX_DAC_RESET,
146	Radio4_RxHP_external,
147
148
149	// -- ADD USER PORTS ABOVE THIS LINE ---------------
150
151	// -- DO NOT EDIT BELOW THIS LINE ------------------
152	// -- Bus protocol ports, do not add to or delete
153	Bus2IP_Clk, // Bus to IP clock
154	Bus2IP_Reset, // Bus to IP reset
155	Bus2IP_Data, // Bus to IP data bus for user logic
156	Bus2IP_BE, // Bus to IP byte enables for user logic
157	Bus2IP_RdCE, // Bus to IP read chip enable for user logic
158	Bus2IP_WrCE, // Bus to IP write chip enable for user logic
159	IP2Bus_Data, // IP to Bus data bus for user logic
160	IP2Bus_Ack, // IP to Bus acknowledgement
161	IP2Bus_Retry, // IP to Bus retry response
162	IP2Bus_Error, // IP to Bus error response
163	IP2Bus_ToutSup // IP to Bus timeout suppress
164	// -- DO NOT EDIT ABOVE THIS LINE ------------------
165	); // user_logic
166
167	// -- ADD USER PARAMETERS BELOW THIS LINE ------------
168	// --USER parameters added here
169	// -- ADD USER PARAMETERS ABOVE THIS LINE ------------
170
171	// -- DO NOT EDIT BELOW THIS LINE --------------------
172	// -- Bus protocol parameters, do not add to or delete
173	parameter C_DWIDTH = 32;
174	parameter C_NUM_CE = 8;
175	// -- DO NOT EDIT ABOVE THIS LINE --------------------
176
177	// -- ADD USER PORTS BELOW THIS LINE -----------------
178	// --USER ports added here
179
180
181	output spi_clk;
182	output data_out;
183	output Radio1_cs;
184	output Radio2_cs;
185	output Radio3_cs;
186	output Radio4_cs;
187	output Dac1_cs;
188	output Dac2_cs;
189	output Dac3_cs;
190	output Dac4_cs;
191	output Radio1_SHDN;
192	output Radio1_TxEn;
193	output Radio1_RxEn;
194	output Radio1_RxHP;
195	input Radio1_LD;
196	output Radio1_24PA;
197	output Radio1_5PA;
198	output [0 : 1] Radio1_ANTSW;
199	output [0 : 2] Radio1_LED;
200	output Radio1_ADC_RX_DCS;
201	output Radio1_ADC_RX_DFS;
202	input Radio1_ADC_RX_OTRA;
203	input Radio1_ADC_RX_OTRB;
204	output Radio1_ADC_RX_PWDNA;
205	output Radio1_ADC_RX_PWDNB;
206	input [0 : 3] Radio1_DIPSW;
207	output Radio1_RSSI_ADC_CLAMP;
208	output Radio1_RSSI_ADC_HIZ;
209	input Radio1_RSSI_ADC_OTR;
210	output Radio1_RSSI_ADC_SLEEP;
211	input [0 : 9] Radio1_RSSI_ADC_D;
212	input Radio1_TX_DAC_PLL_LOCK;
213	output Radio1_TX_DAC_RESET;
214	input Radio1_RxHP_external;
215	output Radio2_SHDN;
216	output Radio2_TxEn;
217	output Radio2_RxEn;
218	output Radio2_RxHP;
219	input Radio2_LD;
220	output Radio2_24PA;
221	output Radio2_5PA;
222	output [0 : 1] Radio2_ANTSW;
223	output [0 : 2] Radio2_LED;
224	output Radio2_ADC_RX_DCS;
225	output Radio2_ADC_RX_DFS;
226	input Radio2_ADC_RX_OTRA;
227	input Radio2_ADC_RX_OTRB;
228	output Radio2_ADC_RX_PWDNA;
229	output Radio2_ADC_RX_PWDNB;
230	input [0 : 3] Radio2_DIPSW;
231	output Radio2_RSSI_ADC_CLAMP;
232	output Radio2_RSSI_ADC_HIZ;
233	input Radio2_RSSI_ADC_OTR;
234	output Radio2_RSSI_ADC_SLEEP;
235	input [0 : 9] Radio2_RSSI_ADC_D;
236	input Radio2_TX_DAC_PLL_LOCK;
237	output Radio2_TX_DAC_RESET;
238	input Radio2_RxHP_external;
239	output Radio3_SHDN;
240	output Radio3_TxEn;
241	output Radio3_RxEn;
242	output Radio3_RxHP;
243	input Radio3_LD;
244	output Radio3_24PA;
245	output Radio3_5PA;
246	output [0 : 1] Radio3_ANTSW;
247	output [0 : 2] Radio3_LED;
248	output Radio3_ADC_RX_DCS;
249	output Radio3_ADC_RX_DFS;
250	input Radio3_ADC_RX_OTRA;
251	input Radio3_ADC_RX_OTRB;
252	output Radio3_ADC_RX_PWDNA;
253	output Radio3_ADC_RX_PWDNB;
254	input [0 : 3] Radio3_DIPSW;
255	output Radio3_RSSI_ADC_CLAMP;
256	output Radio3_RSSI_ADC_HIZ;
257	input Radio3_RSSI_ADC_OTR;
258	output Radio3_RSSI_ADC_SLEEP;
259	input [0 : 9] Radio3_RSSI_ADC_D;
260	input Radio3_TX_DAC_PLL_LOCK;
261	output Radio3_TX_DAC_RESET;
262	input Radio3_RxHP_external;
263	output Radio4_SHDN;
264	output Radio4_TxEn;
265	output Radio4_RxEn;
266	output Radio4_RxHP;
267	input Radio4_LD;
268	output Radio4_24PA;
269	output Radio4_5PA;
270	output [0 : 1] Radio4_ANTSW;
271	output [0 : 2] Radio4_LED; //
272	output Radio4_ADC_RX_DCS;
273	output Radio4_ADC_RX_DFS; // 1
274	input Radio4_ADC_RX_OTRA;
275	input Radio4_ADC_RX_OTRB;
276	output Radio4_ADC_RX_PWDNA;
277	output Radio4_ADC_RX_PWDNB;
278	input [0 : 3] Radio4_DIPSW;
279	output Radio4_RSSI_ADC_CLAMP; //
280	output Radio4_RSSI_ADC_HIZ; //
281	input Radio4_RSSI_ADC_OTR;
282	output Radio4_RSSI_ADC_SLEEP; //
283	input [0 : 9] Radio4_RSSI_ADC_D;
284	input Radio4_TX_DAC_PLL_LOCK;
285	output Radio4_TX_DAC_RESET;
286	input Radio4_RxHP_external;
287
288
289	// -- ADD USER PORTS ABOVE THIS LINE -----------------
290
291	// -- DO NOT EDIT BELOW THIS LINE --------------------
292	// -- Bus protocol ports, do not add to or delete
293	input Bus2IP_Clk;
294	input Bus2IP_Reset;
295	input [0 : C_DWIDTH-1] Bus2IP_Data;
296	input [0 : C_DWIDTH/8-1] Bus2IP_BE;
297	input [0 : C_NUM_CE-1] Bus2IP_RdCE;
298	input [0 : C_NUM_CE-1] Bus2IP_WrCE;
299	output [0 : C_DWIDTH-1] IP2Bus_Data;
300	output IP2Bus_Ack;
301	output IP2Bus_Retry;
302	output IP2Bus_Error;
303	output IP2Bus_ToutSup;
304	// -- DO NOT EDIT ABOVE THIS LINE --------------------
305
306	//----------------------------------------------------------------------------
307	// Implementation
308	//----------------------------------------------------------------------------
309
310	// --USER nets declarations added here, as needed for user logic
311
312	// Nets for user logic slave model s/w accessible register example
313	reg [0 : C_DWIDTH-1] slv_reg0;
314	reg [0 : C_DWIDTH-1] slv_reg1;
315	reg [0 : C_DWIDTH-1] slv_reg2;
316	reg [0 : C_DWIDTH-1] slv_reg3;
317	reg [0 : C_DWIDTH-1] slv_reg4;
318	reg [0 : C_DWIDTH-1] slv_reg5;
319	reg [0 : C_DWIDTH-1] slv_reg6;
320	reg [0 : C_DWIDTH-1] slv_reg7;
321	wire [0 : 7] slv_reg_write_select;
322	wire [0 : 7] slv_reg_read_select;
323	reg [0 : C_DWIDTH-1] slv_ip2bus_data;
324	wire slv_read_ack;
325	wire slv_write_ack;
326	integer byte_index, bit_index;
327
328	// --USER logic implementation added here
329
330
331	wire [7:0] ss_pad_o;
332	wire mytip;
333	wire [13:0] reg_ctrl;
334	wire [7:0] reg_ss;
335	wire reg_divider;
336	wire [17:0] reg_tx;
337
338
339	assign Radio1_SHDN = ~slv_reg0[31];
340	assign Radio1_TxEn = slv_reg0[30];
341	assign Radio1_RxEn = slv_reg0[29];
342	assign Radio1_RxHP = (slv_reg0[27])?slv_reg0[28]:Radio1_RxHP_external;
343	assign Radio1_24PA = ~slv_reg0[26];
344	assign Radio1_5PA = ~slv_reg0[25];
345	assign Radio1_ANTSW[0] = slv_reg0[23];
346	assign Radio1_ANTSW[1] = slv_reg0[24];
347	assign Radio1_ADC_RX_DCS = slv_reg0[22];
348	assign Radio1_LED[0] = ~Radio1_TX_DAC_PLL_LOCK;
349	assign Radio1_LED[1] = Radio1_TxEn;
350	assign Radio1_LED[2] = ~Radio1_LD;
351	assign Radio1_ADC_RX_PWDNA = slv_reg0[18];
352	assign Radio1_ADC_RX_PWDNB = slv_reg0[17];
353	assign Radio1_RSSI_ADC_SLEEP = slv_reg0[16];
354	assign Radio1_TX_DAC_RESET = slv_reg0[10];
355
356	assign Radio1_ADC_RX_DFS = 1'b1; //slv_reg0[18];
357	assign Radio1_RSSI_ADC_CLAMP = 1'b0; //slv_reg0[9];
358	assign Radio1_RSSI_ADC_HIZ = 1'b0; //slv_reg0[8];
359
360	assign Radio2_SHDN = ~slv_reg1[31];
361	assign Radio2_TxEn = slv_reg1[30];
362	assign Radio2_RxEn = slv_reg1[29];
363	assign Radio2_RxHP = (slv_reg1[27])?slv_reg1[28]:Radio2_RxHP_external;
364	assign Radio2_24PA = ~slv_reg1[26];
365	assign Radio2_5PA = ~slv_reg1[25];
366	assign Radio2_ANTSW[0] = slv_reg1[23];
367	assign Radio2_ANTSW[1] = slv_reg1[24];
368	assign Radio2_ADC_RX_DCS = slv_reg1[22];
369	assign Radio2_LED[0] = ~Radio2_TX_DAC_PLL_LOCK;
370	assign Radio2_LED[1] = Radio2_TxEn;
371	assign Radio2_LED[2] = ~Radio2_LD;
372	assign Radio2_ADC_RX_PWDNA = slv_reg1[18];
373	assign Radio2_ADC_RX_PWDNB = slv_reg1[17];
374	assign Radio2_RSSI_ADC_SLEEP = slv_reg1[16];
375	assign Radio2_TX_DAC_RESET = slv_reg1[10];
376
377	assign Radio2_ADC_RX_DFS = 1'b1; //slv_reg1[18];
378	assign Radio2_RSSI_ADC_CLAMP = 1'b0; //slv_reg1[9];
379	assign Radio2_RSSI_ADC_HIZ = 1'b0; //slv_reg1[8];
380
381	assign Radio3_SHDN = ~slv_reg2[31];
382	assign Radio3_TxEn = slv_reg2[30];
383	assign Radio3_RxEn = slv_reg2[29];
384	assign Radio3_RxHP = (slv_reg2[27])?slv_reg2[28]:Radio3_RxHP_external;
385	assign Radio3_24PA = ~slv_reg2[26];
386	assign Radio3_5PA = ~slv_reg2[25];
387	assign Radio3_ANTSW[0] = slv_reg2[23];
388	assign Radio3_ANTSW[1] = slv_reg2[24];
389	assign Radio3_ADC_RX_DCS = slv_reg2[22];
390	assign Radio3_LED[0] = ~Radio3_TX_DAC_PLL_LOCK;
391	assign Radio3_LED[1] = Radio3_TxEn;
392	assign Radio3_LED[2] = ~Radio3_LD;
393	assign Radio3_ADC_RX_PWDNA = slv_reg2[18];
394	assign Radio3_ADC_RX_PWDNB = slv_reg2[17];
395	assign Radio3_RSSI_ADC_SLEEP = slv_reg2[16];
396	assign Radio3_TX_DAC_RESET = slv_reg2[10];
397
398	assign Radio3_ADC_RX_DFS = 1'b1; //slv_reg2[18];
399	assign Radio3_RSSI_ADC_CLAMP = 1'b0; //slv_reg2[9];
400	assign Radio3_RSSI_ADC_HIZ = 1'b0; //slv_reg2[8];
401
402	assign Radio4_SHDN = ~slv_reg3[31];
403	assign Radio4_TxEn = slv_reg3[30];
404	assign Radio4_RxEn = slv_reg3[29];
405	assign Radio4_RxHP = (slv_reg3[27])?slv_reg3[28]:Radio4_RxHP_external;
406	assign Radio4_24PA = ~slv_reg3[26];
407	assign Radio4_5PA = ~slv_reg3[25];
408	assign Radio4_ANTSW[0] = slv_reg3[23];
409	assign Radio4_ANTSW[1] = slv_reg3[24];
410	assign Radio4_ADC_RX_DCS = slv_reg3[22];
411	assign Radio4_LED[0] = ~Radio4_TX_DAC_PLL_LOCK;
412	assign Radio4_LED[1] = Radio4_TxEn;
413	assign Radio4_LED[2] = ~Radio4_LD;
414	assign Radio4_ADC_RX_PWDNA = slv_reg3[18];
415	assign Radio4_ADC_RX_PWDNB = slv_reg3[17];
416	assign Radio4_RSSI_ADC_SLEEP = slv_reg3[16];
417	assign Radio4_TX_DAC_RESET = slv_reg3[10];
418
419	assign Radio4_ADC_RX_DFS = 1'b1; //slv_reg3[18];
420	assign Radio4_RSSI_ADC_CLAMP = 1'b0; //slv_reg3[9];
421	assign Radio4_RSSI_ADC_HIZ = 1'b0; //slv_reg3[8];
422
423	assign Radio1_cs = ss_pad_o[0];
424	assign Radio2_cs = ss_pad_o[1];
425	assign Radio3_cs = ss_pad_o[2];
426	assign Radio4_cs = ss_pad_o[3];
427	assign Dac1_cs = ss_pad_o[4];
428	assign Dac2_cs = ss_pad_o[5];
429	assign Dac3_cs = ss_pad_o[6];
430	assign Dac4_cs = ss_pad_o[7];
431
432	assign reg_ctrl = slv_reg4[18:31];
433	assign reg_divider = slv_reg5[31];
434	assign reg_ss = slv_reg6[24:31];
435	assign reg_tx = slv_reg7[14:31];
436
437	spi_top spi_top(
438	.opb_clk_i(Bus2IP_Clk),
439	.opb_rst_i(Bus2IP_Reset),
440	.reg_ctrl(reg_ctrl),
441	.reg_ss(reg_ss),
442	.reg_divider(reg_divider),
443	.reg_tx(reg_tx),
444	.ctrlwrite(Bus2IP_WrCE[4]),
445	.busval(Bus2IP_Data[23]),
446	.go(mytip),
447	.ss_pad_o(ss_pad_o),
448	.sclk_pad_o(spi_clk),
449	.mosi_pad_o(data_out)
450	);
451
452
453	// ------------------------------------------------------
454	// Example code to read/write user logic slave model s/w accessible registers
455	//
456	// Note:
457	// The example code presented here is to show you one way of reading/writing
458	// software accessible registers implemented in the user logic slave model.
459	// Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
460	// to one software accessible register by the top level template. For example,
461	// if you have four 32 bit software accessible registers in the user logic, you
462	// are basically operating on the following memory mapped registers:
463	//
464	// Bus2IP_WrCE or Memory Mapped
465	// Bus2IP_RdCE Register
466	// "1000" C_BASEADDR + 0x0
467	// "0100" C_BASEADDR + 0x4
468	// "0010" C_BASEADDR + 0x8
469	// "0001" C_BASEADDR + 0xC
470	//
471	// ------------------------------------------------------
472
473	assign
474	slv_reg_write_select = Bus2IP_WrCE[0:7],
475	slv_reg_read_select = Bus2IP_RdCE[0:7],
476	slv_write_ack = Bus2IP_WrCE[0] \|\| Bus2IP_WrCE[1] \|\| Bus2IP_WrCE[2] \|\| Bus2IP_WrCE[3] \|\| Bus2IP_WrCE[4] \|\| Bus2IP_WrCE[5] \|\| Bus2IP_WrCE[6] \|\| Bus2IP_WrCE[7],
477	slv_read_ack = Bus2IP_RdCE[0] \|\| Bus2IP_RdCE[1] \|\| Bus2IP_RdCE[2] \|\| Bus2IP_RdCE[3] \|\| Bus2IP_RdCE[4] \|\| Bus2IP_RdCE[5] \|\| Bus2IP_RdCE[6] \|\| Bus2IP_RdCE[7];
478
479	// implement slave model register(s)
480	always @( posedge Bus2IP_Clk )
481	begin: SLAVE_REG_WRITE_PROC
482
483	if ( Bus2IP_Reset == 1 )
484	begin
485	slv_reg0 <= 0;
486	slv_reg1 <= 0;
487	slv_reg2 <= 0;
488	slv_reg3 <= 0;
489	slv_reg4 <= 0;
490	slv_reg5 <= 0;
491	slv_reg6 <= 0;
492	slv_reg7 <= 0;
493	end
494	else
495	case ( slv_reg_write_select )
496	8'b10000000 :
497	for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
498	if ( Bus2IP_BE[byte_index] == 1 )
499	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
500	slv_reg0[bit_index] <= Bus2IP_Data[bit_index];
501	8'b01000000 :
502	for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
503	if ( Bus2IP_BE[byte_index] == 1 )
504	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
505	slv_reg1[bit_index] <= Bus2IP_Data[bit_index];
506	8'b00100000 :
507	for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
508	if ( Bus2IP_BE[byte_index] == 1 )
509	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
510	slv_reg2[bit_index] <= Bus2IP_Data[bit_index];
511	8'b00010000 :
512	for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
513	if ( Bus2IP_BE[byte_index] == 1 )
514	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
515	slv_reg3[bit_index] <= Bus2IP_Data[bit_index];
516	8'b00001000 :
517	for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
518	if ( Bus2IP_BE[byte_index] == 1 )
519	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
520	slv_reg4[bit_index] <= Bus2IP_Data[bit_index];
521	8'b00000100 :
522	for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
523	if ( Bus2IP_BE[byte_index] == 1 )
524	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
525	slv_reg5[bit_index] <= Bus2IP_Data[bit_index];
526	8'b00000010 :
527	for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
528	if ( Bus2IP_BE[byte_index] == 1 )
529	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
530	slv_reg6[bit_index] <= Bus2IP_Data[bit_index];
531	8'b00000001 :
532	for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
533	if ( Bus2IP_BE[byte_index] == 1 )
534	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
535	slv_reg7[bit_index] <= Bus2IP_Data[bit_index];
536	default : ;
537	endcase
538
539	end // SLAVE_REG_WRITE_PROC
540
541	// implement slave model register read mux
542	always @( slv_reg_read_select or slv_reg0 or slv_reg1 or slv_reg2 or slv_reg3 or slv_reg4 or slv_reg5 or slv_reg6 or slv_reg7 )
543	begin: SLAVE_REG_READ_PROC
544
545	case ( slv_reg_read_select )
546	8'b10000000 : slv_ip2bus_data <= {Radio1_RSSI_ADC_D[0:9],
547	slv_reg0[10],
548	Radio1_TX_DAC_PLL_LOCK,
549	Radio1_RSSI_ADC_OTR,
550	Radio1_DIPSW[3],
551	Radio1_DIPSW[2],
552	Radio1_DIPSW[1],
553	Radio1_DIPSW[0],
554	slv_reg0[17:18],
555	Radio1_ADC_RX_OTRB,
556	Radio1_ADC_RX_OTRA,
557	Radio1_ADC_RX_DFS,
558	slv_reg0[22:26],
559	Radio1_LD,
560	slv_reg0[28:31]};
561
562	8'b01000000 : slv_ip2bus_data <= {Radio2_RSSI_ADC_D[0:9],
563	slv_reg1[10],
564	Radio2_TX_DAC_PLL_LOCK,
565	Radio2_RSSI_ADC_OTR,
566	Radio2_DIPSW[3],
567	Radio2_DIPSW[2],
568	Radio2_DIPSW[1],
569	Radio2_DIPSW[0],
570	slv_reg1[17:18],
571	Radio2_ADC_RX_OTRB,
572	Radio2_ADC_RX_OTRA,
573	Radio2_ADC_RX_DFS,
574	slv_reg1[22:26],
575	Radio2_LD,
576	slv_reg1[28:31]};
577
578	8'b00100000 : slv_ip2bus_data <= {Radio3_RSSI_ADC_D[0:9],
579	slv_reg2[10],
580	Radio3_TX_DAC_PLL_LOCK,
581	Radio3_RSSI_ADC_OTR,
582	Radio3_DIPSW[3],
583	Radio3_DIPSW[2],
584	Radio3_DIPSW[1],
585	Radio3_DIPSW[0],
586	slv_reg2[17:18],
587	Radio3_ADC_RX_OTRB,
588	Radio3_ADC_RX_OTRA,
589	Radio3_ADC_RX_DFS,
590	slv_reg2[22:26],
591	Radio3_LD,
592	slv_reg2[28:31]};
593
594	8'b00010000 : slv_ip2bus_data <= {Radio4_RSSI_ADC_D[0:9],
595	slv_reg3[10],
596	Radio4_TX_DAC_PLL_LOCK,
597	Radio4_RSSI_ADC_OTR,
598	Radio4_DIPSW[3],
599	Radio4_DIPSW[2],
600	Radio4_DIPSW[1],
601	Radio4_DIPSW[0],
602	slv_reg3[17:18],
603	Radio4_ADC_RX_OTRB,
604	Radio4_ADC_RX_OTRA,
605	Radio4_ADC_RX_DFS,
606	slv_reg3[22:26],
607	Radio4_LD,
608	slv_reg3[28:31]};
609
610	8'b00001000 : slv_ip2bus_data <= {slv_reg4[0:22], mytip, slv_reg4[24:31]};
611	8'b00000100 : slv_ip2bus_data <= slv_reg5;
612	8'b00000010 : slv_ip2bus_data <= slv_reg6;
613	8'b00000001 : slv_ip2bus_data <= slv_reg7;
614	default : slv_ip2bus_data <= 0;
615	endcase
616
617	end // SLAVE_REG_READ_PROC
618
619	// ------------------------------------------------------------
620	// Example code to drive IP to Bus signals
621	// ------------------------------------------------------------
622
623	assign IP2Bus_Data = slv_ip2bus_data;
624	assign IP2Bus_Ack = slv_write_ack \|\| slv_read_ack;
625	assign IP2Bus_Error = 0;
626	assign IP2Bus_Retry = 0;
627	assign IP2Bus_ToutSup = 0;
628
629	endmodule

Note: See TracBrowser for help on using the repository browser.

Download in other formats: