source: PlatformSupport/Deprecated/pcores/radio_controller_v1_05_a/data/radio_controller_v2_1_0.mpd

# Copyright (c) 2006 Rice University
# All Rights Reserved
# This code is covered by the Rice-WARP license
# See http://warp.rice.edu/license/ for details
###################################################################
##
## Name     : radio_controller
## Desc     : Microprocessor Peripheral Description
##          : Automatically generated by PsfUtility
##
###################################################################

BEGIN radio_controller

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION CORE_STATE = ACTIVE
OPTION IP_GROUP = MICROBLAZE:PPC:USER
OPTION USAGE_LEVEL = BASE_USER
OPTION HDL = MIXED
OPTION STYLE = HDL

IO_INTERFACE IO_IF = radio_controller, IO_TYPE = WARP_RADIOCONTROLLER_V1


## Bus Interfaces
BUS_INTERFACE BUS = SOPB, BUS_TYPE = SLAVE, BUS_STD = OPB

## Generics for VHDL or Parameters for Verilog
PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x100, BUS = SOPB, ADDRESS = BASE, PAIR = C_HIGHADDR
PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, BUS = SOPB, ADDRESS = HIGH, PAIR = C_BASEADDR
PARAMETER C_OPB_AWIDTH = 32, DT = INTEGER, BUS = SOPB
PARAMETER C_OPB_DWIDTH = 32, DT = INTEGER, BUS = SOPB
PARAMETER C_FAMILY = virtex2p, DT = STRING

## Ports
PORT OPB_Clk = "", DIR = I, SIGIS = Clk, BUS = SOPB
PORT OPB_Rst = OPB_Rst, DIR = I, SIGIS = Rst, BUS = SOPB
PORT Sl_DBus = Sl_DBus, DIR = O, VEC = [0:(C_OPB_DWIDTH-1)], BUS = SOPB
PORT Sl_errAck = Sl_errAck, DIR = O, BUS = SOPB
PORT Sl_retry = Sl_retry, DIR = O, BUS = SOPB
PORT Sl_toutSup = Sl_toutSup, DIR = O, BUS = SOPB
PORT Sl_xferAck = Sl_xferAck, DIR = O, BUS = SOPB
PORT OPB_ABus = OPB_ABus, DIR = I, VEC = [0:(C_OPB_AWIDTH-1)], BUS = SOPB
PORT OPB_BE = OPB_BE, DIR = I, VEC = [0:((C_OPB_DWIDTH/8)-1)], BUS = SOPB
PORT OPB_DBus = OPB_DBus, DIR = I, VEC = [0:(C_OPB_DWIDTH-1)], BUS = SOPB
PORT OPB_RNW = OPB_RNW, DIR = I, BUS = SOPB
PORT OPB_select = OPB_select, DIR = I, BUS = SOPB
PORT OPB_seqAddr = OPB_seqAddr, DIR = I, BUS = SOPB

PORT spi_clk = "", DIR = O
PORT data_out = "", DIR = O
PORT radio1_cs = "", DIR = O
PORT radio2_cs = "", DIR = O
PORT radio3_cs = "", DIR = O
PORT radio4_cs = "", DIR = O
PORT dac1_cs = "", DIR = O
PORT dac2_cs = "", DIR = O
PORT dac3_cs = "", DIR = O
PORT dac4_cs = "", DIR = O
PORT radio1_SHDN = "", DIR = O
PORT radio1_TxEn = "", DIR = O
PORT radio1_RxEn = "", DIR = O
PORT radio1_RxHP = "", DIR = O
PORT radio1_LD = "", DIR = I
PORT radio1_24PA = "", DIR = O
PORT radio1_5PA = "", DIR = O
PORT radio1_ANTSW = "", DIR = O, VEC = [0:1], IO_IS = radio1_antsw
PORT radio1_LED = "", DIR = O, VEC = [0:2], IO_IS = radio1_LED
PORT radio1_ADC_RX_DCS = "", DIR = O
PORT radio1_ADC_RX_DFS = "", DIR = O
PORT radio1_ADC_RX_OTRA = "", DIR = I
PORT radio1_ADC_RX_OTRB = "", DIR = I
PORT radio1_ADC_RX_PWDNA = "", DIR = O
PORT radio1_ADC_RX_PWDNB = "", DIR = O
PORT radio1_DIPSW = "", DIR = I, VEC = [0:3], IO_IS = radio1_dipsw
PORT radio1_RSSI_ADC_CLAMP = "", DIR = O
PORT radio1_RSSI_ADC_HIZ = "", DIR = O
PORT radio1_RSSI_ADC_OTR = "", DIR = I
PORT radio1_RSSI_ADC_SLEEP = "", DIR = O
PORT radio1_RSSI_ADC_D = "", DIR = I, VEC = [0:9], IO_IS = radio1_rssi_ADC_D
PORT radio1_TX_DAC_PLL_LOCK = "", DIR = I
PORT radio1_TX_DAC_RESET = "", DIR = O
PORT radio1_RxHP_external = "", DIR = I
PORT radio1_TxGain = "", DIR = O, VEC = [0:5], IO_IS = radio1_TxGain
PORT radio1_TxStart = "", DIR = O
PORT radio2_SHDN = "", DIR = O
PORT radio2_TxEn = "", DIR = O
PORT radio2_RxEn = "", DIR = O
PORT radio2_RxHP = "", DIR = O
PORT radio2_LD = "", DIR = I
PORT radio2_24PA = "", DIR = O
PORT radio2_5PA = "", DIR = O
PORT radio2_ANTSW = "", DIR = O, VEC = [0:1], IO_IS = radio2_antsw
PORT radio2_LED = "", DIR = O, VEC = [0:2], IO_IS = radio2_LED
PORT radio2_ADC_RX_DCS = "", DIR = O
PORT radio2_ADC_RX_DFS = "", DIR = O
PORT radio2_ADC_RX_OTRA = "", DIR = I
PORT radio2_ADC_RX_OTRB = "", DIR = I
PORT radio2_ADC_RX_PWDNA = "", DIR = O
PORT radio2_ADC_RX_PWDNB = "", DIR = O
PORT radio2_DIPSW = "", DIR = I, VEC = [0:3], IO_IS = radio2_dipsw
PORT radio2_RSSI_ADC_CLAMP = "", DIR = O
PORT radio2_RSSI_ADC_HIZ = "", DIR = O
PORT radio2_RSSI_ADC_OTR = "", DIR = I
PORT radio2_RSSI_ADC_SLEEP = "", DIR = O
PORT radio2_RSSI_ADC_D = "", DIR = I, VEC = [0:9], IO_IS = radio2_rssi_ADC_D
PORT radio2_TX_DAC_PLL_LOCK = "", DIR = I
PORT radio2_TX_DAC_RESET = "", DIR = O
PORT radio2_RxHP_external = "", DIR = I
PORT radio2_TxGain = "", DIR = O, VEC = [0:5], IO_IS = radio2_TxGain
PORT radio2_TxStart = "", DIR = O
PORT radio3_SHDN = "", DIR = O
PORT radio3_TxEn = "", DIR = O
PORT radio3_RxEn = "", DIR = O
PORT radio3_RxHP = "", DIR = O
PORT radio3_LD = "", DIR = I
PORT radio3_24PA = "", DIR = O
PORT radio3_5PA = "", DIR = O
PORT radio3_ANTSW = "", DIR = O, VEC = [0:1], IO_IS = radio3_antsw
PORT radio3_LED = "", DIR = O, VEC = [0:2], IO_IS = radio3_LED
PORT radio3_ADC_RX_DCS = "", DIR = O
PORT radio3_ADC_RX_DFS = "", DIR = O
PORT radio3_ADC_RX_OTRA = "", DIR = I
PORT radio3_ADC_RX_OTRB = "", DIR = I
PORT radio3_ADC_RX_PWDNA = "", DIR = O
PORT radio3_ADC_RX_PWDNB = "", DIR = O
PORT radio3_DIPSW = "", DIR = I, VEC = [0:3], IO_IS = radio3_dipsw
PORT radio3_RSSI_ADC_CLAMP = "", DIR = O
PORT radio3_RSSI_ADC_HIZ = "", DIR = O
PORT radio3_RSSI_ADC_OTR = "", DIR = I
PORT radio3_RSSI_ADC_SLEEP = "", DIR = O
PORT radio3_RSSI_ADC_D = "", DIR = I, VEC = [0:9], IO_IS = radio3_rssi_ADC_D
PORT radio3_TX_DAC_PLL_LOCK = "", DIR = I
PORT radio3_TX_DAC_RESET = "", DIR = O
PORT radio3_RxHP_external = "", DIR = I
PORT radio3_TxGain = "", DIR = O, VEC = [0:5], IO_IS = radio3_TxGain
PORT radio3_TxStart = "", DIR = O
PORT radio4_SHDN = "", DIR = O
PORT radio4_TxEn = "", DIR = O
PORT radio4_RxEn = "", DIR = O
PORT radio4_RxHP = "", DIR = O
PORT radio4_LD = "", DIR = I
PORT radio4_24PA = "", DIR = O
PORT radio4_5PA = "", DIR = O
PORT radio4_ANTSW = "", DIR = O, VEC = [0:1], IO_IS = radio4_antsw
PORT radio4_LED = "", DIR = O, VEC = [0:2], IO_IS = radio4_LED
PORT radio4_ADC_RX_DCS = "", DIR = O
PORT radio4_ADC_RX_DFS = "", DIR = O
PORT radio4_ADC_RX_OTRA = "", DIR = I
PORT radio4_ADC_RX_OTRB = "", DIR = I
PORT radio4_ADC_RX_PWDNA = "", DIR = O
PORT radio4_ADC_RX_PWDNB = "", DIR = O
PORT radio4_DIPSW = "", DIR = I, VEC = [0:3], IO_IS = radio4_dipsw
PORT radio4_RSSI_ADC_CLAMP = "", DIR = O
PORT radio4_RSSI_ADC_HIZ = "", DIR = O
PORT radio4_RSSI_ADC_OTR = "", DIR = I
PORT radio4_RSSI_ADC_SLEEP = "", DIR = O
PORT radio4_RSSI_ADC_D = "", DIR = I, VEC = [0:9], IO_IS = radio4_rssi_ADC_D
PORT radio4_TX_DAC_PLL_LOCK = "", DIR = I
PORT radio4_TX_DAC_RESET = "", DIR = O
PORT radio4_RxHP_external = "", DIR = I
PORT radio4_TxGain = "", DIR = O, VEC = [0:5], IO_IS = radio4_TxGain
PORT radio4_TxStart = "", DIR = O

END