1 | ////////////////////////////////////////////////////////////////////// |
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2 | //// //// |
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3 | //// spi_define.v //// |
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4 | //// //// |
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5 | //// This file is part of the SPI IP core project //// |
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6 | //// http://www.opencores.org/projects/spi/ //// |
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7 | //// //// |
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8 | //// Author(s): //// |
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9 | //// - Simon Srot (simons@opencores.org) //// |
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10 | //// //// |
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11 | //// All additional information is avaliable in the Readme.txt //// |
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12 | //// file. //// |
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13 | //// //// |
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14 | ////////////////////////////////////////////////////////////////////// |
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15 | //// //// |
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16 | //// Copyright (C) 2002 Authors //// |
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17 | //// //// |
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18 | //// This source file may be used and distributed without //// |
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19 | //// restriction provided that this copyright statement is not //// |
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20 | //// removed from the file and that any derivative work contains //// |
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21 | //// the original copyright notice and the associated disclaimer. //// |
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22 | //// //// |
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23 | //// This source file is free software; you can redistribute it //// |
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24 | //// and/or modify it under the terms of the GNU Lesser General //// |
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25 | //// Public License as published by the Free Software Foundation; //// |
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26 | //// either version 2.1 of the License, or (at your option) any //// |
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27 | //// later version. //// |
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28 | //// //// |
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29 | //// This source is distributed in the hope that it will be //// |
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30 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
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31 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
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32 | //// PURPOSE. See the GNU Lesser General Public License for more //// |
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33 | //// details. //// |
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34 | //// //// |
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35 | //// You should have received a copy of the GNU Lesser General //// |
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36 | //// Public License along with this source; if not, download it //// |
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37 | //// from http://www.opencores.org/lgpl.shtml //// |
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38 | //// //// |
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39 | ////////////////////////////////////////////////////////////////////// |
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40 | |
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41 | // |
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42 | // Number of bits used for devider register. If used in system with |
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43 | // low frequency of system clock this can be reduced. |
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44 | // Use SPI_DIVIDER_LEN for fine tuning theexact number. |
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45 | // |
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46 | `define SPI_DIVIDER_LEN_8 |
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47 | //`define SPI_DIVIDER_LEN_16 |
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48 | //`define SPI_DIVIDER_LEN_24 |
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49 | //`define SPI_DIVIDER_LEN_32 |
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50 | |
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51 | `ifdef SPI_DIVIDER_LEN_8 |
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52 | // `define SPI_DIVIDER_LEN 8 // Can be set from 1 to 8 |
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53 | `define SPI_DIVIDER_LEN 1 // Can be set from 1 to 8 |
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54 | `endif |
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55 | `ifdef SPI_DIVIDER_LEN_16 |
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56 | `define SPI_DIVIDER_LEN 16 // Can be set from 9 to 16 |
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57 | `endif |
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58 | `ifdef SPI_DIVIDER_LEN_24 |
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59 | `define SPI_DIVIDER_LEN 24 // Can be set from 17 to 24 |
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60 | `endif |
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61 | `ifdef SPI_DIVIDER_LEN_32 |
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62 | `define SPI_DIVIDER_LEN 32 // Can be set from 25 to 32 |
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63 | `endif |
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64 | |
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65 | // |
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66 | // Maximum nuber of bits that can be send/received at once. |
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67 | // Use SPI_MAX_CHAR for fine tuning the exact number, when using |
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68 | // SPI_MAX_CHAR_32, SPI_MAX_CHAR_24, SPI_MAX_CHAR_16, SPI_MAX_CHAR_8. |
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69 | // |
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70 | //`define SPI_MAX_CHAR_128 |
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71 | //`define SPI_MAX_CHAR_64 |
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72 | //`define SPI_MAX_CHAR_32 |
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73 | `define SPI_MAX_CHAR_24 |
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74 | //`define SPI_MAX_CHAR_16 |
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75 | //`define SPI_MAX_CHAR_8 |
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76 | |
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77 | `ifdef SPI_MAX_CHAR_128 |
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78 | `define SPI_MAX_CHAR 128 // Can only be set to 128 |
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79 | `define SPI_CHAR_LEN_BITS 7 |
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80 | `endif |
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81 | `ifdef SPI_MAX_CHAR_64 |
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82 | `define SPI_MAX_CHAR 64 // Can only be set to 64 |
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83 | `define SPI_CHAR_LEN_BITS 6 |
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84 | `endif |
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85 | `ifdef SPI_MAX_CHAR_32 |
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86 | `define SPI_MAX_CHAR 32 // Can be set from 25 to 32 |
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87 | `define SPI_CHAR_LEN_BITS 5 |
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88 | `endif |
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89 | `ifdef SPI_MAX_CHAR_24 |
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90 | // `define SPI_MAX_CHAR 24 // Can be set from 17 to 24 |
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91 | `define SPI_MAX_CHAR 18 // Can be set from 17 to 24 |
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92 | `define SPI_CHAR_LEN_BITS 5 |
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93 | `endif |
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94 | `ifdef SPI_MAX_CHAR_16 |
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95 | `define SPI_MAX_CHAR 16 // Can be set from 9 to 16 |
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96 | `define SPI_CHAR_LEN_BITS 4 |
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97 | `endif |
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98 | `ifdef SPI_MAX_CHAR_8 |
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99 | `define SPI_MAX_CHAR 8 // Can be set from 1 to 8 |
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100 | `define SPI_CHAR_LEN_BITS 3 |
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101 | `endif |
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102 | |
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103 | // |
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104 | // Number of device select signals. Use SPI_SS_NB for fine tuning the |
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105 | // exact number. |
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106 | // |
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107 | `define SPI_SS_NB_8 |
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108 | //`define SPI_SS_NB_16 |
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109 | //`define SPI_SS_NB_24 |
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110 | //`define SPI_SS_NB_32 |
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111 | |
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112 | `ifdef SPI_SS_NB_8 |
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113 | // `define SPI_SS_NB 8 // Can be set from 1 to 8 |
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114 | `define SPI_SS_NB 8 // Can be set from 1 to 8 |
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115 | `endif |
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116 | `ifdef SPI_SS_NB_16 |
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117 | `define SPI_SS_NB 16 // Can be set from 9 to 16 |
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118 | `endif |
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119 | `ifdef SPI_SS_NB_24 |
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120 | `define SPI_SS_NB 24 // Can be set from 17 to 24 |
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121 | `endif |
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122 | `ifdef SPI_SS_NB_32 |
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123 | `define SPI_SS_NB 32 // Can be set from 25 to 32 |
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124 | `endif |
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125 | |
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126 | // |
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127 | // Bits of WISHBONE address used for partial decoding of SPI registers. |
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128 | // |
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129 | `define SPI_OFS_BITS 4:2 |
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130 | |
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131 | // |
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132 | // Register offset |
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133 | // |
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134 | `define SPI_RX_0 0 |
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135 | `define SPI_RX_1 1 |
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136 | `define SPI_RX_2 2 |
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137 | `define SPI_RX_3 3 |
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138 | `define SPI_TX_0 0 |
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139 | `define SPI_TX_1 1 |
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140 | `define SPI_TX_2 2 |
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141 | `define SPI_TX_3 3 |
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142 | `define SPI_CTRL 4 |
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143 | `define SPI_DEVIDE 5 |
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144 | `define SPI_SS 6 |
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145 | |
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146 | // |
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147 | // Number of bits in ctrl register |
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148 | // |
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149 | `define SPI_CTRL_BIT_NB 14 |
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150 | |
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151 | // |
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152 | // Control register bit position |
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153 | // |
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154 | `define SPI_CTRL_ASS 13 |
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155 | `define SPI_CTRL_IE 12 |
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156 | `define SPI_CTRL_LSB 11 |
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157 | `define SPI_CTRL_TX_NEGEDGE 10 |
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158 | `define SPI_CTRL_RX_NEGEDGE 9 |
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159 | `define SPI_CTRL_GO 8 |
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160 | `define SPI_CTRL_RES_1 7 |
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161 | `define SPI_CTRL_CHAR_LEN 6:0 |
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162 | |
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