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source: PlatformSupport/Deprecated/pcores/radio_controller_v1_05_a/hdl/vhdl/radio_controller.vhd

Last change on this file was 388, checked in by murphpo, 18 years ago
Updated 1.05 controller and bridge
File size: 38.2 KB

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1	-- Copyright (c) 2006 Rice University
2	-- All Rights Reserved
3	-- This code is covered by the Rice-WARP license
4	-- See http://warp.rice.edu/license/ for details
5
6	------------------------------------------------------------------------------
7	-- radio_controller.vhd - entity/architecture pair
8	------------------------------------------------------------------------------
9
10	library ieee;
11	use ieee.std_logic_1164.all;
12	use ieee.std_logic_arith.all;
13	use ieee.std_logic_unsigned.all;
14
15	library proc_common_v2_00_a;
16	use proc_common_v2_00_a.proc_common_pkg.all;
17	use proc_common_v2_00_a.ipif_pkg.all;
18	library opb_ipif_v3_01_c;
19	use opb_ipif_v3_01_c.all;
20
21	library radio_controller_v1_05_a;
22	use radio_controller_v1_05_a.all;
23
24	------------------------------------------------------------------------------
25	-- Entity section
26	------------------------------------------------------------------------------
27	-- Definition of Generics:
28	-- C_BASEADDR -- User logic base address
29	-- C_HIGHADDR -- User logic high address
30	-- C_OPB_AWIDTH -- OPB address bus width
31	-- C_OPB_DWIDTH -- OPB data bus width
32	-- C_FAMILY -- Target FPGA architecture
33	--
34	-- Definition of Ports:
35	-- OPB_Clk -- OPB Clock
36	-- OPB_Rst -- OPB Reset
37	-- Sl_DBus -- Slave data bus
38	-- Sl_errAck -- Slave error acknowledge
39	-- Sl_retry -- Slave retry
40	-- Sl_toutSup -- Slave timeout suppress
41	-- Sl_xferAck -- Slave transfer acknowledge
42	-- OPB_ABus -- OPB address bus
43	-- OPB_BE -- OPB byte enable
44	-- OPB_DBus -- OPB data bus
45	-- OPB_RNW -- OPB read/not write
46	-- OPB_select -- OPB select
47	-- OPB_seqAddr -- OPB sequential address
48	------------------------------------------------------------------------------
49
50	entity radio_controller is
51	generic
52	(
53	-- DO NOT EDIT BELOW THIS LINE ---------------------
54	-- Bus protocol parameters, do not add to or delete
55	C_BASEADDR : std_logic_vector := X"00000000";
56	C_HIGHADDR : std_logic_vector := X"0000FFFF";
57	C_OPB_AWIDTH : integer := 32;
58	C_OPB_DWIDTH : integer := 32;
59	C_FAMILY : string := "virtex2p"
60	-- DO NOT EDIT ABOVE THIS LINE ---------------------
61	);
62	port
63	(
64	-- ADD USER PORTS BELOW THIS LINE ------------------
65
66	spi_clk : out std_logic;
67	data_out : out std_logic;
68	radio1_cs : out std_logic;
69	radio2_cs : out std_logic;
70	radio3_cs : out std_logic;
71	radio4_cs : out std_logic;
72	dac1_cs : out std_logic;
73	dac2_cs : out std_logic;
74	dac3_cs : out std_logic;
75	dac4_cs : out std_logic;
76	radio1_SHDN : out std_logic;
77	radio1_TxEn : out std_logic;
78	radio1_RxEn : out std_logic;
79	radio1_RxHP : out std_logic;
80	radio1_LD : in std_logic;
81	radio1_24PA : out std_logic;
82	radio1_5PA : out std_logic;
83	radio1_ANTSW : out std_logic_vector(0 to 1);
84	radio1_LED : out std_logic_vector(0 to 2);
85	radio1_ADC_RX_DCS : out std_logic;
86	radio1_ADC_RX_DFS : out std_logic;
87	radio1_ADC_RX_OTRA : in std_logic;
88	radio1_ADC_RX_OTRB : in std_logic;
89	radio1_ADC_RX_PWDNA : out std_logic;
90	radio1_ADC_RX_PWDNB : out std_logic;
91	radio1_DIPSW : in std_logic_vector(0 to 3);
92	radio1_RSSI_ADC_CLAMP : out std_logic;
93	radio1_RSSI_ADC_HIZ : out std_logic;
94	radio1_RSSI_ADC_OTR : in std_logic;
95	radio1_RSSI_ADC_SLEEP : out std_logic;
96	radio1_RSSI_ADC_D : in std_logic_vector(0 to 9);
97	radio1_TX_DAC_PLL_LOCK : in std_logic;
98	radio1_TX_DAC_RESET : out std_logic;
99	radio1_RxHP_external : in std_logic;
100	radio1_TxGain : out std_logic_vector(0 to 5);
101	radio1_TxStart : out std_logic;
102	radio2_SHDN : out std_logic;
103	radio2_TxEn : out std_logic;
104	radio2_RxEn : out std_logic;
105	radio2_RxHP : out std_logic;
106	radio2_LD : in std_logic;
107	radio2_24PA : out std_logic;
108	radio2_5PA : out std_logic;
109	radio2_ANTSW : out std_logic_vector(0 to 1);
110	radio2_LED : out std_logic_vector(0 to 2);
111	radio2_ADC_RX_DCS : out std_logic;
112	radio2_ADC_RX_DFS : out std_logic;
113	radio2_ADC_RX_OTRA : in std_logic;
114	radio2_ADC_RX_OTRB : in std_logic;
115	radio2_ADC_RX_PWDNA : out std_logic;
116	radio2_ADC_RX_PWDNB : out std_logic;
117	radio2_DIPSW : in std_logic_vector(0 to 3);
118	radio2_RSSI_ADC_CLAMP : out std_logic;
119	radio2_RSSI_ADC_HIZ : out std_logic;
120	radio2_RSSI_ADC_OTR : in std_logic;
121	radio2_RSSI_ADC_SLEEP : out std_logic;
122	radio2_RSSI_ADC_D : in std_logic_vector(0 to 9);
123	radio2_TX_DAC_PLL_LOCK : in std_logic;
124	radio2_TX_DAC_RESET : out std_logic;
125	radio2_RxHP_external : in std_logic;
126	radio2_TxGain : out std_logic_vector(0 to 5);
127	radio2_TxStart : out std_logic;
128	radio3_SHDN : out std_logic;
129	radio3_TxEn : out std_logic;
130	radio3_RxEn : out std_logic;
131	radio3_RxHP : out std_logic;
132	radio3_LD : in std_logic;
133	radio3_24PA : out std_logic;
134	radio3_5PA : out std_logic;
135	radio3_ANTSW : out std_logic_vector(0 to 1);
136	radio3_LED : out std_logic_vector(0 to 2);
137	radio3_ADC_RX_DCS : out std_logic;
138	radio3_ADC_RX_DFS : out std_logic;
139	radio3_ADC_RX_OTRA : in std_logic;
140	radio3_ADC_RX_OTRB : in std_logic;
141	radio3_ADC_RX_PWDNA : out std_logic;
142	radio3_ADC_RX_PWDNB : out std_logic;
143	radio3_DIPSW : in std_logic_vector(0 to 3);
144	radio3_RSSI_ADC_CLAMP : out std_logic;
145	radio3_RSSI_ADC_HIZ : out std_logic;
146	radio3_RSSI_ADC_OTR : in std_logic;
147	radio3_RSSI_ADC_SLEEP : out std_logic;
148	radio3_RSSI_ADC_D : in std_logic_vector(0 to 9);
149	radio3_TX_DAC_PLL_LOCK : in std_logic;
150	radio3_TX_DAC_RESET : out std_logic;
151	radio3_RxHP_external : in std_logic;
152	radio3_TxGain : out std_logic_vector(0 to 5);
153	radio3_TxStart : out std_logic;
154	radio4_SHDN : out std_logic;
155	radio4_TxEn : out std_logic;
156	radio4_RxEn : out std_logic;
157	radio4_RxHP : out std_logic;
158	radio4_LD : in std_logic;
159	radio4_24PA : out std_logic;
160	radio4_5PA : out std_logic;
161	radio4_ANTSW : out std_logic_vector(0 to 1);
162	radio4_LED : out std_logic_vector(0 to 2);
163	radio4_ADC_RX_DCS : out std_logic;
164	radio4_ADC_RX_DFS : out std_logic;
165	radio4_ADC_RX_OTRA : in std_logic;
166	radio4_ADC_RX_OTRB : in std_logic;
167	radio4_ADC_RX_PWDNA : out std_logic;
168	radio4_ADC_RX_PWDNB : out std_logic;
169	radio4_DIPSW : in std_logic_vector(0 to 3);
170	radio4_RSSI_ADC_CLAMP : out std_logic;
171	radio4_RSSI_ADC_HIZ : out std_logic;
172	radio4_RSSI_ADC_OTR : in std_logic;
173	radio4_RSSI_ADC_SLEEP : out std_logic;
174	radio4_RSSI_ADC_D : in std_logic_vector(0 to 9);
175	radio4_TX_DAC_PLL_LOCK : in std_logic;
176	radio4_TX_DAC_RESET : out std_logic;
177	radio4_RxHP_external : in std_logic;
178	radio4_TxGain : out std_logic_vector(0 to 5);
179	radio4_TxStart : out std_logic;
180
181	-- DO NOT EDIT BELOW THIS LINE ---------------------
182	-- Bus protocol ports, do not add to or delete
183	OPB_Clk : in std_logic;
184	OPB_Rst : in std_logic;
185	Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
186	Sl_errAck : out std_logic;
187	Sl_retry : out std_logic;
188	Sl_toutSup : out std_logic;
189	Sl_xferAck : out std_logic;
190	OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
191	OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
192	OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
193	OPB_RNW : in std_logic;
194	OPB_select : in std_logic;
195	OPB_seqAddr : in std_logic
196	-- DO NOT EDIT ABOVE THIS LINE ---------------------
197	);
198
199	attribute SIGIS : string;
200	attribute SIGIS of OPB_Clk : signal is "Clk";
201	attribute SIGIS of OPB_Rst : signal is "Rst";
202
203	end entity radio_controller;
204
205	------------------------------------------------------------------------------
206	-- Architecture section
207	------------------------------------------------------------------------------
208
209	architecture IMP of radio_controller is
210
211	------------------------------------------
212	-- Constant: array of address range identifiers
213	------------------------------------------
214	constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE :=
215	(
216	0 => USER_00 -- user logic S/W register address space
217	);
218
219	------------------------------------------
220	-- Constant: array of address pairs for each address range
221	------------------------------------------
222	constant ZERO_ADDR_PAD : std_logic_vector(0 to 64-C_OPB_AWIDTH-1) := (others => '0');
223
224	constant USER_BASEADDR : std_logic_vector := C_BASEADDR;
225	constant USER_HIGHADDR : std_logic_vector := C_HIGHADDR;
226
227	constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
228	(
229	ZERO_ADDR_PAD & USER_BASEADDR, -- user logic base address
230	ZERO_ADDR_PAD & USER_HIGHADDR -- user logic high address
231	);
232
233	------------------------------------------
234	-- Constant: array of data widths for each target address range
235	------------------------------------------
236	constant USER_DWIDTH : integer := 32;
237
238	constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
239	(
240	0 => USER_DWIDTH -- user logic data width
241	);
242
243	------------------------------------------
244	-- Constant: array of desired number of chip enables for each address range
245	------------------------------------------
246	-- constant USER_NUM_CE : integer := 8;
247	constant USER_NUM_CE : integer := 16;
248
249	constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
250	(
251	0 => pad_power2(USER_NUM_CE) -- user logic number of CEs
252	);
253
254	------------------------------------------
255	-- Constant: array of unique properties for each address range
256	------------------------------------------
257	constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE :=
258	(
259	0 => (others => 0) -- user logic slave space dependent properties (none defined)
260	);
261
262	------------------------------------------
263	-- Constant: pipeline mode
264	-- 1 = include OPB-In pipeline registers
265	-- 2 = include IP pipeline registers
266	-- 3 = include OPB-In and IP pipeline registers
267	-- 4 = include OPB-Out pipeline registers
268	-- 5 = include OPB-In and OPB-Out pipeline registers
269	-- 6 = include IP and OPB-Out pipeline registers
270	-- 7 = include OPB-In, IP, and OPB-Out pipeline registers
271	-- Note:
272	-- only mode 4, 5, 7 are supported for this release
273	------------------------------------------
274	constant PIPELINE_MODEL : integer := 5;
275
276	------------------------------------------
277	-- Constant: user core ID code
278	------------------------------------------
279	constant DEV_BLK_ID : integer := 0;
280
281	------------------------------------------
282	-- Constant: enable MIR/Reset register
283	------------------------------------------
284	constant DEV_MIR_ENABLE : integer := 0;
285
286	------------------------------------------
287	-- Constant: array of IP interrupt mode
288	-- 1 = Active-high interrupt condition
289	-- 2 = Active-low interrupt condition
290	-- 3 = Active-high pulse interrupt event
291	-- 4 = Active-low pulse interrupt event
292	-- 5 = Positive-edge interrupt event
293	-- 6 = Negative-edge interrupt event
294	------------------------------------------
295	constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
296	(
297	0 => 0 -- not used
298	);
299
300	------------------------------------------
301	-- Constant: enable device burst
302	------------------------------------------
303	constant DEV_BURST_ENABLE : integer := 0;
304
305	------------------------------------------
306	-- Constant: include address counter for burst transfers
307	------------------------------------------
308	constant INCLUDE_ADDR_CNTR : integer := 0;
309
310	------------------------------------------
311	-- Constant: include write buffer that decouples OPB and IPIC write transactions
312	------------------------------------------
313	constant INCLUDE_WR_BUF : integer := 0;
314
315	------------------------------------------
316	-- Constant: index for CS/CE
317	------------------------------------------
318	constant USER00_CS_INDEX : integer := get_id_index(ARD_ID_ARRAY, USER_00);
319
320	constant USER00_CE_INDEX : integer := calc_start_ce_index(ARD_NUM_CE_ARRAY, USER00_CS_INDEX);
321
322	------------------------------------------
323	-- IP Interconnect (IPIC) signal declarations -- do not delete
324	-- prefix 'i' stands for IPIF while prefix 'u' stands for user logic
325	-- typically user logic will be hooked up to IPIF directly via i<sig>
326	-- unless signal slicing and muxing are needed via u<sig>
327	------------------------------------------
328	signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
329	signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
330	signal iBus2IP_Data : std_logic_vector(0 to C_OPB_DWIDTH-1);
331	signal iBus2IP_BE : std_logic_vector(0 to C_OPB_DWIDTH/8-1);
332	signal iIP2Bus_Data : std_logic_vector(0 to C_OPB_DWIDTH-1) := (others => '0');
333	signal iIP2Bus_Ack : std_logic := '0';
334	signal iIP2Bus_Error : std_logic := '0';
335	signal iIP2Bus_Retry : std_logic := '0';
336	signal iIP2Bus_ToutSup : std_logic := '0';
337	signal ZERO_IP2Bus_PostedWrInh : std_logic_vector(0 to ARD_ID_ARRAY'length-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
338	signal ZERO_IP2RFIFO_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_RDFIFO_DATA))-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
339	signal ZERO_WFIFO2IP_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_WRFIFO_DATA))-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
340	signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
341	signal iBus2IP_Clk : std_logic;
342	signal iBus2IP_Reset : std_logic;
343	signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1);
344	signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1);
345	signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1);
346	signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1);
347	signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1);
348
349	------------------------------------------
350	-- Component declaration for verilog user logic
351	------------------------------------------
352	component user_logic is
353	generic
354	(
355	-- ADD USER GENERICS BELOW THIS LINE ---------------
356	--USER generics added here
357	-- ADD USER GENERICS ABOVE THIS LINE ---------------
358
359	-- DO NOT EDIT BELOW THIS LINE ---------------------
360	-- Bus protocol parameters, do not add to or delete
361	C_DWIDTH : integer := 32;
362	C_NUM_CE : integer := 16
363	-- DO NOT EDIT ABOVE THIS LINE ---------------------
364	);
365	port
366	(
367	-- ADD USER PORTS BELOW THIS LINE ------------------
368	--USER ports added here
369
370	spi_clk : out std_logic;
371	data_out : out std_logic;
372	Radio1_cs : out std_logic;
373	Radio2_cs : out std_logic;
374	Radio3_cs : out std_logic;
375	Radio4_cs : out std_logic;
376	Dac1_cs : out std_logic;
377	Dac2_cs : out std_logic;
378	Dac3_cs : out std_logic;
379	Dac4_cs : out std_logic;
380	Radio1_SHDN : out std_logic;
381	Radio1_TxEn : out std_logic;
382	Radio1_RxEn : out std_logic;
383	Radio1_RxHP : out std_logic;
384	Radio1_LD : in std_logic;
385	Radio1_24PA : out std_logic;
386	Radio1_5PA : out std_logic;
387	Radio1_ANTSW : out std_logic_vector(0 to 1);
388	Radio1_LED : out std_logic_vector(0 to 2);
389	Radio1_ADC_RX_DCS : out std_logic;
390	Radio1_ADC_RX_DFS : out std_logic;
391	Radio1_ADC_RX_OTRA : in std_logic;
392	Radio1_ADC_RX_OTRB : in std_logic;
393	Radio1_ADC_RX_PWDNA : out std_logic;
394	Radio1_ADC_RX_PWDNB : out std_logic;
395	Radio1_DIPSW : in std_logic_vector(0 to 3);
396	Radio1_RSSI_ADC_CLAMP : out std_logic;
397	Radio1_RSSI_ADC_HIZ : out std_logic;
398	Radio1_RSSI_ADC_OTR : in std_logic;
399	Radio1_RSSI_ADC_SLEEP : out std_logic;
400	Radio1_RSSI_ADC_D : in std_logic_vector(0 to 9);
401	Radio1_TX_DAC_PLL_LOCK : in std_logic;
402	Radio1_TX_DAC_RESET : out std_logic;
403	Radio1_RxHP_external : in std_logic;
404	Radio1_TxGain : out std_logic_vector(0 to 5);
405	Radio1_TxStart : out std_logic;
406	Radio2_SHDN : out std_logic;
407	Radio2_TxEn : out std_logic;
408	Radio2_RxEn : out std_logic;
409	Radio2_RxHP : out std_logic;
410	Radio2_LD : in std_logic;
411	Radio2_24PA : out std_logic;
412	Radio2_5PA : out std_logic;
413	Radio2_ANTSW : out std_logic_vector(0 to 1);
414	Radio2_LED : out std_logic_vector(0 to 2);
415	Radio2_ADC_RX_DCS : out std_logic;
416	Radio2_ADC_RX_DFS : out std_logic;
417	Radio2_ADC_RX_OTRA : in std_logic;
418	Radio2_ADC_RX_OTRB : in std_logic;
419	Radio2_ADC_RX_PWDNA : out std_logic;
420	Radio2_ADC_RX_PWDNB : out std_logic;
421	Radio2_DIPSW : in std_logic_vector(0 to 3);
422	Radio2_RSSI_ADC_CLAMP : out std_logic;
423	Radio2_RSSI_ADC_HIZ : out std_logic;
424	Radio2_RSSI_ADC_OTR : in std_logic;
425	Radio2_RSSI_ADC_SLEEP : out std_logic;
426	Radio2_RSSI_ADC_D : in std_logic_vector(0 to 9);
427	Radio2_TX_DAC_PLL_LOCK : in std_logic;
428	Radio2_TX_DAC_RESET : out std_logic;
429	Radio2_RxHP_external : in std_logic;
430	Radio2_TxGain : out std_logic_vector(0 to 5);
431	Radio2_TxStart : out std_logic;
432	Radio3_SHDN : out std_logic;
433	Radio3_TxEn : out std_logic;
434	Radio3_RxEn : out std_logic;
435	Radio3_RxHP : out std_logic;
436	Radio3_LD : in std_logic;
437	Radio3_24PA : out std_logic;
438	Radio3_5PA : out std_logic;
439	Radio3_ANTSW : out std_logic_vector(0 to 1);
440	Radio3_LED : out std_logic_vector(0 to 2);
441	Radio3_ADC_RX_DCS : out std_logic;
442	Radio3_ADC_RX_DFS : out std_logic;
443	Radio3_ADC_RX_OTRA : in std_logic;
444	Radio3_ADC_RX_OTRB : in std_logic;
445	Radio3_ADC_RX_PWDNA : out std_logic;
446	Radio3_ADC_RX_PWDNB : out std_logic;
447	Radio3_DIPSW : in std_logic_vector(0 to 3);
448	Radio3_RSSI_ADC_CLAMP : out std_logic;
449	Radio3_RSSI_ADC_HIZ : out std_logic;
450	Radio3_RSSI_ADC_OTR : in std_logic;
451	Radio3_RSSI_ADC_SLEEP : out std_logic;
452	Radio3_RSSI_ADC_D : in std_logic_vector(0 to 9);
453	Radio3_TX_DAC_PLL_LOCK : in std_logic;
454	Radio3_TX_DAC_RESET : out std_logic;
455	Radio3_RxHP_external : in std_logic;
456	Radio3_TxGain : out std_logic_vector(0 to 5);
457	Radio3_TxStart : out std_logic;
458	Radio4_SHDN : out std_logic;
459	Radio4_TxEn : out std_logic;
460	Radio4_RxEn : out std_logic;
461	Radio4_RxHP : out std_logic;
462	Radio4_LD : in std_logic;
463	Radio4_24PA : out std_logic;
464	Radio4_5PA : out std_logic;
465	Radio4_ANTSW : out std_logic_vector(0 to 1);
466	Radio4_LED : out std_logic_vector(0 to 2);
467	Radio4_ADC_RX_DCS : out std_logic;
468	Radio4_ADC_RX_DFS : out std_logic;
469	Radio4_ADC_RX_OTRA : in std_logic;
470	Radio4_ADC_RX_OTRB : in std_logic;
471	Radio4_ADC_RX_PWDNA : out std_logic;
472	Radio4_ADC_RX_PWDNB : out std_logic;
473	Radio4_DIPSW : in std_logic_vector(0 to 3);
474	Radio4_RSSI_ADC_CLAMP : out std_logic;
475	Radio4_RSSI_ADC_HIZ : out std_logic;
476	Radio4_RSSI_ADC_OTR : in std_logic;
477	Radio4_RSSI_ADC_SLEEP : out std_logic;
478	Radio4_RSSI_ADC_D : in std_logic_vector(0 to 9);
479	Radio4_TX_DAC_PLL_LOCK : in std_logic;
480	Radio4_TX_DAC_RESET : out std_logic;
481	Radio4_RxHP_external : in std_logic;
482	Radio4_TxGain : out std_logic_vector(0 to 5);
483	Radio4_TxStart : out std_logic;
484	-- ADD USER PORTS ABOVE THIS LINE ------------------
485
486	-- DO NOT EDIT BELOW THIS LINE ---------------------
487	-- Bus protocol ports, do not add to or delete
488	Bus2IP_Clk : in std_logic;
489	Bus2IP_Reset : in std_logic;
490	Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
491	Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
492	Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1);
493	Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1);
494	IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
495	IP2Bus_Ack : out std_logic;
496	IP2Bus_Retry : out std_logic;
497	IP2Bus_Error : out std_logic;
498	IP2Bus_ToutSup : out std_logic
499	-- DO NOT EDIT ABOVE THIS LINE ---------------------
500	);
501	end component user_logic;
502
503	begin
504
505	------------------------------------------
506	-- instantiate the OPB IPIF
507	------------------------------------------
508	OPB_IPIF_I : entity opb_ipif_v3_01_c.opb_ipif
509	generic map
510	(
511	C_ARD_ID_ARRAY => ARD_ID_ARRAY,
512	C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
513	C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY,
514	C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
515	C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY,
516	C_PIPELINE_MODEL => PIPELINE_MODEL,
517	C_DEV_BLK_ID => DEV_BLK_ID,
518	C_DEV_MIR_ENABLE => DEV_MIR_ENABLE,
519	C_OPB_AWIDTH => C_OPB_AWIDTH,
520	C_OPB_DWIDTH => C_OPB_DWIDTH,
521	C_FAMILY => C_FAMILY,
522	C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
523	C_DEV_BURST_ENABLE => DEV_BURST_ENABLE,
524	C_INCLUDE_ADDR_CNTR => INCLUDE_ADDR_CNTR,
525	C_INCLUDE_WR_BUF => INCLUDE_WR_BUF
526	)
527	port map
528	(
529	OPB_select => OPB_select,
530	OPB_DBus => OPB_DBus,
531	OPB_ABus => OPB_ABus,
532	OPB_BE => OPB_BE,
533	OPB_RNW => OPB_RNW,
534	OPB_seqAddr => OPB_seqAddr,
535	Sln_DBus => Sl_DBus,
536	Sln_xferAck => Sl_xferAck,
537	Sln_errAck => Sl_errAck,
538	Sln_retry => Sl_retry,
539	Sln_toutSup => Sl_toutSup,
540	Bus2IP_CS => open,
541	Bus2IP_CE => open,
542	Bus2IP_RdCE => iBus2IP_RdCE,
543	Bus2IP_WrCE => iBus2IP_WrCE,
544	Bus2IP_Data => iBus2IP_Data,
545	Bus2IP_Addr => open,
546	Bus2IP_AddrValid => open,
547	Bus2IP_BE => iBus2IP_BE,
548	Bus2IP_RNW => open,
549	Bus2IP_Burst => open,
550	IP2Bus_Data => iIP2Bus_Data,
551	IP2Bus_Ack => iIP2Bus_Ack,
552	IP2Bus_AddrAck => '0',
553	IP2Bus_Error => iIP2Bus_Error,
554	IP2Bus_Retry => iIP2Bus_Retry,
555	IP2Bus_ToutSup => iIP2Bus_ToutSup,
556	IP2Bus_PostedWrInh => ZERO_IP2Bus_PostedWrInh,
557	IP2RFIFO_Data => ZERO_IP2RFIFO_Data,
558	IP2RFIFO_WrMark => '0',
559	IP2RFIFO_WrRelease => '0',
560	IP2RFIFO_WrReq => '0',
561	IP2RFIFO_WrRestore => '0',
562	RFIFO2IP_AlmostFull => open,
563	RFIFO2IP_Full => open,
564	RFIFO2IP_Vacancy => open,
565	RFIFO2IP_WrAck => open,
566	IP2WFIFO_RdMark => '0',
567	IP2WFIFO_RdRelease => '0',
568	IP2WFIFO_RdReq => '0',
569	IP2WFIFO_RdRestore => '0',
570	WFIFO2IP_AlmostEmpty => open,
571	WFIFO2IP_Data => ZERO_WFIFO2IP_Data,
572	WFIFO2IP_Empty => open,
573	WFIFO2IP_Occupancy => open,
574	WFIFO2IP_RdAck => open,
575	IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent,
576	IP2INTC_Irpt => open,
577	Freeze => '0',
578	Bus2IP_Freeze => open,
579	OPB_Clk => OPB_Clk,
580	Bus2IP_Clk => iBus2IP_Clk,
581	IP2Bus_Clk => '0',
582	Reset => OPB_Rst,
583	Bus2IP_Reset => iBus2IP_Reset
584	);
585
586	------------------------------------------
587	-- instantiate the User Logic
588	------------------------------------------
589	USER_LOGIC_I : component user_logic
590	generic map
591	(
592	-- MAP USER GENERICS BELOW THIS LINE ---------------
593	--USER generics mapped here
594	-- MAP USER GENERICS ABOVE THIS LINE ---------------
595
596	C_DWIDTH => USER_DWIDTH,
597	C_NUM_CE => USER_NUM_CE
598	)
599	port map
600	(
601	-- MAP USER PORTS BELOW THIS LINE ------------------
602	--USER ports mapped here
603
604
605	spi_clk => spi_clk,
606	data_out => data_out,
607	Radio1_cs => radio1_cs,
608	Radio2_cs => radio2_cs,
609	Radio3_cs => radio3_cs,
610	Radio4_cs => radio4_cs,
611	Dac1_cs => dac1_cs,
612	Dac2_cs => dac2_cs,
613	Dac3_cs => dac3_cs,
614	Dac4_cs => dac4_cs,
615	Radio1_SHDN => radio1_SHDN,
616	Radio1_TxEn => radio1_TxEn,
617	Radio1_RxEn => radio1_RxEn,
618	Radio1_RxHP => radio1_RxHP,
619	Radio1_LD => radio1_LD,
620	Radio1_24PA => radio1_24PA,
621	Radio1_5PA => radio1_5PA,
622	Radio1_ANTSW => radio1_ANTSW,
623	Radio1_LED => radio1_LED,
624	Radio1_ADC_RX_DCS => radio1_ADC_RX_DCS,
625	Radio1_ADC_RX_DFS => radio1_ADC_RX_DFS,
626	Radio1_ADC_RX_OTRA => radio1_ADC_RX_OTRA,
627	Radio1_ADC_RX_OTRB => radio1_ADC_RX_OTRB,
628	Radio1_ADC_RX_PWDNA => radio1_ADC_RX_PWDNA,
629	Radio1_ADC_RX_PWDNB => radio1_ADC_RX_PWDNB,
630	Radio1_DIPSW => radio1_DIPSW,
631	Radio1_RSSI_ADC_CLAMP => radio1_RSSI_ADC_CLAMP,
632	Radio1_RSSI_ADC_HIZ => radio1_RSSI_ADC_HIZ,
633	Radio1_RSSI_ADC_OTR => radio1_RSSI_ADC_OTR,
634	Radio1_RSSI_ADC_SLEEP => radio1_RSSI_ADC_SLEEP,
635	Radio1_RSSI_ADC_D => radio1_RSSI_ADC_D,
636	Radio1_TX_DAC_PLL_LOCK => radio1_TX_DAC_PLL_LOCK,
637	Radio1_TX_DAC_RESET => radio1_TX_DAC_RESET,
638	Radio1_RxHP_external => radio1_RxHP_external,
639	Radio1_TxGain => radio1_TxGain,
640	Radio1_TxStart => radio1_TxStart,
641	Radio2_SHDN => radio2_SHDN,
642	Radio2_TxEn => radio2_TxEn,
643	Radio2_RxEn => radio2_RxEn,
644	Radio2_RxHP => radio2_RxHP,
645	Radio2_LD => radio2_LD,
646	Radio2_24PA => radio2_24PA,
647	Radio2_5PA => radio2_5PA,
648	Radio2_ANTSW => radio2_ANTSW,
649	Radio2_LED => radio2_LED,
650	Radio2_ADC_RX_DCS => radio2_ADC_RX_DCS,
651	Radio2_ADC_RX_DFS => radio2_ADC_RX_DFS,
652	Radio2_ADC_RX_OTRA => radio2_ADC_RX_OTRA,
653	Radio2_ADC_RX_OTRB => radio2_ADC_RX_OTRB,
654	Radio2_ADC_RX_PWDNA => radio2_ADC_RX_PWDNA,
655	Radio2_ADC_RX_PWDNB => radio2_ADC_RX_PWDNB,
656	Radio2_DIPSW => radio2_DIPSW,
657	Radio2_RSSI_ADC_CLAMP => radio2_RSSI_ADC_CLAMP,
658	Radio2_RSSI_ADC_HIZ => radio2_RSSI_ADC_HIZ,
659	Radio2_RSSI_ADC_OTR => radio2_RSSI_ADC_OTR,
660	Radio2_RSSI_ADC_SLEEP => radio2_RSSI_ADC_SLEEP,
661	Radio2_RSSI_ADC_D => radio2_RSSI_ADC_D,
662	Radio2_TX_DAC_PLL_LOCK => radio2_TX_DAC_PLL_LOCK,
663	Radio2_TX_DAC_RESET => radio2_TX_DAC_RESET,
664	Radio2_RxHP_external => radio2_RxHP_external,
665	Radio2_TxGain => radio2_TxGain,
666	Radio2_TxStart => radio2_TxStart,
667	Radio3_SHDN => radio3_SHDN,
668	Radio3_TxEn => radio3_TxEn,
669	Radio3_RxEn => radio3_RxEn,
670	Radio3_RxHP => radio3_RxHP,
671	Radio3_LD => radio3_LD,
672	Radio3_24PA => radio3_24PA,
673	Radio3_5PA => radio3_5PA,
674	Radio3_ANTSW => radio3_ANTSW,
675	Radio3_LED => radio3_LED,
676	Radio3_ADC_RX_DCS => radio3_ADC_RX_DCS,
677	Radio3_ADC_RX_DFS => radio3_ADC_RX_DFS,
678	Radio3_ADC_RX_OTRA => radio3_ADC_RX_OTRA,
679	Radio3_ADC_RX_OTRB => radio3_ADC_RX_OTRB,
680	Radio3_ADC_RX_PWDNA => radio3_ADC_RX_PWDNA,
681	Radio3_ADC_RX_PWDNB => radio3_ADC_RX_PWDNB,
682	Radio3_DIPSW => radio3_DIPSW,
683	Radio3_RSSI_ADC_CLAMP => radio3_RSSI_ADC_CLAMP,
684	Radio3_RSSI_ADC_HIZ => radio3_RSSI_ADC_HIZ,
685	Radio3_RSSI_ADC_OTR => radio3_RSSI_ADC_OTR,
686	Radio3_RSSI_ADC_SLEEP => radio3_RSSI_ADC_SLEEP,
687	Radio3_RSSI_ADC_D => radio3_RSSI_ADC_D,
688	Radio3_TX_DAC_PLL_LOCK => radio3_TX_DAC_PLL_LOCK,
689	Radio3_TX_DAC_RESET => radio3_TX_DAC_RESET,
690	Radio3_RxHP_external => radio3_RxHP_external,
691	Radio3_TxGain => radio3_TxGain,
692	Radio3_TxStart => radio3_TxStart,
693	Radio4_SHDN => radio4_SHDN,
694	Radio4_TxEn => radio4_TxEn,
695	Radio4_RxEn => radio4_RxEn,
696	Radio4_RxHP => radio4_RxHP,
697	Radio4_LD => radio4_LD,
698	Radio4_24PA => radio4_24PA,
699	Radio4_5PA => radio4_5PA,
700	Radio4_ANTSW => radio4_ANTSW,
701	Radio4_LED => radio4_LED,
702	Radio4_ADC_RX_DCS => radio4_ADC_RX_DCS,
703	Radio4_ADC_RX_DFS => radio4_ADC_RX_DFS,
704	Radio4_ADC_RX_OTRA => radio4_ADC_RX_OTRA,
705	Radio4_ADC_RX_OTRB => radio4_ADC_RX_OTRB,
706	Radio4_ADC_RX_PWDNA => radio4_ADC_RX_PWDNA,
707	Radio4_ADC_RX_PWDNB => radio4_ADC_RX_PWDNB,
708	Radio4_DIPSW => radio4_DIPSW,
709	Radio4_RSSI_ADC_CLAMP => radio4_RSSI_ADC_CLAMP,
710	Radio4_RSSI_ADC_HIZ => radio4_RSSI_ADC_HIZ,
711	Radio4_RSSI_ADC_OTR => radio4_RSSI_ADC_OTR,
712	Radio4_RSSI_ADC_SLEEP => radio4_RSSI_ADC_SLEEP,
713	Radio4_RSSI_ADC_D => radio4_RSSI_ADC_D,
714	Radio4_TX_DAC_PLL_LOCK => radio4_TX_DAC_PLL_LOCK,
715	Radio4_TX_DAC_RESET => radio4_TX_DAC_RESET,
716	Radio4_RxHP_external => radio4_RxHP_external,
717	Radio4_TxGain => radio4_TxGain,
718	Radio4_TxStart => radio4_TxStart,
719
720	-- MAP USER PORTS ABOVE THIS LINE ------------------
721
722	Bus2IP_Clk => iBus2IP_Clk,
723	Bus2IP_Reset => iBus2IP_Reset,
724	Bus2IP_Data => uBus2IP_Data,
725	Bus2IP_BE => uBus2IP_BE,
726	Bus2IP_RdCE => uBus2IP_RdCE,
727	Bus2IP_WrCE => uBus2IP_WrCE,
728	IP2Bus_Data => uIP2Bus_Data,
729	IP2Bus_Ack => iIP2Bus_Ack,
730	IP2Bus_Retry => iIP2Bus_Retry,
731	IP2Bus_Error => iIP2Bus_Error,
732	IP2Bus_ToutSup => iIP2Bus_ToutSup
733	);
734
735	------------------------------------------
736	-- hooking up signal slicing
737	------------------------------------------
738	uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1);
739	uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1);
740	uBus2IP_RdCE <= iBus2IP_RdCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1);
741	uBus2IP_WrCE <= iBus2IP_WrCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1);
742	iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data;
743
744	end IMP;

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