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source: PlatformSupport/Deprecated/pcores/radio_controller_v1_08_a/hdl/verilog/user_logic.v

Last change on this file was 602, checked in by murphpo, 17 years ago
Updated radio controller to correctly handle the antenna switch when using external Tx/RxEn mode
File size: 31.4 KB

Line
1	/* Copyright (c) 2006 Rice University */
2	/* All Rights Reserved */
3	/* This code is covered by the Rice-WARP license */
4	/* See http://warp.rice.edu/license/ for details */
5
6	module user_logic
7	(
8	spi_clk,
9	data_out,
10	Radio1_cs,
11	Radio2_cs,
12	Radio3_cs,
13	Radio4_cs,
14	Dac1_cs,
15	Dac2_cs,
16	Dac3_cs,
17	Dac4_cs,
18	Radio1_SHDN,
19	Radio1_TxEn,
20	Radio1_RxEn,
21	Radio1_RxHP,
22	Radio1_LD,
23	Radio1_24PA,
24	Radio1_5PA,
25	Radio1_ANTSW,
26	Radio1_LED,
27	Radio1_ADC_RX_DCS,
28	Radio1_ADC_RX_DFS,
29	Radio1_ADC_RX_OTRA,
30	Radio1_ADC_RX_OTRB,
31	Radio1_ADC_RX_PWDNA,
32	Radio1_ADC_RX_PWDNB,
33	Radio1_DIPSW,
34	Radio1_RSSI_ADC_CLAMP,
35	Radio1_RSSI_ADC_HIZ,
36	Radio1_RSSI_ADC_OTR,
37	Radio1_RSSI_ADC_SLEEP,
38	Radio1_RSSI_ADC_D,
39	Radio1_TX_DAC_PLL_LOCK,
40	Radio1_TX_DAC_RESET,
41	Radio1_SHDN_external,
42	Radio1_TxEn_external,
43	Radio1_RxEn_external,
44	Radio1_RxHP_external,
45	Radio1_TxGain,
46	Radio1_TxStart,
47	Radio2_SHDN,
48	Radio2_TxEn,
49	Radio2_RxEn,
50	Radio2_RxHP,
51	Radio2_LD,
52	Radio2_24PA,
53	Radio2_5PA,
54	Radio2_ANTSW,
55	Radio2_LED,
56	Radio2_ADC_RX_DCS,
57	Radio2_ADC_RX_DFS,
58	Radio2_ADC_RX_OTRA,
59	Radio2_ADC_RX_OTRB,
60	Radio2_ADC_RX_PWDNA,
61	Radio2_ADC_RX_PWDNB,
62	Radio2_DIPSW,
63	Radio2_RSSI_ADC_CLAMP,
64	Radio2_RSSI_ADC_HIZ,
65	Radio2_RSSI_ADC_OTR,
66	Radio2_RSSI_ADC_SLEEP,
67	Radio2_RSSI_ADC_D,
68	Radio2_TX_DAC_PLL_LOCK,
69	Radio2_TX_DAC_RESET,
70	Radio2_SHDN_external,
71	Radio2_TxEn_external,
72	Radio2_RxEn_external,
73	Radio2_RxHP_external,
74	Radio2_TxGain,
75	Radio2_TxStart,
76	Radio3_SHDN,
77	Radio3_TxEn,
78	Radio3_RxEn,
79	Radio3_RxHP,
80	Radio3_LD,
81	Radio3_24PA,
82	Radio3_5PA,
83	Radio3_ANTSW,
84	Radio3_LED,
85	Radio3_ADC_RX_DCS,
86	Radio3_ADC_RX_DFS,
87	Radio3_ADC_RX_OTRA,
88	Radio3_ADC_RX_OTRB,
89	Radio3_ADC_RX_PWDNA,
90	Radio3_ADC_RX_PWDNB,
91	Radio3_DIPSW,
92	Radio3_RSSI_ADC_CLAMP,
93	Radio3_RSSI_ADC_HIZ,
94	Radio3_RSSI_ADC_OTR,
95	Radio3_RSSI_ADC_SLEEP,
96	Radio3_RSSI_ADC_D,
97	Radio3_TX_DAC_PLL_LOCK,
98	Radio3_TX_DAC_RESET,
99	Radio3_SHDN_external,
100	Radio3_TxEn_external,
101	Radio3_RxEn_external,
102	Radio3_RxHP_external,
103	Radio3_TxGain,
104	Radio3_TxStart,
105	Radio4_SHDN,
106	Radio4_TxEn,
107	Radio4_RxEn,
108	Radio4_RxHP,
109	Radio4_LD,
110	Radio4_24PA,
111	Radio4_5PA,
112	Radio4_ANTSW,
113	Radio4_LED,
114	Radio4_ADC_RX_DCS,
115	Radio4_ADC_RX_DFS,
116	Radio4_ADC_RX_OTRA,
117	Radio4_ADC_RX_OTRB,
118	Radio4_ADC_RX_PWDNA,
119	Radio4_ADC_RX_PWDNB,
120	Radio4_DIPSW,
121	Radio4_RSSI_ADC_CLAMP,
122	Radio4_RSSI_ADC_HIZ,
123	Radio4_RSSI_ADC_OTR,
124	Radio4_RSSI_ADC_SLEEP,
125	Radio4_RSSI_ADC_D,
126	Radio4_TX_DAC_PLL_LOCK,
127	Radio4_TX_DAC_RESET,
128	Radio4_SHDN_external,
129	Radio4_TxEn_external,
130	Radio4_RxEn_external,
131	Radio4_RxHP_external,
132	Radio4_TxGain,
133	Radio4_TxStart,
134
135	// -- Bus protocol ports, do not add to or delete
136	Bus2IP_Clk, // Bus to IP clock
137	Bus2IP_Reset, // Bus to IP reset
138	Bus2IP_Data, // Bus to IP data bus for user logic
139	Bus2IP_BE, // Bus to IP byte enables for user logic
140	Bus2IP_RdCE, // Bus to IP read chip enable for user logic
141	Bus2IP_WrCE, // Bus to IP write chip enable for user logic
142	IP2Bus_Data, // IP to Bus data bus for user logic
143	IP2Bus_Ack, // IP to Bus acknowledgement
144	IP2Bus_Retry, // IP to Bus retry response
145	IP2Bus_Error, // IP to Bus error response
146	IP2Bus_ToutSup // IP to Bus timeout suppress
147	); // user_logic
148
149
150	// -- Bus protocol parameters, do not add to or delete
151	parameter C_DWIDTH = 32;
152	parameter C_NUM_CE = 17;
153
154	output spi_clk;
155	output data_out;
156	output Radio1_cs;
157	output Radio2_cs;
158	output Radio3_cs;
159	output Radio4_cs;
160	output Dac1_cs;
161	output Dac2_cs;
162	output Dac3_cs;
163	output Dac4_cs;
164
165	output Radio1_SHDN;
166	output Radio1_TxEn;
167	output Radio1_RxEn;
168	output Radio1_RxHP;
169	input Radio1_LD;
170	output Radio1_24PA;
171	output Radio1_5PA;
172	output [0 : 1] Radio1_ANTSW;
173	output [0 : 2] Radio1_LED;
174	output Radio1_ADC_RX_DCS;
175	output Radio1_ADC_RX_DFS;
176	input Radio1_ADC_RX_OTRA;
177	input Radio1_ADC_RX_OTRB;
178	output Radio1_ADC_RX_PWDNA;
179	output Radio1_ADC_RX_PWDNB;
180	input [0 : 3] Radio1_DIPSW;
181	output Radio1_RSSI_ADC_CLAMP;
182	output Radio1_RSSI_ADC_HIZ;
183	input Radio1_RSSI_ADC_OTR;
184	output Radio1_RSSI_ADC_SLEEP;
185	input [0 : 9] Radio1_RSSI_ADC_D;
186	input Radio1_TX_DAC_PLL_LOCK;
187	output Radio1_TX_DAC_RESET;
188	input Radio1_SHDN_external;
189	input Radio1_TxEn_external;
190	input Radio1_RxEn_external;
191	input Radio1_RxHP_external;
192	output [0 : 5] Radio1_TxGain;
193	output Radio1_TxStart;
194	output Radio2_SHDN;
195	output Radio2_TxEn;
196	output Radio2_RxEn;
197	output Radio2_RxHP;
198	input Radio2_LD;
199	output Radio2_24PA;
200	output Radio2_5PA;
201	output [0 : 1] Radio2_ANTSW;
202	output [0 : 2] Radio2_LED;
203	output Radio2_ADC_RX_DCS;
204	output Radio2_ADC_RX_DFS;
205	input Radio2_ADC_RX_OTRA;
206	input Radio2_ADC_RX_OTRB;
207	output Radio2_ADC_RX_PWDNA;
208	output Radio2_ADC_RX_PWDNB;
209	input [0 : 3] Radio2_DIPSW;
210	output Radio2_RSSI_ADC_CLAMP;
211	output Radio2_RSSI_ADC_HIZ;
212	input Radio2_RSSI_ADC_OTR;
213	output Radio2_RSSI_ADC_SLEEP;
214	input [0 : 9] Radio2_RSSI_ADC_D;
215	input Radio2_TX_DAC_PLL_LOCK;
216	output Radio2_TX_DAC_RESET;
217	input Radio2_SHDN_external;
218	input Radio2_TxEn_external;
219	input Radio2_RxEn_external;
220	input Radio2_RxHP_external;
221	output [0 : 5] Radio2_TxGain;
222	output Radio2_TxStart;
223	output Radio3_SHDN;
224	output Radio3_TxEn;
225	output Radio3_RxEn;
226	output Radio3_RxHP;
227	input Radio3_LD;
228	output Radio3_24PA;
229	output Radio3_5PA;
230	output [0 : 1] Radio3_ANTSW;
231	output [0 : 2] Radio3_LED;
232	output Radio3_ADC_RX_DCS;
233	output Radio3_ADC_RX_DFS;
234	input Radio3_ADC_RX_OTRA;
235	input Radio3_ADC_RX_OTRB;
236	output Radio3_ADC_RX_PWDNA;
237	output Radio3_ADC_RX_PWDNB;
238	input [0 : 3] Radio3_DIPSW;
239	output Radio3_RSSI_ADC_CLAMP;
240	output Radio3_RSSI_ADC_HIZ;
241	input Radio3_RSSI_ADC_OTR;
242	output Radio3_RSSI_ADC_SLEEP;
243	input [0 : 9] Radio3_RSSI_ADC_D;
244	input Radio3_TX_DAC_PLL_LOCK;
245	output Radio3_TX_DAC_RESET;
246	input Radio3_SHDN_external;
247	input Radio3_TxEn_external;
248	input Radio3_RxEn_external;
249	input Radio3_RxHP_external;
250	output [0 : 5] Radio3_TxGain;
251	output Radio3_TxStart;
252	output Radio4_SHDN;
253	output Radio4_TxEn;
254	output Radio4_RxEn;
255	output Radio4_RxHP;
256	input Radio4_LD;
257	output Radio4_24PA;
258	output Radio4_5PA;
259	output [0 : 1] Radio4_ANTSW;
260	output [0 : 2] Radio4_LED;
261	output Radio4_ADC_RX_DCS;
262	output Radio4_ADC_RX_DFS;
263	input Radio4_ADC_RX_OTRA;
264	input Radio4_ADC_RX_OTRB;
265	output Radio4_ADC_RX_PWDNA;
266	output Radio4_ADC_RX_PWDNB;
267	input [0 : 3] Radio4_DIPSW;
268	output Radio4_RSSI_ADC_CLAMP;
269	output Radio4_RSSI_ADC_HIZ;
270	input Radio4_RSSI_ADC_OTR;
271	output Radio4_RSSI_ADC_SLEEP;
272	input [0 : 9] Radio4_RSSI_ADC_D;
273	input Radio4_TX_DAC_PLL_LOCK;
274	output Radio4_TX_DAC_RESET;
275	input Radio4_SHDN_external;
276	input Radio4_TxEn_external;
277	input Radio4_RxEn_external;
278	input Radio4_RxHP_external;
279	output [0 : 5] Radio4_TxGain;
280	output Radio4_TxStart;
281
282
283	// -- Bus protocol ports, do not add to or delete
284	input Bus2IP_Clk;
285	input Bus2IP_Reset;
286	input [0 : C_DWIDTH-1] Bus2IP_Data;
287	input [0 : C_DWIDTH/8-1] Bus2IP_BE;
288	input [0 : C_NUM_CE-1] Bus2IP_RdCE;
289	input [0 : C_NUM_CE-1] Bus2IP_WrCE;
290	output [0 : C_DWIDTH-1] IP2Bus_Data;
291	output IP2Bus_Ack;
292	output IP2Bus_Retry;
293	output IP2Bus_Error;
294	output IP2Bus_ToutSup;
295
296	// Nets for user logic slave model s/w accessible register example
297	reg [0 : C_DWIDTH-1] slv_reg0;
298	reg [0 : C_DWIDTH-1] slv_reg1;
299	reg [0 : C_DWIDTH-1] slv_reg2;
300	reg [0 : C_DWIDTH-1] slv_reg3;
301	reg [0 : C_DWIDTH-1] slv_reg4;
302	reg [0 : C_DWIDTH-1] slv_reg5;
303	reg [0 : C_DWIDTH-1] slv_reg6;
304	reg [0 : C_DWIDTH-1] slv_reg7;
305	reg [0 : C_DWIDTH-1] slv_reg8;
306	reg [0 : C_DWIDTH-1] slv_reg9;
307	reg [0 : C_DWIDTH-1] slv_reg10;
308	reg [0 : C_DWIDTH-1] slv_reg11;
309	reg [0 : C_DWIDTH-1] slv_reg12;
310	reg [0 : C_DWIDTH-1] slv_reg13;
311	reg [0 : C_DWIDTH-1] slv_reg14;
312	reg [0 : C_DWIDTH-1] slv_reg15;
313	reg [0 : C_DWIDTH-1] slv_reg16;
314	wire [0 : 16] slv_reg_write_select;
315	wire [0 : 16] slv_reg_read_select;
316	reg [0 : C_DWIDTH-1] slv_ip2bus_data;
317	wire slv_read_ack;
318	wire slv_write_ack;
319	integer byte_index, bit_index;
320
321	// Nets for SPI interface connected to user_logic
322	wire [7:0] ss_pad_o;
323	wire mytip;
324	wire [13:0] reg_ctrl;
325	wire [7:0] reg_ss;
326	wire reg_divider;
327	wire [17:0] reg_tx;
328
329	// Intermediate signals for transmit gain state machine
330	wire Radio1_PowerAmpEnable, Radio1_swTxEn, Radio1_sw24PAEn, Radio1_sw5PAEn;
331	wire Radio2_PowerAmpEnable, Radio2_swTxEn, Radio2_sw24PAEn, Radio2_sw5PAEn;
332	wire Radio3_PowerAmpEnable, Radio3_swTxEn, Radio3_sw24PAEn, Radio3_sw5PAEn;
333	wire Radio4_PowerAmpEnable, Radio4_swTxEn, Radio4_sw24PAEn, Radio4_sw5PAEn;
334
335	// Internal signals for calculating Tx gains
336	wire [0:5] Radio1_TargetTxGain, Radio2_TargetTxGain, Radio3_TargetTxGain, Radio4_TargetTxGain;
337	wire [0:3] Radio1_TxGainStep, Radio2_TxGainStep, Radio3_TxGainStep, Radio4_TxGainStep;
338	wire [0:3] Radio1_TxGainTimeStep, Radio2_TxGainTimeStep, Radio3_TxGainTimeStep, Radio4_TxGainTimeStep;
339
340	// Internal signals setting delays used to control Tx timing
341	wire [0:7] Radio1_GainRampThresh, Radio1_PAThresh, Radio1_TxEnThresh, Radio1_TxStartThresh;
342	wire [0:7] Radio2_GainRampThresh, Radio2_PAThresh, Radio2_TxEnThresh, Radio2_TxStartThresh;
343	wire [0:7] Radio3_GainRampThresh, Radio3_PAThresh, Radio3_TxEnThresh, Radio3_TxStartThresh;
344	wire [0:7] Radio4_GainRampThresh, Radio4_PAThresh, Radio4_TxEnThresh, Radio4_TxStartThresh;
345
346
347	// SPI Interface signals
348	assign Radio1_cs = ss_pad_o[0];
349	assign Radio2_cs = ss_pad_o[1];
350	assign Radio3_cs = ss_pad_o[2];
351	assign Radio4_cs = ss_pad_o[3];
352	assign Dac1_cs = ss_pad_o[4];
353	assign Dac2_cs = ss_pad_o[5];
354	assign Dac3_cs = ss_pad_o[6];
355	assign Dac4_cs = ss_pad_o[7];
356
357	assign reg_ctrl = slv_reg5[18:31];
358	assign reg_divider = slv_reg6[31];
359	assign reg_ss = slv_reg7[24:31];
360	assign reg_tx = slv_reg8[14:31];
361
362	// Instantiate the SPI controller top-level
363	spi_top spi_top(
364	.opb_clk_i(Bus2IP_Clk),
365	.opb_rst_i(Bus2IP_Reset),
366	.reg_ctrl(reg_ctrl),
367	.reg_ss(reg_ss),
368	.reg_divider(reg_divider),
369	.reg_tx(reg_tx),
370	.ctrlwrite(Bus2IP_WrCE[5]),
371	.busval(Bus2IP_Data[23]),
372	.go(mytip),
373	.ss_pad_o(ss_pad_o),
374	.sclk_pad_o(spi_clk),
375	.mosi_pad_o(data_out)
376	);
377
378
379	//// Signals and Tx state machine for Radio 1
380
381	assign Radio1_SHDN = (slv_reg0[27])?~Radio1_SHDN_external:~slv_reg0[31];
382	assign Radio1_swTxEn = (slv_reg0[19])?Radio1_TxEn_external:slv_reg0[23];
383	assign Radio1_RxEn = (slv_reg0[11])?Radio1_RxEn_external:slv_reg0[15];
384	assign Radio1_RxHP = (slv_reg0[3])?Radio1_RxHP_external:slv_reg0[7];
385
386	assign Radio1_sw24PAEn = slv_reg1[31];
387	assign Radio1_sw5PAEn = slv_reg1[27];
388
389	assign Radio1_24PA = ~(Radio1_sw24PAEn & Radio1_PowerAmpEnable); //active low output
390	assign Radio1_5PA = ~(Radio1_sw5PAEn & Radio1_PowerAmpEnable); //active low output
391
392	assign Radio1_ANTSW[0] = (slv_reg0[19])? Radio1_TxEn_external : slv_reg1[15]; //slv_reg1[15];
393	assign Radio1_ANTSW[1] = (slv_reg0[11])? Radio1_RxEn_external : ~slv_reg1[15]; //~slv_reg1[15];
394	assign Radio1_ADC_RX_DCS = slv_reg1[7];
395	assign Radio1_LED[0] = Radio1_RxEn;
396	assign Radio1_LED[1] = Radio1_TxEn;
397	assign Radio1_LED[2] = ~Radio1_LD;
398	assign Radio1_ADC_RX_PWDNA = slv_reg2[23];
399	assign Radio1_ADC_RX_PWDNB = slv_reg2[19];
400	assign Radio1_RSSI_ADC_SLEEP = slv_reg2[15];
401	assign Radio1_TX_DAC_RESET = slv_reg1[11];
402
403	assign Radio1_ADC_RX_DFS = 1'b1; //slv_reg1[3];
404	assign Radio1_RSSI_ADC_CLAMP = 1'b0; //slv_reg2[3];
405	assign Radio1_RSSI_ADC_HIZ = 1'b0; //slv_reg2[7];
406
407	//Read the user register for programmed target Tx gain
408	assign Radio1_TargetTxGain = slv_reg9[0:5];
409
410	//Read the user regsiter for programmed Tx gain ramp increment
411	assign Radio1_TxGainStep = slv_reg9[6:9];
412
413	//Read the user register for programmed delay between gain steps
414	assign Radio1_TxGainTimeStep = slv_reg9[10:13];
415
416	//slv_reg9[14:31] available for future use
417
418	//Read the user registers for the the delays before each Tx event
419	assign Radio1_GainRampThresh = slv_reg13[0:7];
420	assign Radio1_PAThresh = slv_reg13[8:15];
421	assign Radio1_TxEnThresh = slv_reg13[16:23];
422	assign Radio1_TxStartThresh = slv_reg13[24:31];
423
424	radio_controller_TxTiming Radio1_TxTiming (
425	.clk(Bus2IP_Clk),
426	.reset(Bus2IP_Reset),
427
428	.Tx_swEnable(Radio1_swTxEn),
429
430	.TxGain_target(Radio1_TargetTxGain),
431	.TxGain_rampGainStep(Radio1_TxGainStep),
432	.TxGain_rampTimeStep(Radio1_TxGainTimeStep),
433
434	.dly_hwTxEn(Radio1_TxEnThresh),
435	.dly_TxStart(Radio1_TxStartThresh),
436	.dly_PowerAmpEn(Radio1_PAThresh),
437	.dly_RampGain(Radio1_GainRampThresh),
438
439	.hw_TxEn(Radio1_TxEn),
440	.hw_TxGain(Radio1_TxGain),
441	.hw_PAEn(Radio1_PowerAmpEnable),
442	.hw_TxStart(Radio1_TxStart)
443	);
444
445
446	//// Signals and Tx state machine for Radio 2
447
448	assign Radio2_SHDN = (slv_reg0[26])?~Radio2_SHDN_external:~slv_reg0[30];
449	assign Radio2_swTxEn = (slv_reg0[18])?Radio2_TxEn_external:slv_reg0[22];
450	assign Radio2_RxEn = (slv_reg0[10])?Radio2_RxEn_external:slv_reg0[14];
451	assign Radio2_RxHP = (slv_reg0[2])?Radio2_RxHP_external:slv_reg0[6];
452
453	assign Radio2_sw24PAEn = slv_reg1[30];
454	assign Radio2_sw5PAEn = slv_reg1[26];
455
456	assign Radio2_24PA = ~(Radio2_sw24PAEn & Radio2_PowerAmpEnable); //active low output
457	assign Radio2_5PA = ~(Radio2_sw5PAEn & Radio2_PowerAmpEnable); //active low output
458
459	assign Radio2_ANTSW[0] = (slv_reg0[18])? Radio2_TxEn_external : slv_reg1[14]; //slv_reg1[14];
460	assign Radio2_ANTSW[1] = (slv_reg0[10])? Radio2_RxEn_external : ~slv_reg1[14]; //~slv_reg1[14];
461	assign Radio2_ADC_RX_DCS = slv_reg1[6];
462	assign Radio2_LED[0] = Radio2_RxEn;
463	assign Radio2_LED[1] = Radio2_TxEn;
464	assign Radio2_LED[2] = ~Radio2_LD;
465	assign Radio2_ADC_RX_PWDNA = slv_reg2[22];
466	assign Radio2_ADC_RX_PWDNB = slv_reg2[18];
467	assign Radio2_RSSI_ADC_SLEEP = slv_reg2[14];
468	assign Radio2_TX_DAC_RESET = slv_reg1[10];
469
470	assign Radio2_ADC_RX_DFS = 1'b1; //slv_reg1[2];
471	assign Radio2_RSSI_ADC_CLAMP = 1'b0; //slv_reg2[2];
472	assign Radio2_RSSI_ADC_HIZ = 1'b0; //slv_reg2[6];
473
474	//Read the user register for programmed target Tx gain
475	assign Radio2_TargetTxGain = slv_reg10[0:5];
476
477	//Read the user regsiter for programmed Tx gain ramp increment
478	assign Radio2_TxGainStep = slv_reg10[6:9];
479
480	//Read the user register for programmed delay between gain steps
481	assign Radio2_TxGainTimeStep = slv_reg10[10:13];
482
483	//slv_reg10[14:31] available for future use
484
485	//Read the user registers for the the delays before each Tx event
486	assign Radio2_GainRampThresh = slv_reg14[0:7];
487	assign Radio2_PAThresh = slv_reg14[8:15];
488	assign Radio2_TxEnThresh = slv_reg14[16:23];
489	assign Radio2_TxStartThresh = slv_reg14[24:31];
490
491	radio_controller_TxTiming Radio2_TxTiming (
492	.clk(Bus2IP_Clk),
493	.reset(Bus2IP_Reset),
494
495	.Tx_swEnable(Radio2_swTxEn),
496
497	.TxGain_target(Radio2_TargetTxGain),
498	.TxGain_rampGainStep(Radio2_TxGainStep),
499	.TxGain_rampTimeStep(Radio2_TxGainTimeStep),
500
501	.dly_hwTxEn(Radio2_TxEnThresh),
502	.dly_TxStart(Radio2_TxStartThresh),
503	.dly_PowerAmpEn(Radio2_PAThresh),
504	.dly_RampGain(Radio2_GainRampThresh),
505
506	.hw_TxEn(Radio2_TxEn),
507	.hw_TxGain(Radio2_TxGain),
508	.hw_PAEn(Radio2_PowerAmpEnable),
509	.hw_TxStart(Radio2_TxStart)
510	);
511
512
513	//// Signals and Tx state machine for Radio 3
514
515	assign Radio3_SHDN = (slv_reg0[25])?~Radio3_SHDN_external:~slv_reg0[29];
516	assign Radio3_swTxEn = (slv_reg0[17])?Radio3_TxEn_external:slv_reg0[21];
517	assign Radio3_RxEn = (slv_reg0[9])?Radio3_RxEn_external:slv_reg0[13];
518	assign Radio3_RxHP = (slv_reg0[1])?Radio3_RxHP_external:slv_reg0[5];
519
520	assign Radio3_sw24PAEn = slv_reg1[29];
521	assign Radio3_sw5PAEn = slv_reg1[25];
522
523	assign Radio3_24PA = ~(Radio3_sw24PAEn & Radio3_PowerAmpEnable); //active low output
524	assign Radio3_5PA = ~(Radio3_sw5PAEn & Radio3_PowerAmpEnable); //active low output
525
526	assign Radio3_ANTSW[0] = (slv_reg0[17])? Radio3_TxEn_external : slv_reg1[13]; //slv_reg1[13];
527	assign Radio3_ANTSW[1] = (slv_reg0[9])? Radio3_RxEn_external : ~slv_reg1[13]; //~slv_reg1[13];
528	assign Radio3_ADC_RX_DCS = slv_reg1[5];
529	assign Radio3_LED[0] = Radio3_RxEn;
530	assign Radio3_LED[1] = Radio3_TxEn;
531	assign Radio3_LED[2] = ~Radio3_LD;
532	assign Radio3_ADC_RX_PWDNA = slv_reg2[21];
533	assign Radio3_ADC_RX_PWDNB = slv_reg2[17];
534	assign Radio3_RSSI_ADC_SLEEP = slv_reg2[13];
535	assign Radio3_TX_DAC_RESET = slv_reg1[9];
536
537	assign Radio3_ADC_RX_DFS = 1'b1; //slv_reg1[1];
538	assign Radio3_RSSI_ADC_CLAMP = 1'b0; //slv_reg2[1];
539	assign Radio3_RSSI_ADC_HIZ = 1'b0; //slv_reg2[5];
540
541	//Read the user register for programmed target Tx gain
542	assign Radio3_TargetTxGain = slv_reg11[0:5];
543
544	//Read the user regsiter for programmed Tx gain ramp increment
545	assign Radio3_TxGainStep = slv_reg11[6:9];
546
547	//Read the user register for programmed delay between gain steps
548	assign Radio3_TxGainTimeStep = slv_reg11[10:13];
549
550	//slv_reg11[14:31] available for future use
551
552	//Read the user registers for the the delays before each Tx event
553	assign Radio3_GainRampThresh = slv_reg15[0:7];
554	assign Radio3_PAThresh = slv_reg15[8:15];
555	assign Radio3_TxEnThresh = slv_reg15[16:23];
556	assign Radio3_TxStartThresh = slv_reg15[24:31];
557
558	radio_controller_TxTiming Radio3_TxTiming (
559	.clk(Bus2IP_Clk),
560	.reset(Bus2IP_Reset),
561
562	.Tx_swEnable(Radio3_swTxEn),
563
564	.TxGain_target(Radio3_TargetTxGain),
565	.TxGain_rampGainStep(Radio3_TxGainStep),
566	.TxGain_rampTimeStep(Radio3_TxGainTimeStep),
567
568	.dly_hwTxEn(Radio3_TxEnThresh),
569	.dly_TxStart(Radio3_TxStartThresh),
570	.dly_PowerAmpEn(Radio3_PAThresh),
571	.dly_RampGain(Radio3_GainRampThresh),
572
573	.hw_TxEn(Radio3_TxEn),
574	.hw_TxGain(Radio3_TxGain),
575	.hw_PAEn(Radio3_PowerAmpEnable),
576	.hw_TxStart(Radio3_TxStart)
577	);
578
579
580	//// Signals and Tx state machine for Radio 4
581
582	assign Radio4_SHDN = (slv_reg0[24])?~Radio4_SHDN_external:~slv_reg0[28];
583	assign Radio4_swTxEn = (slv_reg0[16])?Radio4_TxEn_external:slv_reg0[20];
584	assign Radio4_RxEn = (slv_reg0[8])?Radio4_RxEn_external:slv_reg0[12];
585	assign Radio4_RxHP = (slv_reg0[0])?Radio4_RxHP_external:slv_reg0[4];
586
587	assign Radio4_sw24PAEn = slv_reg1[28];
588	assign Radio4_sw5PAEn = slv_reg1[24];
589
590	assign Radio4_24PA = ~(Radio4_sw24PAEn & Radio4_PowerAmpEnable); //active low output
591	assign Radio4_5PA = ~(Radio4_sw5PAEn & Radio4_PowerAmpEnable); //active low output
592
593	assign Radio4_ANTSW[0] = (slv_reg0[16])? Radio4_TxEn_external : slv_reg1[12]; //slv_reg1[12];
594	assign Radio4_ANTSW[1] = (slv_reg0[8])? Radio4_RxEn_external : ~slv_reg1[12]; //~slv_reg1[12];
595	assign Radio4_ADC_RX_DCS = slv_reg1[4];
596	assign Radio4_LED[0] = Radio4_RxEn;
597	assign Radio4_LED[1] = Radio4_TxEn;
598	assign Radio4_LED[2] = ~Radio4_LD;
599	assign Radio4_ADC_RX_PWDNA = slv_reg2[20];
600	assign Radio4_ADC_RX_PWDNB = slv_reg2[16];
601	assign Radio4_RSSI_ADC_SLEEP = slv_reg2[12];
602	assign Radio4_TX_DAC_RESET = slv_reg1[8];
603
604	assign Radio4_ADC_RX_DFS = 1'b1; //slv_reg1[0];
605	assign Radio4_RSSI_ADC_CLAMP = 1'b0; //slv_reg2[0];
606	assign Radio4_RSSI_ADC_HIZ = 1'b0; //slv_reg2[4];
607
608	//Read the user register for programmed target Tx gain
609	assign Radio4_TargetTxGain = slv_reg12[0:5];
610
611	//Read the user regsiter for programmed Tx gain ramp increment
612	assign Radio4_TxGainStep = slv_reg12[6:9];
613
614	//Read the user register for programmed delay between gain steps
615	assign Radio4_TxGainTimeStep = slv_reg12[10:13];
616
617	//slv_reg12[14:31] available for future use
618
619	//Read the user registers for the the delays before each Tx event
620	assign Radio4_GainRampThresh = slv_reg16[0:7];
621	assign Radio4_PAThresh = slv_reg16[8:15];
622	assign Radio4_TxEnThresh = slv_reg16[16:23];
623	assign Radio4_TxStartThresh = slv_reg16[24:31];
624
625	radio_controller_TxTiming Radio4_TxTiming (
626	.clk(Bus2IP_Clk),
627	.reset(Bus2IP_Reset),
628
629	.Tx_swEnable(Radio4_swTxEn),
630
631	.TxGain_target(Radio4_TargetTxGain),
632	.TxGain_rampGainStep(Radio4_TxGainStep),
633	.TxGain_rampTimeStep(Radio4_TxGainTimeStep),
634
635	.dly_hwTxEn(Radio4_TxEnThresh),
636	.dly_TxStart(Radio4_TxStartThresh),
637	.dly_PowerAmpEn(Radio4_PAThresh),
638	.dly_RampGain(Radio4_GainRampThresh),
639
640	.hw_TxEn(Radio4_TxEn),
641	.hw_TxGain(Radio4_TxGain),
642	.hw_PAEn(Radio4_PowerAmpEnable),
643	.hw_TxStart(Radio4_TxStart)
644	);
645
646
647	assign
648	slv_reg_write_select = Bus2IP_WrCE[0:16],
649	slv_reg_read_select = Bus2IP_RdCE[0:16],
650	slv_write_ack = Bus2IP_WrCE[0] \|\| Bus2IP_WrCE[1] \|\| Bus2IP_WrCE[2] \|\| Bus2IP_WrCE[3] \|\| Bus2IP_WrCE[4] \|\| Bus2IP_WrCE[5] \|\| Bus2IP_WrCE[6] \|\| Bus2IP_WrCE[7] \|\| Bus2IP_WrCE[8] \|\| Bus2IP_WrCE[9] \|\| Bus2IP_WrCE[10] \|\| Bus2IP_WrCE[11] \|\| Bus2IP_WrCE[12] \|\| Bus2IP_WrCE[13] \|\| Bus2IP_WrCE[14] \|\| Bus2IP_WrCE[15] \|\| Bus2IP_WrCE[16],
651	slv_read_ack = Bus2IP_RdCE[0] \|\| Bus2IP_RdCE[1] \|\| Bus2IP_RdCE[2] \|\| Bus2IP_RdCE[3] \|\| Bus2IP_RdCE[4] \|\| Bus2IP_RdCE[5] \|\| Bus2IP_RdCE[6] \|\| Bus2IP_RdCE[7] \|\| Bus2IP_RdCE[8] \|\| Bus2IP_RdCE[9] \|\| Bus2IP_RdCE[10] \|\| Bus2IP_RdCE[11] \|\| Bus2IP_RdCE[12] \|\| Bus2IP_RdCE[13] \|\| Bus2IP_RdCE[14] \|\| Bus2IP_RdCE[15] \|\| Bus2IP_RdCE[16];
652
653	// implement slave model register(s)
654	always @( posedge Bus2IP_Clk )
655	begin: SLAVE_REG_WRITE_PROC
656
657	if ( Bus2IP_Reset == 1 )
658	begin
659	slv_reg0 <= 0;
660	slv_reg1 <= 0;
661	slv_reg2 <= 0;
662	slv_reg3 <= 0;
663	slv_reg4 <= 0;
664	slv_reg5 <= 0;
665	slv_reg6 <= 0;
666	slv_reg7 <= 0;
667	slv_reg8 <= 0;
668	slv_reg9 <= {14'h3fff, 22'h0}; //Gain increment, targets & delays all default to max values
669	slv_reg10 <= {14'h3fff, 22'h0};
670	slv_reg11 <= {14'h3fff, 22'h0};
671	slv_reg12 <= {14'h3fff, 22'h0};
672	slv_reg13 <= 0;
673	slv_reg14 <= 0;
674	slv_reg15 <= 0;
675	slv_reg16 <= 0;
676	end
677	else
678	case ( slv_reg_write_select )
679	17'b10000000000000000 :
680	for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
681	if ( Bus2IP_BE[byte_index] == 1 )
682	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
683	slv_reg0[bit_index] <= Bus2IP_Data[bit_index];
684	17'b01000000000000000 :
685	for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
686	if ( Bus2IP_BE[byte_index] == 1 )
687	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
688	slv_reg1[bit_index] <= Bus2IP_Data[bit_index];
689	17'b00100000000000000 :
690	for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
691	if ( Bus2IP_BE[byte_index] == 1 )
692	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
693	slv_reg2[bit_index] <= Bus2IP_Data[bit_index];
694	17'b00010000000000000 :
695	for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
696	if ( Bus2IP_BE[byte_index] == 1 )
697	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
698	slv_reg3[bit_index] <= Bus2IP_Data[bit_index];
699	17'b00001000000000000 :
700	for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
701	if ( Bus2IP_BE[byte_index] == 1 )
702	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
703	slv_reg4[bit_index] <= Bus2IP_Data[bit_index];
704	17'b00000100000000000 :
705	for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
706	if ( Bus2IP_BE[byte_index] == 1 )
707	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
708	slv_reg5[bit_index] <= Bus2IP_Data[bit_index];
709	17'b00000010000000000 :
710	for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
711	if ( Bus2IP_BE[byte_index] == 1 )
712	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
713	slv_reg6[bit_index] <= Bus2IP_Data[bit_index];
714	17'b00000001000000000 :
715	for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
716	if ( Bus2IP_BE[byte_index] == 1 )
717	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
718	slv_reg7[bit_index] <= Bus2IP_Data[bit_index];
719	17'b00000000100000000 :
720	for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
721	if ( Bus2IP_BE[byte_index] == 1 )
722	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
723	slv_reg8[bit_index] <= Bus2IP_Data[bit_index];
724	17'b00000000010000000 :
725	for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
726	if ( Bus2IP_BE[byte_index] == 1 )
727	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
728	slv_reg9[bit_index] <= Bus2IP_Data[bit_index];
729	17'b00000000001000000 :
730	for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
731	if ( Bus2IP_BE[byte_index] == 1 )
732	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
733	slv_reg10[bit_index] <= Bus2IP_Data[bit_index];
734	17'b00000000000100000 :
735	for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
736	if ( Bus2IP_BE[byte_index] == 1 )
737	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
738	slv_reg11[bit_index] <= Bus2IP_Data[bit_index];
739	17'b00000000000010000 :
740	for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
741	if ( Bus2IP_BE[byte_index] == 1 )
742	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
743	slv_reg12[bit_index] <= Bus2IP_Data[bit_index];
744	17'b00000000000001000 :
745	for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
746	if ( Bus2IP_BE[byte_index] == 1 )
747	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
748	slv_reg13[bit_index] <= Bus2IP_Data[bit_index];
749	17'b00000000000000100 :
750	for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
751	if ( Bus2IP_BE[byte_index] == 1 )
752	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
753	slv_reg14[bit_index] <= Bus2IP_Data[bit_index];
754	17'b00000000000000010 :
755	for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
756	if ( Bus2IP_BE[byte_index] == 1 )
757	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
758	slv_reg15[bit_index] <= Bus2IP_Data[bit_index];
759	17'b00000000000000001 :
760	for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
761	if ( Bus2IP_BE[byte_index] == 1 )
762	for ( bit_index = byte_index8; bit_index <= byte_index8+7; bit_index = bit_index+1 )
763	slv_reg16[bit_index] <= Bus2IP_Data[bit_index];
764	default : ;
765	endcase
766
767	end // SLAVE_REG_WRITE_PROC
768
769	// implement slave model register read mux
770	always @( slv_reg_read_select or slv_reg0 or slv_reg1 or slv_reg2 or slv_reg3 or slv_reg4 or slv_reg5 or slv_reg6 or slv_reg7 or slv_reg8 or slv_reg9 or slv_reg10 or slv_reg11 or slv_reg12 or slv_reg13 or slv_reg14 or slv_reg15 or slv_reg16 )
771	begin: SLAVE_REG_READ_PROC
772
773	case ( slv_reg_read_select )
774	17'b10000000000000000 : slv_ip2bus_data <= slv_reg0;
775	17'b01000000000000000 : slv_ip2bus_data <= {Radio4_ADC_RX_DFS,
776	Radio3_ADC_RX_DFS,
777	Radio2_ADC_RX_DFS,
778	Radio1_ADC_RX_DFS,
779	slv_reg1[4:19],
780	Radio4_LD,
781	Radio3_LD,
782	Radio2_LD,
783	Radio1_LD,
784	slv_reg1[24:31]};
785	17'b00100000000000000 : slv_ip2bus_data <= {Radio4_RSSI_ADC_CLAMP,
786	Radio3_RSSI_ADC_CLAMP,
787	Radio2_RSSI_ADC_CLAMP,
788	Radio1_RSSI_ADC_CLAMP,
789	Radio4_RSSI_ADC_HIZ,
790	Radio3_RSSI_ADC_HIZ,
791	Radio2_RSSI_ADC_HIZ,
792	Radio1_RSSI_ADC_HIZ,
793	Radio4_RSSI_ADC_OTR,
794	Radio3_RSSI_ADC_OTR,
795	Radio2_RSSI_ADC_OTR,
796	Radio1_RSSI_ADC_OTR,
797	slv_reg4[12:23],
798	Radio4_ADC_RX_OTRB,
799	Radio3_ADC_RX_OTRB,
800	Radio2_ADC_RX_OTRB,
801	Radio1_ADC_RX_OTRB,
802	Radio4_ADC_RX_OTRA,
803	Radio3_ADC_RX_OTRA,
804	Radio2_ADC_RX_OTRA,
805	Radio1_ADC_RX_OTRA};
806	17'b00010000000000000 : slv_ip2bus_data <= {Radio2_TX_DAC_PLL_LOCK,
807	slv_reg3[1],
808	Radio2_DIPSW[3],
809	Radio2_DIPSW[2],
810	Radio2_DIPSW[1],
811	Radio2_DIPSW[0],
812	Radio2_RSSI_ADC_D,
813	Radio1_TX_DAC_PLL_LOCK,
814	slv_reg3[17],
815	Radio1_DIPSW[3],
816	Radio1_DIPSW[2],
817	Radio1_DIPSW[1],
818	Radio1_DIPSW[0],
819	Radio1_RSSI_ADC_D};
820	17'b00001000000000000 : slv_ip2bus_data <= {Radio4_TX_DAC_PLL_LOCK,
821	slv_reg4[1],
822	Radio4_DIPSW[3],
823	Radio4_DIPSW[2],
824	Radio4_DIPSW[1],
825	Radio4_DIPSW[0],
826	Radio4_RSSI_ADC_D,
827	Radio3_TX_DAC_PLL_LOCK,
828	slv_reg4[17],
829	Radio3_DIPSW[3],
830	Radio3_DIPSW[2],
831	Radio3_DIPSW[1],
832	Radio3_DIPSW[0],
833	Radio3_RSSI_ADC_D};
834	17'b00000100000000000 : slv_ip2bus_data <= {slv_reg5[0:22], mytip, slv_reg5[24:31]};
835	17'b00000010000000000 : slv_ip2bus_data <= slv_reg6;
836	17'b00000001000000000 : slv_ip2bus_data <= slv_reg7;
837	17'b00000000100000000 : slv_ip2bus_data <= slv_reg8;
838	17'b00000000010000000 : slv_ip2bus_data <= slv_reg9;
839	17'b00000000001000000 : slv_ip2bus_data <= slv_reg10;
840	17'b00000000000100000 : slv_ip2bus_data <= slv_reg11;
841	17'b00000000000010000 : slv_ip2bus_data <= slv_reg12;
842	17'b00000000000001000 : slv_ip2bus_data <= slv_reg13;
843	17'b00000000000000100 : slv_ip2bus_data <= slv_reg14;
844	17'b00000000000000010 : slv_ip2bus_data <= slv_reg15;
845	17'b00000000000000001 : slv_ip2bus_data <= slv_reg16;
846	default : slv_ip2bus_data <= 0;
847	endcase
848
849	end // SLAVE_REG_READ_PROC
850
851	// ------------------------------------------------------------
852	// Example code to drive IP to Bus signals
853	// ------------------------------------------------------------
854
855	assign IP2Bus_Data = slv_ip2bus_data;
856	assign IP2Bus_Ack = slv_write_ack \|\| slv_read_ack;
857	assign IP2Bus_Error = 0;
858	assign IP2Bus_Retry = 0;
859	assign IP2Bus_ToutSup = 0;
860
861	endmodule

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