1 | -- Copyright (c) 2006 Rice University |
---|
2 | -- All Rights Reserved |
---|
3 | -- This code is covered by the Rice-WARP license |
---|
4 | -- See http://warp.rice.edu/license/ for details |
---|
5 | |
---|
6 | ------------------------------------------------------------------------------ |
---|
7 | -- radio_controller.vhd - entity/architecture pair |
---|
8 | ------------------------------------------------------------------------------ |
---|
9 | |
---|
10 | library ieee; |
---|
11 | use ieee.std_logic_1164.all; |
---|
12 | use ieee.std_logic_arith.all; |
---|
13 | use ieee.std_logic_unsigned.all; |
---|
14 | |
---|
15 | library proc_common_v2_00_a; |
---|
16 | use proc_common_v2_00_a.proc_common_pkg.all; |
---|
17 | use proc_common_v2_00_a.ipif_pkg.all; |
---|
18 | library opb_ipif_v3_01_c; |
---|
19 | use opb_ipif_v3_01_c.all; |
---|
20 | |
---|
21 | library radio_controller_v1_10_a; |
---|
22 | use radio_controller_v1_10_a.all; |
---|
23 | |
---|
24 | ------------------------------------------------------------------------------ |
---|
25 | -- Entity section |
---|
26 | ------------------------------------------------------------------------------ |
---|
27 | -- Definition of Generics: |
---|
28 | -- C_BASEADDR -- User logic base address |
---|
29 | -- C_HIGHADDR -- User logic high address |
---|
30 | -- C_OPB_AWIDTH -- OPB address bus width |
---|
31 | -- C_OPB_DWIDTH -- OPB data bus width |
---|
32 | -- C_FAMILY -- Target FPGA architecture |
---|
33 | -- |
---|
34 | -- Definition of Ports: |
---|
35 | -- OPB_Clk -- OPB Clock |
---|
36 | -- OPB_Rst -- OPB Reset |
---|
37 | -- Sl_DBus -- Slave data bus |
---|
38 | -- Sl_errAck -- Slave error acknowledge |
---|
39 | -- Sl_retry -- Slave retry |
---|
40 | -- Sl_toutSup -- Slave timeout suppress |
---|
41 | -- Sl_xferAck -- Slave transfer acknowledge |
---|
42 | -- OPB_ABus -- OPB address bus |
---|
43 | -- OPB_BE -- OPB byte enable |
---|
44 | -- OPB_DBus -- OPB data bus |
---|
45 | -- OPB_RNW -- OPB read/not write |
---|
46 | -- OPB_select -- OPB select |
---|
47 | -- OPB_seqAddr -- OPB sequential address |
---|
48 | ------------------------------------------------------------------------------ |
---|
49 | |
---|
50 | entity radio_controller is |
---|
51 | generic |
---|
52 | ( |
---|
53 | -- DO NOT EDIT BELOW THIS LINE --------------------- |
---|
54 | -- Bus protocol parameters, do not add to or delete |
---|
55 | C_BASEADDR : std_logic_vector := X"00000000"; |
---|
56 | C_HIGHADDR : std_logic_vector := X"0000FFFF"; |
---|
57 | C_OPB_AWIDTH : integer := 32; |
---|
58 | C_OPB_DWIDTH : integer := 32; |
---|
59 | C_FAMILY : string := "virtex2p" |
---|
60 | -- DO NOT EDIT ABOVE THIS LINE --------------------- |
---|
61 | ); |
---|
62 | port |
---|
63 | ( |
---|
64 | -- ADD USER PORTS BELOW THIS LINE ------------------ |
---|
65 | |
---|
66 | spi_clk : out std_logic; |
---|
67 | data_out : out std_logic; |
---|
68 | radio1_cs : out std_logic; |
---|
69 | radio2_cs : out std_logic; |
---|
70 | radio3_cs : out std_logic; |
---|
71 | radio4_cs : out std_logic; |
---|
72 | dac1_cs : out std_logic; |
---|
73 | dac2_cs : out std_logic; |
---|
74 | dac3_cs : out std_logic; |
---|
75 | dac4_cs : out std_logic; |
---|
76 | radio1_SHDN : out std_logic; |
---|
77 | radio1_TxEn : out std_logic; |
---|
78 | radio1_RxEn : out std_logic; |
---|
79 | radio1_RxHP : out std_logic; |
---|
80 | radio1_LD : in std_logic; |
---|
81 | radio1_24PA : out std_logic; |
---|
82 | radio1_5PA : out std_logic; |
---|
83 | radio1_ANTSW : out std_logic_vector(0 to 1); |
---|
84 | radio1_LED : out std_logic_vector(0 to 2); |
---|
85 | radio1_ADC_RX_DCS : out std_logic; |
---|
86 | radio1_ADC_RX_DFS : out std_logic; |
---|
87 | radio1_ADC_RX_OTRA : in std_logic; |
---|
88 | radio1_ADC_RX_OTRB : in std_logic; |
---|
89 | radio1_ADC_RX_PWDNA : out std_logic; |
---|
90 | radio1_ADC_RX_PWDNB : out std_logic; |
---|
91 | radio1_DIPSW : in std_logic_vector(0 to 3); |
---|
92 | radio1_RSSI_ADC_CLAMP : out std_logic; |
---|
93 | radio1_RSSI_ADC_HIZ : out std_logic; |
---|
94 | radio1_RSSI_ADC_OTR : in std_logic; |
---|
95 | radio1_RSSI_ADC_SLEEP : out std_logic; |
---|
96 | radio1_RSSI_ADC_D : in std_logic_vector(0 to 9); |
---|
97 | radio1_TX_DAC_PLL_LOCK : in std_logic; |
---|
98 | radio1_TX_DAC_RESET : out std_logic; |
---|
99 | radio1_SHDN_external : in std_logic; |
---|
100 | radio1_TxEn_external : in std_logic; |
---|
101 | radio1_RxEn_external : in std_logic; |
---|
102 | radio1_RxHP_external : in std_logic; |
---|
103 | radio1_TxGain : out std_logic_vector(0 to 5); |
---|
104 | radio1_TxStart : out std_logic; |
---|
105 | radio2_SHDN : out std_logic; |
---|
106 | radio2_TxEn : out std_logic; |
---|
107 | radio2_RxEn : out std_logic; |
---|
108 | radio2_RxHP : out std_logic; |
---|
109 | radio2_LD : in std_logic; |
---|
110 | radio2_24PA : out std_logic; |
---|
111 | radio2_5PA : out std_logic; |
---|
112 | radio2_ANTSW : out std_logic_vector(0 to 1); |
---|
113 | radio2_LED : out std_logic_vector(0 to 2); |
---|
114 | radio2_ADC_RX_DCS : out std_logic; |
---|
115 | radio2_ADC_RX_DFS : out std_logic; |
---|
116 | radio2_ADC_RX_OTRA : in std_logic; |
---|
117 | radio2_ADC_RX_OTRB : in std_logic; |
---|
118 | radio2_ADC_RX_PWDNA : out std_logic; |
---|
119 | radio2_ADC_RX_PWDNB : out std_logic; |
---|
120 | radio2_DIPSW : in std_logic_vector(0 to 3); |
---|
121 | radio2_RSSI_ADC_CLAMP : out std_logic; |
---|
122 | radio2_RSSI_ADC_HIZ : out std_logic; |
---|
123 | radio2_RSSI_ADC_OTR : in std_logic; |
---|
124 | radio2_RSSI_ADC_SLEEP : out std_logic; |
---|
125 | radio2_RSSI_ADC_D : in std_logic_vector(0 to 9); |
---|
126 | radio2_TX_DAC_PLL_LOCK : in std_logic; |
---|
127 | radio2_TX_DAC_RESET : out std_logic; |
---|
128 | radio2_SHDN_external : in std_logic; |
---|
129 | radio2_TxEn_external : in std_logic; |
---|
130 | radio2_RxEn_external : in std_logic; |
---|
131 | radio2_RxHP_external : in std_logic; |
---|
132 | radio2_TxGain : out std_logic_vector(0 to 5); |
---|
133 | radio2_TxStart : out std_logic; |
---|
134 | radio3_SHDN : out std_logic; |
---|
135 | radio3_TxEn : out std_logic; |
---|
136 | radio3_RxEn : out std_logic; |
---|
137 | radio3_RxHP : out std_logic; |
---|
138 | radio3_LD : in std_logic; |
---|
139 | radio3_24PA : out std_logic; |
---|
140 | radio3_5PA : out std_logic; |
---|
141 | radio3_ANTSW : out std_logic_vector(0 to 1); |
---|
142 | radio3_LED : out std_logic_vector(0 to 2); |
---|
143 | radio3_ADC_RX_DCS : out std_logic; |
---|
144 | radio3_ADC_RX_DFS : out std_logic; |
---|
145 | radio3_ADC_RX_OTRA : in std_logic; |
---|
146 | radio3_ADC_RX_OTRB : in std_logic; |
---|
147 | radio3_ADC_RX_PWDNA : out std_logic; |
---|
148 | radio3_ADC_RX_PWDNB : out std_logic; |
---|
149 | radio3_DIPSW : in std_logic_vector(0 to 3); |
---|
150 | radio3_RSSI_ADC_CLAMP : out std_logic; |
---|
151 | radio3_RSSI_ADC_HIZ : out std_logic; |
---|
152 | radio3_RSSI_ADC_OTR : in std_logic; |
---|
153 | radio3_RSSI_ADC_SLEEP : out std_logic; |
---|
154 | radio3_RSSI_ADC_D : in std_logic_vector(0 to 9); |
---|
155 | radio3_TX_DAC_PLL_LOCK : in std_logic; |
---|
156 | radio3_TX_DAC_RESET : out std_logic; |
---|
157 | radio3_SHDN_external : in std_logic; |
---|
158 | radio3_TxEn_external : in std_logic; |
---|
159 | radio3_RxEn_external : in std_logic; |
---|
160 | radio3_RxHP_external : in std_logic; |
---|
161 | radio3_TxGain : out std_logic_vector(0 to 5); |
---|
162 | radio3_TxStart : out std_logic; |
---|
163 | radio4_SHDN : out std_logic; |
---|
164 | radio4_TxEn : out std_logic; |
---|
165 | radio4_RxEn : out std_logic; |
---|
166 | radio4_RxHP : out std_logic; |
---|
167 | radio4_LD : in std_logic; |
---|
168 | radio4_24PA : out std_logic; |
---|
169 | radio4_5PA : out std_logic; |
---|
170 | radio4_ANTSW : out std_logic_vector(0 to 1); |
---|
171 | radio4_LED : out std_logic_vector(0 to 2); |
---|
172 | radio4_ADC_RX_DCS : out std_logic; |
---|
173 | radio4_ADC_RX_DFS : out std_logic; |
---|
174 | radio4_ADC_RX_OTRA : in std_logic; |
---|
175 | radio4_ADC_RX_OTRB : in std_logic; |
---|
176 | radio4_ADC_RX_PWDNA : out std_logic; |
---|
177 | radio4_ADC_RX_PWDNB : out std_logic; |
---|
178 | radio4_DIPSW : in std_logic_vector(0 to 3); |
---|
179 | radio4_RSSI_ADC_CLAMP : out std_logic; |
---|
180 | radio4_RSSI_ADC_HIZ : out std_logic; |
---|
181 | radio4_RSSI_ADC_OTR : in std_logic; |
---|
182 | radio4_RSSI_ADC_SLEEP : out std_logic; |
---|
183 | radio4_RSSI_ADC_D : in std_logic_vector(0 to 9); |
---|
184 | radio4_TX_DAC_PLL_LOCK : in std_logic; |
---|
185 | radio4_TX_DAC_RESET : out std_logic; |
---|
186 | radio4_SHDN_external : in std_logic; |
---|
187 | radio4_TxEn_external : in std_logic; |
---|
188 | radio4_RxEn_external : in std_logic; |
---|
189 | radio4_RxHP_external : in std_logic; |
---|
190 | radio4_TxGain : out std_logic_vector(0 to 5); |
---|
191 | radio4_TxStart : out std_logic; |
---|
192 | |
---|
193 | -- ADD USER PORTS ABOVE THIS LINE ------------------ |
---|
194 | |
---|
195 | -- DO NOT EDIT BELOW THIS LINE --------------------- |
---|
196 | -- Bus protocol ports, do not add to or delete |
---|
197 | OPB_Clk : in std_logic; |
---|
198 | OPB_Rst : in std_logic; |
---|
199 | Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); |
---|
200 | Sl_errAck : out std_logic; |
---|
201 | Sl_retry : out std_logic; |
---|
202 | Sl_toutSup : out std_logic; |
---|
203 | Sl_xferAck : out std_logic; |
---|
204 | OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1); |
---|
205 | OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1); |
---|
206 | OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); |
---|
207 | OPB_RNW : in std_logic; |
---|
208 | OPB_select : in std_logic; |
---|
209 | OPB_seqAddr : in std_logic |
---|
210 | -- DO NOT EDIT ABOVE THIS LINE --------------------- |
---|
211 | ); |
---|
212 | |
---|
213 | attribute SIGIS : string; |
---|
214 | attribute SIGIS of OPB_Clk : signal is "Clk"; |
---|
215 | attribute SIGIS of OPB_Rst : signal is "Rst"; |
---|
216 | |
---|
217 | end entity radio_controller; |
---|
218 | |
---|
219 | ------------------------------------------------------------------------------ |
---|
220 | -- Architecture section |
---|
221 | ------------------------------------------------------------------------------ |
---|
222 | |
---|
223 | architecture IMP of radio_controller is |
---|
224 | |
---|
225 | ------------------------------------------ |
---|
226 | -- Constant: array of address range identifiers |
---|
227 | ------------------------------------------ |
---|
228 | constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE := |
---|
229 | ( |
---|
230 | 0 => USER_00 -- user logic S/W register address space |
---|
231 | ); |
---|
232 | |
---|
233 | ------------------------------------------ |
---|
234 | -- Constant: array of address pairs for each address range |
---|
235 | ------------------------------------------ |
---|
236 | constant ZERO_ADDR_PAD : std_logic_vector(0 to 64-C_OPB_AWIDTH-1) := (others => '0'); |
---|
237 | |
---|
238 | constant USER_BASEADDR : std_logic_vector := C_BASEADDR; |
---|
239 | constant USER_HIGHADDR : std_logic_vector := C_HIGHADDR; |
---|
240 | |
---|
241 | constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := |
---|
242 | ( |
---|
243 | ZERO_ADDR_PAD & USER_BASEADDR, -- user logic base address |
---|
244 | ZERO_ADDR_PAD & USER_HIGHADDR -- user logic high address |
---|
245 | ); |
---|
246 | |
---|
247 | ------------------------------------------ |
---|
248 | -- Constant: array of data widths for each target address range |
---|
249 | ------------------------------------------ |
---|
250 | constant USER_DWIDTH : integer := 32; |
---|
251 | |
---|
252 | constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE := |
---|
253 | ( |
---|
254 | 0 => USER_DWIDTH -- user logic data width |
---|
255 | ); |
---|
256 | |
---|
257 | ------------------------------------------ |
---|
258 | -- Constant: array of desired number of chip enables for each address range |
---|
259 | ------------------------------------------ |
---|
260 | constant USER_NUM_CE : integer := 17; |
---|
261 | |
---|
262 | constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := |
---|
263 | ( |
---|
264 | 0 => pad_power2(USER_NUM_CE) -- user logic number of CEs |
---|
265 | ); |
---|
266 | |
---|
267 | ------------------------------------------ |
---|
268 | -- Constant: array of unique properties for each address range |
---|
269 | ------------------------------------------ |
---|
270 | constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE := |
---|
271 | ( |
---|
272 | 0 => (others => 0) -- user logic slave space dependent properties (none defined) |
---|
273 | ); |
---|
274 | |
---|
275 | ------------------------------------------ |
---|
276 | -- Constant: pipeline mode |
---|
277 | -- 1 = include OPB-In pipeline registers |
---|
278 | -- 2 = include IP pipeline registers |
---|
279 | -- 3 = include OPB-In and IP pipeline registers |
---|
280 | -- 4 = include OPB-Out pipeline registers |
---|
281 | -- 5 = include OPB-In and OPB-Out pipeline registers |
---|
282 | -- 6 = include IP and OPB-Out pipeline registers |
---|
283 | -- 7 = include OPB-In, IP, and OPB-Out pipeline registers |
---|
284 | -- Note: |
---|
285 | -- only mode 4, 5, 7 are supported for this release |
---|
286 | ------------------------------------------ |
---|
287 | constant PIPELINE_MODEL : integer := 5; |
---|
288 | |
---|
289 | ------------------------------------------ |
---|
290 | -- Constant: user core ID code |
---|
291 | ------------------------------------------ |
---|
292 | constant DEV_BLK_ID : integer := 0; |
---|
293 | |
---|
294 | ------------------------------------------ |
---|
295 | -- Constant: enable MIR/Reset register |
---|
296 | ------------------------------------------ |
---|
297 | constant DEV_MIR_ENABLE : integer := 0; |
---|
298 | |
---|
299 | ------------------------------------------ |
---|
300 | -- Constant: array of IP interrupt mode |
---|
301 | -- 1 = Active-high interrupt condition |
---|
302 | -- 2 = Active-low interrupt condition |
---|
303 | -- 3 = Active-high pulse interrupt event |
---|
304 | -- 4 = Active-low pulse interrupt event |
---|
305 | -- 5 = Positive-edge interrupt event |
---|
306 | -- 6 = Negative-edge interrupt event |
---|
307 | ------------------------------------------ |
---|
308 | constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE := |
---|
309 | ( |
---|
310 | 0 => 0 -- not used |
---|
311 | ); |
---|
312 | |
---|
313 | ------------------------------------------ |
---|
314 | -- Constant: enable device burst |
---|
315 | ------------------------------------------ |
---|
316 | constant DEV_BURST_ENABLE : integer := 0; |
---|
317 | |
---|
318 | ------------------------------------------ |
---|
319 | -- Constant: include address counter for burst transfers |
---|
320 | ------------------------------------------ |
---|
321 | constant INCLUDE_ADDR_CNTR : integer := 0; |
---|
322 | |
---|
323 | ------------------------------------------ |
---|
324 | -- Constant: include write buffer that decouples OPB and IPIC write transactions |
---|
325 | ------------------------------------------ |
---|
326 | constant INCLUDE_WR_BUF : integer := 0; |
---|
327 | |
---|
328 | ------------------------------------------ |
---|
329 | -- Constant: index for CS/CE |
---|
330 | ------------------------------------------ |
---|
331 | constant USER00_CS_INDEX : integer := get_id_index(ARD_ID_ARRAY, USER_00); |
---|
332 | |
---|
333 | constant USER00_CE_INDEX : integer := calc_start_ce_index(ARD_NUM_CE_ARRAY, USER00_CS_INDEX); |
---|
334 | |
---|
335 | ------------------------------------------ |
---|
336 | -- IP Interconnect (IPIC) signal declarations -- do not delete |
---|
337 | -- prefix 'i' stands for IPIF while prefix 'u' stands for user logic |
---|
338 | -- typically user logic will be hooked up to IPIF directly via i<sig> |
---|
339 | -- unless signal slicing and muxing are needed via u<sig> |
---|
340 | ------------------------------------------ |
---|
341 | signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1); |
---|
342 | signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1); |
---|
343 | signal iBus2IP_Data : std_logic_vector(0 to C_OPB_DWIDTH-1); |
---|
344 | signal iBus2IP_BE : std_logic_vector(0 to C_OPB_DWIDTH/8-1); |
---|
345 | signal iIP2Bus_Data : std_logic_vector(0 to C_OPB_DWIDTH-1) := (others => '0'); |
---|
346 | signal iIP2Bus_Ack : std_logic := '0'; |
---|
347 | signal iIP2Bus_Error : std_logic := '0'; |
---|
348 | signal iIP2Bus_Retry : std_logic := '0'; |
---|
349 | signal iIP2Bus_ToutSup : std_logic := '0'; |
---|
350 | signal ENABLE_POSTED_WRITE : std_logic_vector(0 to ARD_ID_ARRAY'length-1) := (others => '0'); -- enable posted write behavior |
---|
351 | signal ZERO_IP2RFIFO_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_RDFIFO_DATA))-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping |
---|
352 | signal ZERO_WFIFO2IP_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_WRFIFO_DATA))-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping |
---|
353 | signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping |
---|
354 | signal iBus2IP_Clk : std_logic; |
---|
355 | signal iBus2IP_Reset : std_logic; |
---|
356 | signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1); |
---|
357 | signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1); |
---|
358 | signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1); |
---|
359 | signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1); |
---|
360 | signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1); |
---|
361 | |
---|
362 | ------------------------------------------ |
---|
363 | -- Component declaration for verilog user logic |
---|
364 | ------------------------------------------ |
---|
365 | component user_logic is |
---|
366 | generic |
---|
367 | ( |
---|
368 | -- DO NOT EDIT BELOW THIS LINE --------------------- |
---|
369 | -- Bus protocol parameters, do not add to or delete |
---|
370 | C_DWIDTH : integer := 32; |
---|
371 | C_NUM_CE : integer := 17 |
---|
372 | -- DO NOT EDIT ABOVE THIS LINE --------------------- |
---|
373 | ); |
---|
374 | port |
---|
375 | ( |
---|
376 | -- ADD USER PORTS BELOW THIS LINE ------------------ |
---|
377 | |
---|
378 | spi_clk : out std_logic; |
---|
379 | data_out : out std_logic; |
---|
380 | Radio1_cs : out std_logic; |
---|
381 | Radio2_cs : out std_logic; |
---|
382 | Radio3_cs : out std_logic; |
---|
383 | Radio4_cs : out std_logic; |
---|
384 | Dac1_cs : out std_logic; |
---|
385 | Dac2_cs : out std_logic; |
---|
386 | Dac3_cs : out std_logic; |
---|
387 | Dac4_cs : out std_logic; |
---|
388 | Radio1_SHDN : out std_logic; |
---|
389 | Radio1_TxEn : out std_logic; |
---|
390 | Radio1_RxEn : out std_logic; |
---|
391 | Radio1_RxHP : out std_logic; |
---|
392 | Radio1_LD : in std_logic; |
---|
393 | Radio1_24PA : out std_logic; |
---|
394 | Radio1_5PA : out std_logic; |
---|
395 | Radio1_ANTSW : out std_logic_vector(0 to 1); |
---|
396 | Radio1_LED : out std_logic_vector(0 to 2); |
---|
397 | Radio1_ADC_RX_DCS : out std_logic; |
---|
398 | Radio1_ADC_RX_DFS : out std_logic; |
---|
399 | Radio1_ADC_RX_OTRA : in std_logic; |
---|
400 | Radio1_ADC_RX_OTRB : in std_logic; |
---|
401 | Radio1_ADC_RX_PWDNA : out std_logic; |
---|
402 | Radio1_ADC_RX_PWDNB : out std_logic; |
---|
403 | Radio1_DIPSW : in std_logic_vector(0 to 3); |
---|
404 | Radio1_RSSI_ADC_CLAMP : out std_logic; |
---|
405 | Radio1_RSSI_ADC_HIZ : out std_logic; |
---|
406 | Radio1_RSSI_ADC_OTR : in std_logic; |
---|
407 | Radio1_RSSI_ADC_SLEEP : out std_logic; |
---|
408 | Radio1_RSSI_ADC_D : in std_logic_vector(0 to 9); |
---|
409 | Radio1_TX_DAC_PLL_LOCK : in std_logic; |
---|
410 | Radio1_TX_DAC_RESET : out std_logic; |
---|
411 | Radio1_SHDN_external : in std_logic; |
---|
412 | Radio1_TxEn_external : in std_logic; |
---|
413 | Radio1_RxEn_external : in std_logic; |
---|
414 | Radio1_RxHP_external : in std_logic; |
---|
415 | Radio1_TxGain : out std_logic_vector(0 to 5); |
---|
416 | Radio1_TxStart : out std_logic; |
---|
417 | Radio2_SHDN : out std_logic; |
---|
418 | Radio2_TxEn : out std_logic; |
---|
419 | Radio2_RxEn : out std_logic; |
---|
420 | Radio2_RxHP : out std_logic; |
---|
421 | Radio2_LD : in std_logic; |
---|
422 | Radio2_24PA : out std_logic; |
---|
423 | Radio2_5PA : out std_logic; |
---|
424 | Radio2_ANTSW : out std_logic_vector(0 to 1); |
---|
425 | Radio2_LED : out std_logic_vector(0 to 2); |
---|
426 | Radio2_ADC_RX_DCS : out std_logic; |
---|
427 | Radio2_ADC_RX_DFS : out std_logic; |
---|
428 | Radio2_ADC_RX_OTRA : in std_logic; |
---|
429 | Radio2_ADC_RX_OTRB : in std_logic; |
---|
430 | Radio2_ADC_RX_PWDNA : out std_logic; |
---|
431 | Radio2_ADC_RX_PWDNB : out std_logic; |
---|
432 | Radio2_DIPSW : in std_logic_vector(0 to 3); |
---|
433 | Radio2_RSSI_ADC_CLAMP : out std_logic; |
---|
434 | Radio2_RSSI_ADC_HIZ : out std_logic; |
---|
435 | Radio2_RSSI_ADC_OTR : in std_logic; |
---|
436 | Radio2_RSSI_ADC_SLEEP : out std_logic; |
---|
437 | Radio2_RSSI_ADC_D : in std_logic_vector(0 to 9); |
---|
438 | Radio2_TX_DAC_PLL_LOCK : in std_logic; |
---|
439 | Radio2_TX_DAC_RESET : out std_logic; |
---|
440 | Radio2_SHDN_external : in std_logic; |
---|
441 | Radio2_TxEn_external : in std_logic; |
---|
442 | Radio2_RxEn_external : in std_logic; |
---|
443 | Radio2_RxHP_external : in std_logic; |
---|
444 | Radio2_TxGain : out std_logic_vector(0 to 5); |
---|
445 | Radio2_TxStart : out std_logic; |
---|
446 | Radio3_SHDN : out std_logic; |
---|
447 | Radio3_TxEn : out std_logic; |
---|
448 | Radio3_RxEn : out std_logic; |
---|
449 | Radio3_RxHP : out std_logic; |
---|
450 | Radio3_LD : in std_logic; |
---|
451 | Radio3_24PA : out std_logic; |
---|
452 | Radio3_5PA : out std_logic; |
---|
453 | Radio3_ANTSW : out std_logic_vector(0 to 1); |
---|
454 | Radio3_LED : out std_logic_vector(0 to 2); |
---|
455 | Radio3_ADC_RX_DCS : out std_logic; |
---|
456 | Radio3_ADC_RX_DFS : out std_logic; |
---|
457 | Radio3_ADC_RX_OTRA : in std_logic; |
---|
458 | Radio3_ADC_RX_OTRB : in std_logic; |
---|
459 | Radio3_ADC_RX_PWDNA : out std_logic; |
---|
460 | Radio3_ADC_RX_PWDNB : out std_logic; |
---|
461 | Radio3_DIPSW : in std_logic_vector(0 to 3); |
---|
462 | Radio3_RSSI_ADC_CLAMP : out std_logic; |
---|
463 | Radio3_RSSI_ADC_HIZ : out std_logic; |
---|
464 | Radio3_RSSI_ADC_OTR : in std_logic; |
---|
465 | Radio3_RSSI_ADC_SLEEP : out std_logic; |
---|
466 | Radio3_RSSI_ADC_D : in std_logic_vector(0 to 9); |
---|
467 | Radio3_TX_DAC_PLL_LOCK : in std_logic; |
---|
468 | Radio3_TX_DAC_RESET : out std_logic; |
---|
469 | Radio3_SHDN_external : in std_logic; |
---|
470 | Radio3_TxEn_external : in std_logic; |
---|
471 | Radio3_RxEn_external : in std_logic; |
---|
472 | Radio3_RxHP_external : in std_logic; |
---|
473 | Radio3_TxGain : out std_logic_vector(0 to 5); |
---|
474 | Radio3_TxStart : out std_logic; |
---|
475 | Radio4_SHDN : out std_logic; |
---|
476 | Radio4_TxEn : out std_logic; |
---|
477 | Radio4_RxEn : out std_logic; |
---|
478 | Radio4_RxHP : out std_logic; |
---|
479 | Radio4_LD : in std_logic; |
---|
480 | Radio4_24PA : out std_logic; |
---|
481 | Radio4_5PA : out std_logic; |
---|
482 | Radio4_ANTSW : out std_logic_vector(0 to 1); |
---|
483 | Radio4_LED : out std_logic_vector(0 to 2); |
---|
484 | Radio4_ADC_RX_DCS : out std_logic; |
---|
485 | Radio4_ADC_RX_DFS : out std_logic; |
---|
486 | Radio4_ADC_RX_OTRA : in std_logic; |
---|
487 | Radio4_ADC_RX_OTRB : in std_logic; |
---|
488 | Radio4_ADC_RX_PWDNA : out std_logic; |
---|
489 | Radio4_ADC_RX_PWDNB : out std_logic; |
---|
490 | Radio4_DIPSW : in std_logic_vector(0 to 3); |
---|
491 | Radio4_RSSI_ADC_CLAMP : out std_logic; |
---|
492 | Radio4_RSSI_ADC_HIZ : out std_logic; |
---|
493 | Radio4_RSSI_ADC_OTR : in std_logic; |
---|
494 | Radio4_RSSI_ADC_SLEEP : out std_logic; |
---|
495 | Radio4_RSSI_ADC_D : in std_logic_vector(0 to 9); |
---|
496 | Radio4_TX_DAC_PLL_LOCK : in std_logic; |
---|
497 | Radio4_TX_DAC_RESET : out std_logic; |
---|
498 | Radio4_SHDN_external : in std_logic; |
---|
499 | Radio4_TxEn_external : in std_logic; |
---|
500 | Radio4_RxEn_external : in std_logic; |
---|
501 | Radio4_RxHP_external : in std_logic; |
---|
502 | Radio4_TxGain : out std_logic_vector(0 to 5); |
---|
503 | Radio4_TxStart : out std_logic; |
---|
504 | -- ADD USER PORTS ABOVE THIS LINE ------------------ |
---|
505 | |
---|
506 | -- DO NOT EDIT BELOW THIS LINE --------------------- |
---|
507 | -- Bus protocol ports, do not add to or delete |
---|
508 | Bus2IP_Clk : in std_logic; |
---|
509 | Bus2IP_Reset : in std_logic; |
---|
510 | Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1); |
---|
511 | Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1); |
---|
512 | Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1); |
---|
513 | Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1); |
---|
514 | IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1); |
---|
515 | IP2Bus_Ack : out std_logic; |
---|
516 | IP2Bus_Retry : out std_logic; |
---|
517 | IP2Bus_Error : out std_logic; |
---|
518 | IP2Bus_ToutSup : out std_logic |
---|
519 | -- DO NOT EDIT ABOVE THIS LINE --------------------- |
---|
520 | ); |
---|
521 | end component user_logic; |
---|
522 | |
---|
523 | begin |
---|
524 | |
---|
525 | ------------------------------------------ |
---|
526 | -- instantiate the OPB IPIF |
---|
527 | ------------------------------------------ |
---|
528 | OPB_IPIF_I : entity opb_ipif_v3_01_c.opb_ipif |
---|
529 | generic map |
---|
530 | ( |
---|
531 | C_ARD_ID_ARRAY => ARD_ID_ARRAY, |
---|
532 | C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY, |
---|
533 | C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY, |
---|
534 | C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY, |
---|
535 | C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY, |
---|
536 | C_PIPELINE_MODEL => PIPELINE_MODEL, |
---|
537 | C_DEV_BLK_ID => DEV_BLK_ID, |
---|
538 | C_DEV_MIR_ENABLE => DEV_MIR_ENABLE, |
---|
539 | C_OPB_AWIDTH => C_OPB_AWIDTH, |
---|
540 | C_OPB_DWIDTH => C_OPB_DWIDTH, |
---|
541 | C_FAMILY => C_FAMILY, |
---|
542 | C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY, |
---|
543 | C_DEV_BURST_ENABLE => DEV_BURST_ENABLE, |
---|
544 | C_INCLUDE_ADDR_CNTR => INCLUDE_ADDR_CNTR, |
---|
545 | C_INCLUDE_WR_BUF => INCLUDE_WR_BUF |
---|
546 | ) |
---|
547 | port map |
---|
548 | ( |
---|
549 | OPB_select => OPB_select, |
---|
550 | OPB_DBus => OPB_DBus, |
---|
551 | OPB_ABus => OPB_ABus, |
---|
552 | OPB_BE => OPB_BE, |
---|
553 | OPB_RNW => OPB_RNW, |
---|
554 | OPB_seqAddr => OPB_seqAddr, |
---|
555 | Sln_DBus => Sl_DBus, |
---|
556 | Sln_xferAck => Sl_xferAck, |
---|
557 | Sln_errAck => Sl_errAck, |
---|
558 | Sln_retry => Sl_retry, |
---|
559 | Sln_toutSup => Sl_toutSup, |
---|
560 | Bus2IP_CS => open, |
---|
561 | Bus2IP_CE => open, |
---|
562 | Bus2IP_RdCE => iBus2IP_RdCE, |
---|
563 | Bus2IP_WrCE => iBus2IP_WrCE, |
---|
564 | Bus2IP_Data => iBus2IP_Data, |
---|
565 | Bus2IP_Addr => open, |
---|
566 | Bus2IP_AddrValid => open, |
---|
567 | Bus2IP_BE => iBus2IP_BE, |
---|
568 | Bus2IP_RNW => open, |
---|
569 | Bus2IP_Burst => open, |
---|
570 | IP2Bus_Data => iIP2Bus_Data, |
---|
571 | IP2Bus_Ack => iIP2Bus_Ack, |
---|
572 | IP2Bus_AddrAck => '0', |
---|
573 | IP2Bus_Error => iIP2Bus_Error, |
---|
574 | IP2Bus_Retry => iIP2Bus_Retry, |
---|
575 | IP2Bus_ToutSup => iIP2Bus_ToutSup, |
---|
576 | IP2Bus_PostedWrInh => ENABLE_POSTED_WRITE, |
---|
577 | IP2RFIFO_Data => ZERO_IP2RFIFO_Data, |
---|
578 | IP2RFIFO_WrMark => '0', |
---|
579 | IP2RFIFO_WrRelease => '0', |
---|
580 | IP2RFIFO_WrReq => '0', |
---|
581 | IP2RFIFO_WrRestore => '0', |
---|
582 | RFIFO2IP_AlmostFull => open, |
---|
583 | RFIFO2IP_Full => open, |
---|
584 | RFIFO2IP_Vacancy => open, |
---|
585 | RFIFO2IP_WrAck => open, |
---|
586 | IP2WFIFO_RdMark => '0', |
---|
587 | IP2WFIFO_RdRelease => '0', |
---|
588 | IP2WFIFO_RdReq => '0', |
---|
589 | IP2WFIFO_RdRestore => '0', |
---|
590 | WFIFO2IP_AlmostEmpty => open, |
---|
591 | WFIFO2IP_Data => ZERO_WFIFO2IP_Data, |
---|
592 | WFIFO2IP_Empty => open, |
---|
593 | WFIFO2IP_Occupancy => open, |
---|
594 | WFIFO2IP_RdAck => open, |
---|
595 | IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent, |
---|
596 | IP2INTC_Irpt => open, |
---|
597 | Freeze => '0', |
---|
598 | Bus2IP_Freeze => open, |
---|
599 | OPB_Clk => OPB_Clk, |
---|
600 | Bus2IP_Clk => iBus2IP_Clk, |
---|
601 | IP2Bus_Clk => '0', |
---|
602 | Reset => OPB_Rst, |
---|
603 | Bus2IP_Reset => iBus2IP_Reset |
---|
604 | ); |
---|
605 | |
---|
606 | ------------------------------------------ |
---|
607 | -- instantiate the User Logic |
---|
608 | ------------------------------------------ |
---|
609 | USER_LOGIC_I : component user_logic |
---|
610 | generic map |
---|
611 | ( |
---|
612 | C_DWIDTH => USER_DWIDTH, |
---|
613 | C_NUM_CE => USER_NUM_CE |
---|
614 | ) |
---|
615 | port map |
---|
616 | ( |
---|
617 | -- MAP USER PORTS BELOW THIS LINE ------------------ |
---|
618 | |
---|
619 | spi_clk => spi_clk, |
---|
620 | data_out => data_out, |
---|
621 | Radio1_cs => radio1_cs, |
---|
622 | Radio2_cs => radio2_cs, |
---|
623 | Radio3_cs => radio3_cs, |
---|
624 | Radio4_cs => radio4_cs, |
---|
625 | Dac1_cs => dac1_cs, |
---|
626 | Dac2_cs => dac2_cs, |
---|
627 | Dac3_cs => dac3_cs, |
---|
628 | Dac4_cs => dac4_cs, |
---|
629 | Radio1_SHDN => radio1_SHDN, |
---|
630 | Radio1_TxEn => radio1_TxEn, |
---|
631 | Radio1_RxEn => radio1_RxEn, |
---|
632 | Radio1_RxHP => radio1_RxHP, |
---|
633 | Radio1_LD => radio1_LD, |
---|
634 | Radio1_24PA => radio1_24PA, |
---|
635 | Radio1_5PA => radio1_5PA, |
---|
636 | Radio1_ANTSW => radio1_ANTSW, |
---|
637 | Radio1_LED => radio1_LED, |
---|
638 | Radio1_ADC_RX_DCS => radio1_ADC_RX_DCS, |
---|
639 | Radio1_ADC_RX_DFS => radio1_ADC_RX_DFS, |
---|
640 | Radio1_ADC_RX_OTRA => radio1_ADC_RX_OTRA, |
---|
641 | Radio1_ADC_RX_OTRB => radio1_ADC_RX_OTRB, |
---|
642 | Radio1_ADC_RX_PWDNA => radio1_ADC_RX_PWDNA, |
---|
643 | Radio1_ADC_RX_PWDNB => radio1_ADC_RX_PWDNB, |
---|
644 | Radio1_DIPSW => radio1_DIPSW, |
---|
645 | Radio1_RSSI_ADC_CLAMP => radio1_RSSI_ADC_CLAMP, |
---|
646 | Radio1_RSSI_ADC_HIZ => radio1_RSSI_ADC_HIZ, |
---|
647 | Radio1_RSSI_ADC_OTR => radio1_RSSI_ADC_OTR, |
---|
648 | Radio1_RSSI_ADC_SLEEP => radio1_RSSI_ADC_SLEEP, |
---|
649 | Radio1_RSSI_ADC_D => radio1_RSSI_ADC_D, |
---|
650 | Radio1_TX_DAC_PLL_LOCK => radio1_TX_DAC_PLL_LOCK, |
---|
651 | Radio1_TX_DAC_RESET => radio1_TX_DAC_RESET, |
---|
652 | Radio1_SHDN_external => radio1_SHDN_external, |
---|
653 | Radio1_TxEn_external => radio1_TxEn_external, |
---|
654 | Radio1_RxEn_external => radio1_RxEn_external, |
---|
655 | Radio1_RxHP_external => radio1_RxHP_external, |
---|
656 | Radio1_TxGain => radio1_TxGain, |
---|
657 | Radio1_TxStart => radio1_TxStart, |
---|
658 | Radio2_SHDN => radio2_SHDN, |
---|
659 | Radio2_TxEn => radio2_TxEn, |
---|
660 | Radio2_RxEn => radio2_RxEn, |
---|
661 | Radio2_RxHP => radio2_RxHP, |
---|
662 | Radio2_LD => radio2_LD, |
---|
663 | Radio2_24PA => radio2_24PA, |
---|
664 | Radio2_5PA => radio2_5PA, |
---|
665 | Radio2_ANTSW => radio2_ANTSW, |
---|
666 | Radio2_LED => radio2_LED, |
---|
667 | Radio2_ADC_RX_DCS => radio2_ADC_RX_DCS, |
---|
668 | Radio2_ADC_RX_DFS => radio2_ADC_RX_DFS, |
---|
669 | Radio2_ADC_RX_OTRA => radio2_ADC_RX_OTRA, |
---|
670 | Radio2_ADC_RX_OTRB => radio2_ADC_RX_OTRB, |
---|
671 | Radio2_ADC_RX_PWDNA => radio2_ADC_RX_PWDNA, |
---|
672 | Radio2_ADC_RX_PWDNB => radio2_ADC_RX_PWDNB, |
---|
673 | Radio2_DIPSW => radio2_DIPSW, |
---|
674 | Radio2_RSSI_ADC_CLAMP => radio2_RSSI_ADC_CLAMP, |
---|
675 | Radio2_RSSI_ADC_HIZ => radio2_RSSI_ADC_HIZ, |
---|
676 | Radio2_RSSI_ADC_OTR => radio2_RSSI_ADC_OTR, |
---|
677 | Radio2_RSSI_ADC_SLEEP => radio2_RSSI_ADC_SLEEP, |
---|
678 | Radio2_RSSI_ADC_D => radio2_RSSI_ADC_D, |
---|
679 | Radio2_TX_DAC_PLL_LOCK => radio2_TX_DAC_PLL_LOCK, |
---|
680 | Radio2_TX_DAC_RESET => radio2_TX_DAC_RESET, |
---|
681 | Radio2_SHDN_external => radio2_SHDN_external, |
---|
682 | Radio2_TxEn_external => radio2_TxEn_external, |
---|
683 | Radio2_RxEn_external => radio2_RxEn_external, |
---|
684 | Radio2_RxHP_external => radio2_RxHP_external, |
---|
685 | Radio2_TxGain => radio2_TxGain, |
---|
686 | Radio2_TxStart => radio2_TxStart, |
---|
687 | Radio3_SHDN => radio3_SHDN, |
---|
688 | Radio3_TxEn => radio3_TxEn, |
---|
689 | Radio3_RxEn => radio3_RxEn, |
---|
690 | Radio3_RxHP => radio3_RxHP, |
---|
691 | Radio3_LD => radio3_LD, |
---|
692 | Radio3_24PA => radio3_24PA, |
---|
693 | Radio3_5PA => radio3_5PA, |
---|
694 | Radio3_ANTSW => radio3_ANTSW, |
---|
695 | Radio3_LED => radio3_LED, |
---|
696 | Radio3_ADC_RX_DCS => radio3_ADC_RX_DCS, |
---|
697 | Radio3_ADC_RX_DFS => radio3_ADC_RX_DFS, |
---|
698 | Radio3_ADC_RX_OTRA => radio3_ADC_RX_OTRA, |
---|
699 | Radio3_ADC_RX_OTRB => radio3_ADC_RX_OTRB, |
---|
700 | Radio3_ADC_RX_PWDNA => radio3_ADC_RX_PWDNA, |
---|
701 | Radio3_ADC_RX_PWDNB => radio3_ADC_RX_PWDNB, |
---|
702 | Radio3_DIPSW => radio3_DIPSW, |
---|
703 | Radio3_RSSI_ADC_CLAMP => radio3_RSSI_ADC_CLAMP, |
---|
704 | Radio3_RSSI_ADC_HIZ => radio3_RSSI_ADC_HIZ, |
---|
705 | Radio3_RSSI_ADC_OTR => radio3_RSSI_ADC_OTR, |
---|
706 | Radio3_RSSI_ADC_SLEEP => radio3_RSSI_ADC_SLEEP, |
---|
707 | Radio3_RSSI_ADC_D => radio3_RSSI_ADC_D, |
---|
708 | Radio3_TX_DAC_PLL_LOCK => radio3_TX_DAC_PLL_LOCK, |
---|
709 | Radio3_TX_DAC_RESET => radio3_TX_DAC_RESET, |
---|
710 | Radio3_SHDN_external => radio3_SHDN_external, |
---|
711 | Radio3_TxEn_external => radio3_TxEn_external, |
---|
712 | Radio3_RxEn_external => radio3_RxEn_external, |
---|
713 | Radio3_RxHP_external => radio3_RxHP_external, |
---|
714 | Radio3_TxGain => radio3_TxGain, |
---|
715 | Radio3_TxStart => radio3_TxStart, |
---|
716 | Radio4_SHDN => radio4_SHDN, |
---|
717 | Radio4_TxEn => radio4_TxEn, |
---|
718 | Radio4_RxEn => radio4_RxEn, |
---|
719 | Radio4_RxHP => radio4_RxHP, |
---|
720 | Radio4_LD => radio4_LD, |
---|
721 | Radio4_24PA => radio4_24PA, |
---|
722 | Radio4_5PA => radio4_5PA, |
---|
723 | Radio4_ANTSW => radio4_ANTSW, |
---|
724 | Radio4_LED => radio4_LED, |
---|
725 | Radio4_ADC_RX_DCS => radio4_ADC_RX_DCS, |
---|
726 | Radio4_ADC_RX_DFS => radio4_ADC_RX_DFS, |
---|
727 | Radio4_ADC_RX_OTRA => radio4_ADC_RX_OTRA, |
---|
728 | Radio4_ADC_RX_OTRB => radio4_ADC_RX_OTRB, |
---|
729 | Radio4_ADC_RX_PWDNA => radio4_ADC_RX_PWDNA, |
---|
730 | Radio4_ADC_RX_PWDNB => radio4_ADC_RX_PWDNB, |
---|
731 | Radio4_DIPSW => radio4_DIPSW, |
---|
732 | Radio4_RSSI_ADC_CLAMP => radio4_RSSI_ADC_CLAMP, |
---|
733 | Radio4_RSSI_ADC_HIZ => radio4_RSSI_ADC_HIZ, |
---|
734 | Radio4_RSSI_ADC_OTR => radio4_RSSI_ADC_OTR, |
---|
735 | Radio4_RSSI_ADC_SLEEP => radio4_RSSI_ADC_SLEEP, |
---|
736 | Radio4_RSSI_ADC_D => radio4_RSSI_ADC_D, |
---|
737 | Radio4_TX_DAC_PLL_LOCK => radio4_TX_DAC_PLL_LOCK, |
---|
738 | Radio4_TX_DAC_RESET => radio4_TX_DAC_RESET, |
---|
739 | Radio4_SHDN_external => radio4_SHDN_external, |
---|
740 | Radio4_TxEn_external => radio4_TxEn_external, |
---|
741 | Radio4_RxEn_external => radio4_RxEn_external, |
---|
742 | Radio4_RxHP_external => radio4_RxHP_external, |
---|
743 | Radio4_TxGain => radio4_TxGain, |
---|
744 | Radio4_TxStart => radio4_TxStart, |
---|
745 | |
---|
746 | -- MAP USER PORTS ABOVE THIS LINE ------------------ |
---|
747 | |
---|
748 | Bus2IP_Clk => iBus2IP_Clk, |
---|
749 | Bus2IP_Reset => iBus2IP_Reset, |
---|
750 | Bus2IP_Data => uBus2IP_Data, |
---|
751 | Bus2IP_BE => uBus2IP_BE, |
---|
752 | Bus2IP_RdCE => uBus2IP_RdCE, |
---|
753 | Bus2IP_WrCE => uBus2IP_WrCE, |
---|
754 | IP2Bus_Data => uIP2Bus_Data, |
---|
755 | IP2Bus_Ack => iIP2Bus_Ack, |
---|
756 | IP2Bus_Retry => iIP2Bus_Retry, |
---|
757 | IP2Bus_Error => iIP2Bus_Error, |
---|
758 | IP2Bus_ToutSup => iIP2Bus_ToutSup |
---|
759 | ); |
---|
760 | |
---|
761 | ------------------------------------------ |
---|
762 | -- hooking up signal slicing |
---|
763 | ------------------------------------------ |
---|
764 | uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1); |
---|
765 | uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1); |
---|
766 | uBus2IP_RdCE <= iBus2IP_RdCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1); |
---|
767 | uBus2IP_WrCE <= iBus2IP_WrCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1); |
---|
768 | iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data; |
---|
769 | |
---|
770 | end IMP; |
---|