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radio_controller.vhd

Last change on this file was 1061, checked in by murphpo, 16 years ago
Updated radio controller/bridge v1.21a with support for bypassing interp/dec filters from software; filters can still be excluded from hardware with a parameter
File size: 45.9 KB

Line
1	------------------------------------------------------------------------------
2	-- radio_controller.vhd - entity/architecture pair
3	------------------------------------------------------------------------------
4	-- IMPORTANT:
5	-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
6	--
7	-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
8	--
9	-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
10	-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
11	-- OF THE USER_LOGIC ENTITY.
12	------------------------------------------------------------------------------
13	--
14	-- ***************************************************************************
15	-- Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
16	--
17	-- Xilinx, Inc.
18	-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
19	-- AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
20	-- SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
21	-- OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
22	-- APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
23	-- THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
24	-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
25	-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
26	-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
27	-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
28	-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
29	-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
30	-- FOR A PARTICULAR PURPOSE.
31	--
32	-- ***************************************************************************
33	--
34	------------------------------------------------------------------------------
35	-- Filename: radio_controller.vhd
36	-- Version: 1.20.a
37	-- Description: Top level design, instantiates library components and user logic.
38	-- Date: Wed Feb 06 13:11:09 2008 (by Create and Import Peripheral Wizard)
39	-- VHDL Standard: VHDL'93
40	------------------------------------------------------------------------------
41	-- Naming Conventions:
42	-- active low signals: "*_n"
43	-- clock signals: "clk", "clk_div#", "clk_#x"
44	-- reset signals: "rst", "rst_n"
45	-- generics: "C_*"
46	-- user defined types: "*_TYPE"
47	-- state machine next state: "*_ns"
48	-- state machine current state: "*_cs"
49	-- combinatorial signals: "*_com"
50	-- pipelined or register delay signals: "*_d#"
51	-- counter signals: "cnt"
52	-- clock enable signals: "*_ce"
53	-- internal version of output port: "*_i"
54	-- device pins: "*_pin"
55	-- ports: "- Names begin with Uppercase"
56	-- processes: "*_PROCESS"
57	-- component instantiations: "<ENTITY_>I_<#\|FUNC>"
58	------------------------------------------------------------------------------
59
60	library ieee;
61	use ieee.std_logic_1164.all;
62	use ieee.std_logic_arith.all;
63	use ieee.std_logic_unsigned.all;
64
65	library proc_common_v2_00_a;
66	use proc_common_v2_00_a.proc_common_pkg.all;
67	use proc_common_v2_00_a.ipif_pkg.all;
68
69	library plbv46_slave_single_v1_00_a;
70	use plbv46_slave_single_v1_00_a.plbv46_slave_single;
71
72	------------------------------------------------------------------------------
73	-- Entity section
74	------------------------------------------------------------------------------
75	-- Definition of Generics:
76	-- C_BASEADDR -- PLBv46 slave: base address
77	-- C_HIGHADDR -- PLBv46 slave: high address
78	-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
79	-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
80	-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
81	-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
82	-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
83	-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
84	-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
85	-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
86	-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
87	-- C_FAMILY -- Xilinx FPGA family
88	--
89	-- Definition of Ports:
90	-- SPLB_Clk -- PLB main bus clock
91	-- SPLB_Rst -- PLB main bus reset
92	-- PLB_ABus -- PLB address bus
93	-- PLB_UABus -- PLB upper address bus
94	-- PLB_PAValid -- PLB primary address valid indicator
95	-- PLB_SAValid -- PLB secondary address valid indicator
96	-- PLB_rdPrim -- PLB secondary to primary read request indicator
97	-- PLB_wrPrim -- PLB secondary to primary write request indicator
98	-- PLB_masterID -- PLB current master identifier
99	-- PLB_abort -- PLB abort request indicator
100	-- PLB_busLock -- PLB bus lock
101	-- PLB_RNW -- PLB read/not write
102	-- PLB_BE -- PLB byte enables
103	-- PLB_MSize -- PLB master data bus size
104	-- PLB_size -- PLB transfer size
105	-- PLB_type -- PLB transfer type
106	-- PLB_lockErr -- PLB lock error indicator
107	-- PLB_wrDBus -- PLB write data bus
108	-- PLB_wrBurst -- PLB burst write transfer indicator
109	-- PLB_rdBurst -- PLB burst read transfer indicator
110	-- PLB_wrPendReq -- PLB write pending bus request indicator
111	-- PLB_rdPendReq -- PLB read pending bus request indicator
112	-- PLB_wrPendPri -- PLB write pending request priority
113	-- PLB_rdPendPri -- PLB read pending request priority
114	-- PLB_reqPri -- PLB current request priority
115	-- PLB_TAttribute -- PLB transfer attribute
116	-- Sl_addrAck -- Slave address acknowledge
117	-- Sl_SSize -- Slave data bus size
118	-- Sl_wait -- Slave wait indicator
119	-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
120	-- Sl_wrDAck -- Slave write data acknowledge
121	-- Sl_wrComp -- Slave write transfer complete indicator
122	-- Sl_wrBTerm -- Slave terminate write burst transfer
123	-- Sl_rdDBus -- Slave read data bus
124	-- Sl_rdWdAddr -- Slave read word address
125	-- Sl_rdDAck -- Slave read data acknowledge
126	-- Sl_rdComp -- Slave read transfer complete indicator
127	-- Sl_rdBTerm -- Slave terminate read burst transfer
128	-- Sl_MBusy -- Slave busy indicator
129	-- Sl_MWrErr -- Slave write error indicator
130	-- Sl_MRdErr -- Slave read error indicator
131	-- Sl_MIRQ -- Slave interrupt indicator
132	------------------------------------------------------------------------------
133
134	entity radio_controller is
135	generic
136	(
137	-- ADD USER GENERICS BELOW THIS LINE ---------------
138	--USER generics added here
139	-- ADD USER GENERICS ABOVE THIS LINE ---------------
140
141	-- DO NOT EDIT BELOW THIS LINE ---------------------
142	-- Bus protocol parameters, do not add to or delete
143	C_BASEADDR : std_logic_vector := X"FFFFFFFF";
144	C_HIGHADDR : std_logic_vector := X"00000000";
145	C_SPLB_AWIDTH : integer := 32;
146	C_SPLB_DWIDTH : integer := 128;
147	C_SPLB_NUM_MASTERS : integer := 8;
148	C_SPLB_MID_WIDTH : integer := 3;
149	C_SPLB_NATIVE_DWIDTH : integer := 32;
150	C_SPLB_P2P : integer := 0;
151	C_SPLB_SUPPORT_BURSTS : integer := 0;
152	C_SPLB_SMALLEST_MASTER : integer := 32;
153	C_SPLB_CLK_PERIOD_PS : integer := 10000;
154	C_FAMILY : string := "virtex5"
155	-- DO NOT EDIT ABOVE THIS LINE ---------------------
156	);
157	port
158	(
159	-- ADD USER PORTS BELOW THIS LINE ------------------
160
161
162	controller_logic_clk : out std_logic;
163	spi_clk : out std_logic;
164	data_out : out std_logic;
165	radio1_cs : out std_logic;
166	radio2_cs : out std_logic;
167	radio3_cs : out std_logic;
168	radio4_cs : out std_logic;
169	dac1_cs : out std_logic;
170	dac2_cs : out std_logic;
171	dac3_cs : out std_logic;
172	dac4_cs : out std_logic;
173	radio1_interpfiltbypass : out std_logic;
174	radio1_decfiltbypass : out std_logic;
175	radio1_SHDN : out std_logic;
176	radio1_TxEn : out std_logic;
177	radio1_RxEn : out std_logic;
178	radio1_RxHP : out std_logic;
179	radio1_LD : in std_logic;
180	radio1_24PA : out std_logic;
181	radio1_5PA : out std_logic;
182	radio1_ANTSW : out std_logic_vector(0 to 1);
183	radio1_LED : out std_logic_vector(0 to 2);
184	radio1_ADC_RX_DCS : out std_logic;
185	radio1_ADC_RX_DFS : out std_logic;
186	radio1_ADC_RX_OTRA : in std_logic;
187	radio1_ADC_RX_OTRB : in std_logic;
188	radio1_ADC_RX_PWDNA : out std_logic;
189	radio1_ADC_RX_PWDNB : out std_logic;
190	radio1_DIPSW : in std_logic_vector(0 to 3);
191	radio1_RSSI_ADC_CLAMP : out std_logic;
192	radio1_RSSI_ADC_HIZ : out std_logic;
193	radio1_RSSI_ADC_OTR : in std_logic;
194	radio1_RSSI_ADC_SLEEP : out std_logic;
195	radio1_RSSI_ADC_D : in std_logic_vector(0 to 9);
196	radio1_TX_DAC_PLL_LOCK : in std_logic;
197	radio1_TX_DAC_RESET : out std_logic;
198	radio1_SHDN_external : in std_logic;
199	radio1_TxEn_external : in std_logic;
200	radio1_RxEn_external : in std_logic;
201	radio1_RxHP_external : in std_logic;
202	radio1_TxGain : out std_logic_vector(0 to 5);
203	radio1_TxStart : out std_logic;
204	radio2_interpfiltbypass : out std_logic;
205	radio2_decfiltbypass : out std_logic;
206	radio2_SHDN : out std_logic;
207	radio2_TxEn : out std_logic;
208	radio2_RxEn : out std_logic;
209	radio2_RxHP : out std_logic;
210	radio2_LD : in std_logic;
211	radio2_24PA : out std_logic;
212	radio2_5PA : out std_logic;
213	radio2_ANTSW : out std_logic_vector(0 to 1);
214	radio2_LED : out std_logic_vector(0 to 2);
215	radio2_ADC_RX_DCS : out std_logic;
216	radio2_ADC_RX_DFS : out std_logic;
217	radio2_ADC_RX_OTRA : in std_logic;
218	radio2_ADC_RX_OTRB : in std_logic;
219	radio2_ADC_RX_PWDNA : out std_logic;
220	radio2_ADC_RX_PWDNB : out std_logic;
221	radio2_DIPSW : in std_logic_vector(0 to 3);
222	radio2_RSSI_ADC_CLAMP : out std_logic;
223	radio2_RSSI_ADC_HIZ : out std_logic;
224	radio2_RSSI_ADC_OTR : in std_logic;
225	radio2_RSSI_ADC_SLEEP : out std_logic;
226	radio2_RSSI_ADC_D : in std_logic_vector(0 to 9);
227	radio2_TX_DAC_PLL_LOCK : in std_logic;
228	radio2_TX_DAC_RESET : out std_logic;
229	radio2_SHDN_external : in std_logic;
230	radio2_TxEn_external : in std_logic;
231	radio2_RxEn_external : in std_logic;
232	radio2_RxHP_external : in std_logic;
233	radio2_TxGain : out std_logic_vector(0 to 5);
234	radio2_TxStart : out std_logic;
235	radio3_interpfiltbypass : out std_logic;
236	radio3_decfiltbypass : out std_logic;
237	radio3_SHDN : out std_logic;
238	radio3_TxEn : out std_logic;
239	radio3_RxEn : out std_logic;
240	radio3_RxHP : out std_logic;
241	radio3_LD : in std_logic;
242	radio3_24PA : out std_logic;
243	radio3_5PA : out std_logic;
244	radio3_ANTSW : out std_logic_vector(0 to 1);
245	radio3_LED : out std_logic_vector(0 to 2);
246	radio3_ADC_RX_DCS : out std_logic;
247	radio3_ADC_RX_DFS : out std_logic;
248	radio3_ADC_RX_OTRA : in std_logic;
249	radio3_ADC_RX_OTRB : in std_logic;
250	radio3_ADC_RX_PWDNA : out std_logic;
251	radio3_ADC_RX_PWDNB : out std_logic;
252	radio3_DIPSW : in std_logic_vector(0 to 3);
253	radio3_RSSI_ADC_CLAMP : out std_logic;
254	radio3_RSSI_ADC_HIZ : out std_logic;
255	radio3_RSSI_ADC_OTR : in std_logic;
256	radio3_RSSI_ADC_SLEEP : out std_logic;
257	radio3_RSSI_ADC_D : in std_logic_vector(0 to 9);
258	radio3_TX_DAC_PLL_LOCK : in std_logic;
259	radio3_TX_DAC_RESET : out std_logic;
260	radio3_SHDN_external : in std_logic;
261	radio3_TxEn_external : in std_logic;
262	radio3_RxEn_external : in std_logic;
263	radio3_RxHP_external : in std_logic;
264	radio3_TxGain : out std_logic_vector(0 to 5);
265	radio3_TxStart : out std_logic;
266	radio4_interpfiltbypass : out std_logic;
267	radio4_decfiltbypass : out std_logic;
268	radio4_SHDN : out std_logic;
269	radio4_TxEn : out std_logic;
270	radio4_RxEn : out std_logic;
271	radio4_RxHP : out std_logic;
272	radio4_LD : in std_logic;
273	radio4_24PA : out std_logic;
274	radio4_5PA : out std_logic;
275	radio4_ANTSW : out std_logic_vector(0 to 1);
276	radio4_LED : out std_logic_vector(0 to 2);
277	radio4_ADC_RX_DCS : out std_logic;
278	radio4_ADC_RX_DFS : out std_logic;
279	radio4_ADC_RX_OTRA : in std_logic;
280	radio4_ADC_RX_OTRB : in std_logic;
281	radio4_ADC_RX_PWDNA : out std_logic;
282	radio4_ADC_RX_PWDNB : out std_logic;
283	radio4_DIPSW : in std_logic_vector(0 to 3);
284	radio4_RSSI_ADC_CLAMP : out std_logic;
285	radio4_RSSI_ADC_HIZ : out std_logic;
286	radio4_RSSI_ADC_OTR : in std_logic;
287	radio4_RSSI_ADC_SLEEP : out std_logic;
288	radio4_RSSI_ADC_D : in std_logic_vector(0 to 9);
289	radio4_TX_DAC_PLL_LOCK : in std_logic;
290	radio4_TX_DAC_RESET : out std_logic;
291	radio4_SHDN_external : in std_logic;
292	radio4_TxEn_external : in std_logic;
293	radio4_RxEn_external : in std_logic;
294	radio4_RxHP_external : in std_logic;
295	radio4_TxGain : out std_logic_vector(0 to 5);
296	radio4_TxStart : out std_logic;
297	-- ADD USER PORTS ABOVE THIS LINE ------------------
298
299	-- DO NOT EDIT BELOW THIS LINE ---------------------
300	-- Bus protocol ports, do not add to or delete
301	SPLB_Clk : in std_logic;
302	SPLB_Rst : in std_logic;
303	PLB_ABus : in std_logic_vector(0 to 31);
304	PLB_UABus : in std_logic_vector(0 to 31);
305	PLB_PAValid : in std_logic;
306	PLB_SAValid : in std_logic;
307	PLB_rdPrim : in std_logic;
308	PLB_wrPrim : in std_logic;
309	PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
310	PLB_abort : in std_logic;
311	PLB_busLock : in std_logic;
312	PLB_RNW : in std_logic;
313	PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
314	PLB_MSize : in std_logic_vector(0 to 1);
315	PLB_size : in std_logic_vector(0 to 3);
316	PLB_type : in std_logic_vector(0 to 2);
317	PLB_lockErr : in std_logic;
318	PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
319	PLB_wrBurst : in std_logic;
320	PLB_rdBurst : in std_logic;
321	PLB_wrPendReq : in std_logic;
322	PLB_rdPendReq : in std_logic;
323	PLB_wrPendPri : in std_logic_vector(0 to 1);
324	PLB_rdPendPri : in std_logic_vector(0 to 1);
325	PLB_reqPri : in std_logic_vector(0 to 1);
326	PLB_TAttribute : in std_logic_vector(0 to 15);
327	Sl_addrAck : out std_logic;
328	Sl_SSize : out std_logic_vector(0 to 1);
329	Sl_wait : out std_logic;
330	Sl_rearbitrate : out std_logic;
331	Sl_wrDAck : out std_logic;
332	Sl_wrComp : out std_logic;
333	Sl_wrBTerm : out std_logic;
334	Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
335	Sl_rdWdAddr : out std_logic_vector(0 to 3);
336	Sl_rdDAck : out std_logic;
337	Sl_rdComp : out std_logic;
338	Sl_rdBTerm : out std_logic;
339	Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
340	Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
341	Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
342	Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
343	-- DO NOT EDIT ABOVE THIS LINE ---------------------
344	);
345
346	attribute SIGIS : string;
347	attribute SIGIS of SPLB_Clk : signal is "CLK";
348	attribute SIGIS of SPLB_Rst : signal is "RST";
349
350	end entity radio_controller;
351
352	------------------------------------------------------------------------------
353	-- Architecture section
354	------------------------------------------------------------------------------
355
356	architecture IMP of radio_controller is
357
358	------------------------------------------
359	-- Array of base/high address pairs for each address range
360	------------------------------------------
361	constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
362	constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
363	constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
364
365	constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
366	(
367	ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
368	ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
369	);
370
371	------------------------------------------
372	-- Array of desired number of chip enables for each address range
373	------------------------------------------
374	constant USER_SLV_NUM_REG : integer := 17;
375	constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
376
377	constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
378	(
379	0 => pad_power2(USER_SLV_NUM_REG) -- number of ce for user logic slave space
380	);
381
382	------------------------------------------
383	-- Ratio of bus clock to core clock (for use in dual clock systems)
384	-- 1 = ratio is 1:1
385	-- 2 = ratio is 2:1
386	------------------------------------------
387	constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
388
389	------------------------------------------
390	-- Width of the slave data bus (32 only)
391	------------------------------------------
392	constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
393
394	constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
395
396	------------------------------------------
397	-- Index for CS/CE
398	------------------------------------------
399	constant USER_SLV_CS_INDEX : integer := 0;
400	constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
401
402	constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
403
404	------------------------------------------
405	-- IP Interconnect (IPIC) signal declarations
406	------------------------------------------
407	signal ipif_Bus2IP_Clk : std_logic;
408	signal ipif_Bus2IP_Reset : std_logic;
409	signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
410	signal ipif_IP2Bus_WrAck : std_logic;
411	signal ipif_IP2Bus_RdAck : std_logic;
412	signal ipif_IP2Bus_Error : std_logic;
413	signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
414	signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
415	signal ipif_Bus2IP_RNW : std_logic;
416	signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
417	signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
418	signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
419	signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
420	signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
421	signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
422	signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
423	signal user_IP2Bus_RdAck : std_logic;
424	signal user_IP2Bus_WrAck : std_logic;
425	signal user_IP2Bus_Error : std_logic;
426
427	------------------------------------------
428	-- Component declaration for verilog user logic
429	------------------------------------------
430	component user_logic is
431	generic
432	(
433	-- ADD USER GENERICS BELOW THIS LINE ---------------
434	--USER generics added here
435	-- ADD USER GENERICS ABOVE THIS LINE ---------------
436
437	-- DO NOT EDIT BELOW THIS LINE ---------------------
438	-- Bus protocol parameters, do not add to or delete
439	C_SLV_DWIDTH : integer := 32;
440	C_NUM_REG : integer := 17
441	-- DO NOT EDIT ABOVE THIS LINE ---------------------
442	);
443	port
444	(
445	-- ADD USER PORTS BELOW THIS LINE ------------------
446	controller_logic_clk : out std_logic;
447	spi_clk : out std_logic;
448	data_out : out std_logic;
449	Radio1_cs : out std_logic;
450	Radio2_cs : out std_logic;
451	Radio3_cs : out std_logic;
452	Radio4_cs : out std_logic;
453	Dac1_cs : out std_logic;
454	Dac2_cs : out std_logic;
455	Dac3_cs : out std_logic;
456	Dac4_cs : out std_logic;
457	Radio1_interpfiltbypass : out std_logic;
458	Radio1_decfiltbypass : out std_logic;
459	Radio1_SHDN : out std_logic;
460	Radio1_TxEn : out std_logic;
461	Radio1_RxEn : out std_logic;
462	Radio1_RxHP : out std_logic;
463	Radio1_LD : in std_logic;
464	Radio1_24PA : out std_logic;
465	Radio1_5PA : out std_logic;
466	Radio1_ANTSW : out std_logic_vector(0 to 1);
467	Radio1_LED : out std_logic_vector(0 to 2);
468	Radio1_ADC_RX_DCS : out std_logic;
469	Radio1_ADC_RX_DFS : out std_logic;
470	Radio1_ADC_RX_OTRA : in std_logic;
471	Radio1_ADC_RX_OTRB : in std_logic;
472	Radio1_ADC_RX_PWDNA : out std_logic;
473	Radio1_ADC_RX_PWDNB : out std_logic;
474	Radio1_DIPSW : in std_logic_vector(0 to 3);
475	Radio1_RSSI_ADC_CLAMP : out std_logic;
476	Radio1_RSSI_ADC_HIZ : out std_logic;
477	Radio1_RSSI_ADC_OTR : in std_logic;
478	Radio1_RSSI_ADC_SLEEP : out std_logic;
479	Radio1_RSSI_ADC_D : in std_logic_vector(0 to 9);
480	Radio1_TX_DAC_PLL_LOCK : in std_logic;
481	Radio1_TX_DAC_RESET : out std_logic;
482	Radio1_SHDN_external : in std_logic;
483	Radio1_TxEn_external : in std_logic;
484	Radio1_RxEn_external : in std_logic;
485	Radio1_RxHP_external : in std_logic;
486	Radio1_TxGain : out std_logic_vector(0 to 5);
487	Radio1_TxStart : out std_logic;
488	Radio2_interpfiltbypass : out std_logic;
489	Radio2_decfiltbypass : out std_logic;
490	Radio2_SHDN : out std_logic;
491	Radio2_TxEn : out std_logic;
492	Radio2_RxEn : out std_logic;
493	Radio2_RxHP : out std_logic;
494	Radio2_LD : in std_logic;
495	Radio2_24PA : out std_logic;
496	Radio2_5PA : out std_logic;
497	Radio2_ANTSW : out std_logic_vector(0 to 1);
498	Radio2_LED : out std_logic_vector(0 to 2);
499	Radio2_ADC_RX_DCS : out std_logic;
500	Radio2_ADC_RX_DFS : out std_logic;
501	Radio2_ADC_RX_OTRA : in std_logic;
502	Radio2_ADC_RX_OTRB : in std_logic;
503	Radio2_ADC_RX_PWDNA : out std_logic;
504	Radio2_ADC_RX_PWDNB : out std_logic;
505	Radio2_DIPSW : in std_logic_vector(0 to 3);
506	Radio2_RSSI_ADC_CLAMP : out std_logic;
507	Radio2_RSSI_ADC_HIZ : out std_logic;
508	Radio2_RSSI_ADC_OTR : in std_logic;
509	Radio2_RSSI_ADC_SLEEP : out std_logic;
510	Radio2_RSSI_ADC_D : in std_logic_vector(0 to 9);
511	Radio2_TX_DAC_PLL_LOCK : in std_logic;
512	Radio2_TX_DAC_RESET : out std_logic;
513	Radio2_SHDN_external : in std_logic;
514	Radio2_TxEn_external : in std_logic;
515	Radio2_RxEn_external : in std_logic;
516	Radio2_RxHP_external : in std_logic;
517	Radio2_TxGain : out std_logic_vector(0 to 5);
518	Radio2_TxStart : out std_logic;
519	Radio3_interpfiltbypass : out std_logic;
520	Radio3_decfiltbypass : out std_logic;
521	Radio3_SHDN : out std_logic;
522	Radio3_TxEn : out std_logic;
523	Radio3_RxEn : out std_logic;
524	Radio3_RxHP : out std_logic;
525	Radio3_LD : in std_logic;
526	Radio3_24PA : out std_logic;
527	Radio3_5PA : out std_logic;
528	Radio3_ANTSW : out std_logic_vector(0 to 1);
529	Radio3_LED : out std_logic_vector(0 to 2);
530	Radio3_ADC_RX_DCS : out std_logic;
531	Radio3_ADC_RX_DFS : out std_logic;
532	Radio3_ADC_RX_OTRA : in std_logic;
533	Radio3_ADC_RX_OTRB : in std_logic;
534	Radio3_ADC_RX_PWDNA : out std_logic;
535	Radio3_ADC_RX_PWDNB : out std_logic;
536	Radio3_DIPSW : in std_logic_vector(0 to 3);
537	Radio3_RSSI_ADC_CLAMP : out std_logic;
538	Radio3_RSSI_ADC_HIZ : out std_logic;
539	Radio3_RSSI_ADC_OTR : in std_logic;
540	Radio3_RSSI_ADC_SLEEP : out std_logic;
541	Radio3_RSSI_ADC_D : in std_logic_vector(0 to 9);
542	Radio3_TX_DAC_PLL_LOCK : in std_logic;
543	Radio3_TX_DAC_RESET : out std_logic;
544	Radio3_SHDN_external : in std_logic;
545	Radio3_TxEn_external : in std_logic;
546	Radio3_RxEn_external : in std_logic;
547	Radio3_RxHP_external : in std_logic;
548	Radio3_TxGain : out std_logic_vector(0 to 5);
549	Radio3_TxStart : out std_logic;
550	Radio4_interpfiltbypass : out std_logic;
551	Radio4_decfiltbypass : out std_logic;
552	Radio4_SHDN : out std_logic;
553	Radio4_TxEn : out std_logic;
554	Radio4_RxEn : out std_logic;
555	Radio4_RxHP : out std_logic;
556	Radio4_LD : in std_logic;
557	Radio4_24PA : out std_logic;
558	Radio4_5PA : out std_logic;
559	Radio4_ANTSW : out std_logic_vector(0 to 1);
560	Radio4_LED : out std_logic_vector(0 to 2);
561	Radio4_ADC_RX_DCS : out std_logic;
562	Radio4_ADC_RX_DFS : out std_logic;
563	Radio4_ADC_RX_OTRA : in std_logic;
564	Radio4_ADC_RX_OTRB : in std_logic;
565	Radio4_ADC_RX_PWDNA : out std_logic;
566	Radio4_ADC_RX_PWDNB : out std_logic;
567	Radio4_DIPSW : in std_logic_vector(0 to 3);
568	Radio4_RSSI_ADC_CLAMP : out std_logic;
569	Radio4_RSSI_ADC_HIZ : out std_logic;
570	Radio4_RSSI_ADC_OTR : in std_logic;
571	Radio4_RSSI_ADC_SLEEP : out std_logic;
572	Radio4_RSSI_ADC_D : in std_logic_vector(0 to 9);
573	Radio4_TX_DAC_PLL_LOCK : in std_logic;
574	Radio4_TX_DAC_RESET : out std_logic;
575	Radio4_SHDN_external : in std_logic;
576	Radio4_TxEn_external : in std_logic;
577	Radio4_RxEn_external : in std_logic;
578	Radio4_RxHP_external : in std_logic;
579	Radio4_TxGain : out std_logic_vector(0 to 5);
580	Radio4_TxStart : out std_logic;
581	-- ADD USER PORTS ABOVE THIS LINE ------------------
582
583	-- DO NOT EDIT BELOW THIS LINE ---------------------
584	-- Bus protocol ports, do not add to or delete
585	Bus2IP_Clk : in std_logic;
586	Bus2IP_Reset : in std_logic;
587	Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
588	Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
589	Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
590	Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
591	IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
592	IP2Bus_RdAck : out std_logic;
593	IP2Bus_WrAck : out std_logic;
594	IP2Bus_Error : out std_logic
595	-- DO NOT EDIT ABOVE THIS LINE ---------------------
596	);
597	end component user_logic;
598
599	begin
600
601	------------------------------------------
602	-- instantiate plbv46_slave_single
603	------------------------------------------
604	PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_00_a.plbv46_slave_single
605	generic map
606	(
607	C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
608	C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
609	C_SPLB_P2P => C_SPLB_P2P,
610	C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
611	C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
612	C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
613	C_SPLB_AWIDTH => C_SPLB_AWIDTH,
614	C_SPLB_DWIDTH => C_SPLB_DWIDTH,
615	C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
616	C_FAMILY => C_FAMILY
617	)
618	port map
619	(
620	SPLB_Clk => SPLB_Clk,
621	SPLB_Rst => SPLB_Rst,
622	PLB_ABus => PLB_ABus,
623	PLB_UABus => PLB_UABus,
624	PLB_PAValid => PLB_PAValid,
625	PLB_SAValid => PLB_SAValid,
626	PLB_rdPrim => PLB_rdPrim,
627	PLB_wrPrim => PLB_wrPrim,
628	PLB_masterID => PLB_masterID,
629	PLB_abort => PLB_abort,
630	PLB_busLock => PLB_busLock,
631	PLB_RNW => PLB_RNW,
632	PLB_BE => PLB_BE,
633	PLB_MSize => PLB_MSize,
634	PLB_size => PLB_size,
635	PLB_type => PLB_type,
636	PLB_lockErr => PLB_lockErr,
637	PLB_wrDBus => PLB_wrDBus,
638	PLB_wrBurst => PLB_wrBurst,
639	PLB_rdBurst => PLB_rdBurst,
640	PLB_wrPendReq => PLB_wrPendReq,
641	PLB_rdPendReq => PLB_rdPendReq,
642	PLB_wrPendPri => PLB_wrPendPri,
643	PLB_rdPendPri => PLB_rdPendPri,
644	PLB_reqPri => PLB_reqPri,
645	PLB_TAttribute => PLB_TAttribute,
646	Sl_addrAck => Sl_addrAck,
647	Sl_SSize => Sl_SSize,
648	Sl_wait => Sl_wait,
649	Sl_rearbitrate => Sl_rearbitrate,
650	Sl_wrDAck => Sl_wrDAck,
651	Sl_wrComp => Sl_wrComp,
652	Sl_wrBTerm => Sl_wrBTerm,
653	Sl_rdDBus => Sl_rdDBus,
654	Sl_rdWdAddr => Sl_rdWdAddr,
655	Sl_rdDAck => Sl_rdDAck,
656	Sl_rdComp => Sl_rdComp,
657	Sl_rdBTerm => Sl_rdBTerm,
658	Sl_MBusy => Sl_MBusy,
659	Sl_MWrErr => Sl_MWrErr,
660	Sl_MRdErr => Sl_MRdErr,
661	Sl_MIRQ => Sl_MIRQ,
662	Bus2IP_Clk => ipif_Bus2IP_Clk,
663	Bus2IP_Reset => ipif_Bus2IP_Reset,
664	IP2Bus_Data => ipif_IP2Bus_Data,
665	IP2Bus_WrAck => ipif_IP2Bus_WrAck,
666	IP2Bus_RdAck => ipif_IP2Bus_RdAck,
667	IP2Bus_Error => ipif_IP2Bus_Error,
668	Bus2IP_Addr => ipif_Bus2IP_Addr,
669	Bus2IP_Data => ipif_Bus2IP_Data,
670	Bus2IP_RNW => ipif_Bus2IP_RNW,
671	Bus2IP_BE => ipif_Bus2IP_BE,
672	Bus2IP_CS => ipif_Bus2IP_CS,
673	Bus2IP_RdCE => ipif_Bus2IP_RdCE,
674	Bus2IP_WrCE => ipif_Bus2IP_WrCE
675	);
676
677	------------------------------------------
678	-- instantiate User Logic
679	------------------------------------------
680	USER_LOGIC_I : component user_logic
681	generic map
682	(
683	-- MAP USER GENERICS BELOW THIS LINE ---------------
684	--USER generics mapped here
685	-- MAP USER GENERICS ABOVE THIS LINE ---------------
686
687	C_SLV_DWIDTH => USER_SLV_DWIDTH,
688	C_NUM_REG => USER_NUM_REG
689	)
690	port map
691	(
692	-- MAP USER PORTS BELOW THIS LINE ------------------
693
694	controller_logic_clk => controller_logic_clk,
695	spi_clk => spi_clk,
696	data_out => data_out,
697	Radio1_cs => radio1_cs,
698	Radio2_cs => radio2_cs,
699	Radio3_cs => radio3_cs,
700	Radio4_cs => radio4_cs,
701	Dac1_cs => dac1_cs,
702	Dac2_cs => dac2_cs,
703	Dac3_cs => dac3_cs,
704	Dac4_cs => dac4_cs,
705	Radio1_interpfiltbypass => radio1_interpfiltbypass,
706	Radio1_decfiltbypass => radio1_decfiltbypass,
707	Radio1_SHDN => radio1_SHDN,
708	Radio1_TxEn => radio1_TxEn,
709	Radio1_RxEn => radio1_RxEn,
710	Radio1_RxHP => radio1_RxHP,
711	Radio1_LD => radio1_LD,
712	Radio1_24PA => radio1_24PA,
713	Radio1_5PA => radio1_5PA,
714	Radio1_ANTSW => radio1_ANTSW,
715	Radio1_LED => radio1_LED,
716	Radio1_ADC_RX_DCS => radio1_ADC_RX_DCS,
717	Radio1_ADC_RX_DFS => radio1_ADC_RX_DFS,
718	Radio1_ADC_RX_OTRA => radio1_ADC_RX_OTRA,
719	Radio1_ADC_RX_OTRB => radio1_ADC_RX_OTRB,
720	Radio1_ADC_RX_PWDNA => radio1_ADC_RX_PWDNA,
721	Radio1_ADC_RX_PWDNB => radio1_ADC_RX_PWDNB,
722	Radio1_DIPSW => radio1_DIPSW,
723	Radio1_RSSI_ADC_CLAMP => radio1_RSSI_ADC_CLAMP,
724	Radio1_RSSI_ADC_HIZ => radio1_RSSI_ADC_HIZ,
725	Radio1_RSSI_ADC_OTR => radio1_RSSI_ADC_OTR,
726	Radio1_RSSI_ADC_SLEEP => radio1_RSSI_ADC_SLEEP,
727	Radio1_RSSI_ADC_D => radio1_RSSI_ADC_D,
728	Radio1_TX_DAC_PLL_LOCK => radio1_TX_DAC_PLL_LOCK,
729	Radio1_TX_DAC_RESET => radio1_TX_DAC_RESET,
730	Radio1_SHDN_external => radio1_SHDN_external,
731	Radio1_TxEn_external => radio1_TxEn_external,
732	Radio1_RxEn_external => radio1_RxEn_external,
733	Radio1_RxHP_external => radio1_RxHP_external,
734	Radio1_TxGain => radio1_TxGain,
735	Radio1_TxStart => radio1_TxStart,
736	Radio2_interpfiltbypass => radio2_interpfiltbypass,
737	Radio2_decfiltbypass => radio2_decfiltbypass,
738	Radio2_SHDN => radio2_SHDN,
739	Radio2_TxEn => radio2_TxEn,
740	Radio2_RxEn => radio2_RxEn,
741	Radio2_RxHP => radio2_RxHP,
742	Radio2_LD => radio2_LD,
743	Radio2_24PA => radio2_24PA,
744	Radio2_5PA => radio2_5PA,
745	Radio2_ANTSW => radio2_ANTSW,
746	Radio2_LED => radio2_LED,
747	Radio2_ADC_RX_DCS => radio2_ADC_RX_DCS,
748	Radio2_ADC_RX_DFS => radio2_ADC_RX_DFS,
749	Radio2_ADC_RX_OTRA => radio2_ADC_RX_OTRA,
750	Radio2_ADC_RX_OTRB => radio2_ADC_RX_OTRB,
751	Radio2_ADC_RX_PWDNA => radio2_ADC_RX_PWDNA,
752	Radio2_ADC_RX_PWDNB => radio2_ADC_RX_PWDNB,
753	Radio2_DIPSW => radio2_DIPSW,
754	Radio2_RSSI_ADC_CLAMP => radio2_RSSI_ADC_CLAMP,
755	Radio2_RSSI_ADC_HIZ => radio2_RSSI_ADC_HIZ,
756	Radio2_RSSI_ADC_OTR => radio2_RSSI_ADC_OTR,
757	Radio2_RSSI_ADC_SLEEP => radio2_RSSI_ADC_SLEEP,
758	Radio2_RSSI_ADC_D => radio2_RSSI_ADC_D,
759	Radio2_TX_DAC_PLL_LOCK => radio2_TX_DAC_PLL_LOCK,
760	Radio2_TX_DAC_RESET => radio2_TX_DAC_RESET,
761	Radio2_SHDN_external => radio2_SHDN_external,
762	Radio2_TxEn_external => radio2_TxEn_external,
763	Radio2_RxEn_external => radio2_RxEn_external,
764	Radio2_RxHP_external => radio2_RxHP_external,
765	Radio2_TxGain => radio2_TxGain,
766	Radio2_TxStart => radio2_TxStart,
767	Radio3_interpfiltbypass => radio3_interpfiltbypass,
768	Radio3_decfiltbypass => radio3_decfiltbypass,
769	Radio3_SHDN => radio3_SHDN,
770	Radio3_TxEn => radio3_TxEn,
771	Radio3_RxEn => radio3_RxEn,
772	Radio3_RxHP => radio3_RxHP,
773	Radio3_LD => radio3_LD,
774	Radio3_24PA => radio3_24PA,
775	Radio3_5PA => radio3_5PA,
776	Radio3_ANTSW => radio3_ANTSW,
777	Radio3_LED => radio3_LED,
778	Radio3_ADC_RX_DCS => radio3_ADC_RX_DCS,
779	Radio3_ADC_RX_DFS => radio3_ADC_RX_DFS,
780	Radio3_ADC_RX_OTRA => radio3_ADC_RX_OTRA,
781	Radio3_ADC_RX_OTRB => radio3_ADC_RX_OTRB,
782	Radio3_ADC_RX_PWDNA => radio3_ADC_RX_PWDNA,
783	Radio3_ADC_RX_PWDNB => radio3_ADC_RX_PWDNB,
784	Radio3_DIPSW => radio3_DIPSW,
785	Radio3_RSSI_ADC_CLAMP => radio3_RSSI_ADC_CLAMP,
786	Radio3_RSSI_ADC_HIZ => radio3_RSSI_ADC_HIZ,
787	Radio3_RSSI_ADC_OTR => radio3_RSSI_ADC_OTR,
788	Radio3_RSSI_ADC_SLEEP => radio3_RSSI_ADC_SLEEP,
789	Radio3_RSSI_ADC_D => radio3_RSSI_ADC_D,
790	Radio3_TX_DAC_PLL_LOCK => radio3_TX_DAC_PLL_LOCK,
791	Radio3_TX_DAC_RESET => radio3_TX_DAC_RESET,
792	Radio3_SHDN_external => radio3_SHDN_external,
793	Radio3_TxEn_external => radio3_TxEn_external,
794	Radio3_RxEn_external => radio3_RxEn_external,
795	Radio3_RxHP_external => radio3_RxHP_external,
796	Radio3_TxGain => radio3_TxGain,
797	Radio3_TxStart => radio3_TxStart,
798	Radio4_interpfiltbypass => radio4_interpfiltbypass,
799	Radio4_decfiltbypass => radio4_decfiltbypass,
800	Radio4_SHDN => radio4_SHDN,
801	Radio4_TxEn => radio4_TxEn,
802	Radio4_RxEn => radio4_RxEn,
803	Radio4_RxHP => radio4_RxHP,
804	Radio4_LD => radio4_LD,
805	Radio4_24PA => radio4_24PA,
806	Radio4_5PA => radio4_5PA,
807	Radio4_ANTSW => radio4_ANTSW,
808	Radio4_LED => radio4_LED,
809	Radio4_ADC_RX_DCS => radio4_ADC_RX_DCS,
810	Radio4_ADC_RX_DFS => radio4_ADC_RX_DFS,
811	Radio4_ADC_RX_OTRA => radio4_ADC_RX_OTRA,
812	Radio4_ADC_RX_OTRB => radio4_ADC_RX_OTRB,
813	Radio4_ADC_RX_PWDNA => radio4_ADC_RX_PWDNA,
814	Radio4_ADC_RX_PWDNB => radio4_ADC_RX_PWDNB,
815	Radio4_DIPSW => radio4_DIPSW,
816	Radio4_RSSI_ADC_CLAMP => radio4_RSSI_ADC_CLAMP,
817	Radio4_RSSI_ADC_HIZ => radio4_RSSI_ADC_HIZ,
818	Radio4_RSSI_ADC_OTR => radio4_RSSI_ADC_OTR,
819	Radio4_RSSI_ADC_SLEEP => radio4_RSSI_ADC_SLEEP,
820	Radio4_RSSI_ADC_D => radio4_RSSI_ADC_D,
821	Radio4_TX_DAC_PLL_LOCK => radio4_TX_DAC_PLL_LOCK,
822	Radio4_TX_DAC_RESET => radio4_TX_DAC_RESET,
823	Radio4_SHDN_external => radio4_SHDN_external,
824	Radio4_TxEn_external => radio4_TxEn_external,
825	Radio4_RxEn_external => radio4_RxEn_external,
826	Radio4_RxHP_external => radio4_RxHP_external,
827	Radio4_TxGain => radio4_TxGain,
828	Radio4_TxStart => radio4_TxStart,
829	-- MAP USER PORTS ABOVE THIS LINE ------------------
830
831	Bus2IP_Clk => ipif_Bus2IP_Clk,
832	Bus2IP_Reset => ipif_Bus2IP_Reset,
833	Bus2IP_Data => ipif_Bus2IP_Data,
834	Bus2IP_BE => ipif_Bus2IP_BE,
835	Bus2IP_RdCE => user_Bus2IP_RdCE,
836	Bus2IP_WrCE => user_Bus2IP_WrCE,
837	IP2Bus_Data => user_IP2Bus_Data,
838	IP2Bus_RdAck => user_IP2Bus_RdAck,
839	IP2Bus_WrAck => user_IP2Bus_WrAck,
840	IP2Bus_Error => user_IP2Bus_Error
841	);
842
843	------------------------------------------
844	-- connect internal signals
845	------------------------------------------
846	ipif_IP2Bus_Data <= user_IP2Bus_Data;
847	ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
848	ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
849	ipif_IP2Bus_Error <= user_IP2Bus_Error;
850
851	user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
852	user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
853
854	end IMP;

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source: PlatformSupport/Deprecated/pcores/radio_controller_v1_21_a/hdl/vhdl/radio_controller.vhd

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