source: PlatformSupport/Deprecated/pcores/user_io_board_controller_opbw_v1_00_a/data/user_io_board_controller_opbw_v2_1_0.mpd

## Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.                      
                      
## You may copy and modify these files for your own internal use solely with                      
## Xilinx programmable logic devices and  Xilinx EDK system or create IP                      
## modules solely for Xilinx programmable logic devices and Xilinx EDK system.                      
## No rights are granted to distribute any files unless they are distributed in                      
## Xilinx programmable logic devices.                      
###################################################################                      
##                      
## Name     : user_io_board_controller_opbw                      
## Desc     : Microprocessor Peripheral Description                      
##          : Automatically generated by PsfUtility                      
##                      
###################################################################                      
                      
BEGIN user_io_board_controller_opbw                      
                      
## Peripheral Options                      
OPTION IPTYPE = PERIPHERAL                      
OPTION STYLE = MIX                      
OPTION IMP_NETLIST = TRUE                      
OPTION HDL = VHDL                      
                      
                      
## Bus Interfaces                      
BUS_INTERFACE BUS = SOPB, BUS_TYPE = SLAVE, BUS_STD = OPB                      
                      
## Generics for VHDL or Parameters for Verilog                      
PARAMETER C_BASEADDR = 0xFFFFFFFF, DT = std_logic_vector(0 to 31), BUS = SOPB, ADDRESS = BASE, PAIR = C_HIGHADDR, MIN_SIZE = 0x40000
PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector(0 to 31), BUS = SOPB, ADDRESS = HIGH, PAIR = C_BASEADDR
PARAMETER C_OPB_AWIDTH = 32, DT = INTEGER, BUS = SOPB                      
PARAMETER C_OPB_DWIDTH = 32, DT = INTEGER, BUS = SOPB                      
                      
## Ports                      
PORT ce = "net_vcc", DIR = I
PORT opb_abus = OPB_ABus, DIR = I, VEC = [0:31], BUS = SOPB                      
PORT opb_be = OPB_BE, DIR = I, VEC = [0:3], BUS = SOPB                      
PORT opb_clk = "", DIR = I, BUS = SOPB                      
PORT opb_dbus = OPB_DBus, DIR = I, VEC = [0:31], BUS = SOPB                      
PORT opb_rnw = OPB_RNW, DIR = I, BUS = SOPB                      
PORT opb_rst = OPB_Rst, DIR = I, BUS = SOPB                      
PORT opb_select = OPB_select, DIR = I, BUS = SOPB                      
PORT opb_seqaddr = OPB_seqAddr, DIR = I, BUS = SOPB                      
PORT reset = "", DIR = I                      
PORT cs = "", DIR = O                      
PORT resetlcd = "", DIR = O                      
PORT scl = "", DIR = O                      
PORT sdi = "", DIR = O                      
PORT sgp_dbus = Sl_DBus, DIR = O, VEC = [0:31], BUS = SOPB                      
PORT sgp_errack = Sl_errAck, DIR = O, BUS = SOPB                      
PORT sgp_retry = Sl_retry, DIR = O, BUS = SOPB                      
PORT sgp_toutsup = Sl_toutSup, DIR = O, BUS = SOPB                      
PORT sgp_xferack = Sl_xferAck, DIR = O, BUS = SOPB                      
                      
END