source: PlatformSupport/Deprecated/pcores/user_io_board_controller_opbw_v1_00_a/netlist/adder_subtracter_virtex2p_7_0_cb748602b0616a72.edn

Last change on this file was 653, checked in by sgupta, 17 years ago

Adding user io board controller

File size: 13.3 KB
Line 
1(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
2(status (written (timeStamp 2007 8 25 21 25 13)
3   (author "Xilinx, Inc.")
4   (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 8.2.03i"))))
5   (comment "                                                                               
6      This file is owned and controlled by Xilinx and must be used             
7      solely for design, simulation, implementation and creation of             
8      design files limited to Xilinx devices or technologies. Use               
9      with non-Xilinx devices or technologies is expressly prohibited           
10      and immediately terminates your license.                                 
11                                                                               
12      XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'             
13      SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                   
14      XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION           
15      AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION               
16      OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                 
17      IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                   
18      AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         
19      FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 
20      WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                   
21      IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           
22      REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF           
23      INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS           
24      FOR A PARTICULAR PURPOSE.                                                 
25                                                                               
26      Xilinx products are not intended for use in life support                 
27      appliances, devices, or systems. Use in such applications are             
28      expressly prohibited.                                                     
29                                                                               
30      (c) Copyright 1995-2006 Xilinx, Inc.                                     
31      All rights reserved.                                                     
32                                                                               
33   ")
34   (comment "Core parameters: ")
35       (comment "c_has_bypass_with_cin = false ")
36       (comment "c_a_type = 0 ")
37       (comment "c_has_sclr = false ")
38       (comment "c_sync_priority = 1 ")
39       (comment "c_has_aset = false ")
40       (comment "c_has_b_out = false ")
41       (comment "c_has_s = true ")
42       (comment "c_has_q = false ")
43       (comment "InstanceName = adder_subtracter_virtex2p_7_0_cb748602b0616a72 ")
44       (comment "c_family = virtex2p ")
45       (comment "c_bypass_enable = false ")
46       (comment "c_b_constant = false ")
47       (comment "c_has_ovfl = false ")
48       (comment "c_high_bit = 4 ")
49       (comment "c_latency = 0 ")
50       (comment "c_sinit_val = 0 ")
51       (comment "c_has_bypass = false ")
52       (comment "c_pipe_stages = 1 ")
53       (comment "c_has_sset = false ")
54       (comment "c_has_ainit = false ")
55       (comment "c_has_a_signed = false ")
56       (comment "c_has_q_c_out = false ")
57       (comment "c_b_type = 0 ")
58       (comment "c_has_add = false ")
59       (comment "c_has_sinit = false ")
60       (comment "c_has_b_in = false ")
61       (comment "c_has_b_signed = false ")
62       (comment "c_bypass_low = false ")
63       (comment "c_enable_rlocs = true ")
64       (comment "c_b_value = 0 ")
65       (comment "c_add_mode = 1 ")
66       (comment "c_has_aclr = false ")
67       (comment "c_out_width = 5 ")
68       (comment "c_ainit_val = 0000 ")
69       (comment "c_low_bit = 0 ")
70       (comment "c_has_q_ovfl = false ")
71       (comment "c_has_q_b_out = false ")
72       (comment "c_has_c_out = false ")
73       (comment "c_b_width = 5 ")
74       (comment "c_a_width = 5 ")
75       (comment "c_sync_enable = 0 ")
76       (comment "c_has_ce = true ")
77       (comment "c_has_c_in = false ")
78   (external xilinxun (edifLevel 0)
79      (technology (numberDefinition))
80       (cell VCC (cellType GENERIC)
81           (view view_1 (viewType NETLIST)
82               (interface
83                   (port P (direction OUTPUT))
84               )
85           )
86       )
87       (cell GND (cellType GENERIC)
88           (view view_1 (viewType NETLIST)
89               (interface
90                   (port G (direction OUTPUT))
91               )
92           )
93       )
94       (cell LUT4 (cellType GENERIC)
95           (view view_1 (viewType NETLIST)
96               (interface
97                   (port I0 (direction INPUT))
98                   (port I1 (direction INPUT))
99                   (port I2 (direction INPUT))
100                   (port I3 (direction INPUT))
101                   (port O (direction OUTPUT))
102               )
103           )
104       )
105       (cell MUXCY (cellType GENERIC)
106           (view view_1 (viewType NETLIST)
107               (interface
108                   (port DI (direction INPUT))
109                   (port CI (direction INPUT))
110                   (port S (direction INPUT))
111                   (port O (direction OUTPUT))
112               )
113           )
114       )
115       (cell XORCY (cellType GENERIC)
116           (view view_1 (viewType NETLIST)
117               (interface
118                   (port LI (direction INPUT))
119                   (port CI (direction INPUT))
120                   (port O (direction OUTPUT))
121               )
122           )
123       )
124   )
125(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
126(cell adder_subtracter_virtex2p_7_0_cb748602b0616a72
127 (cellType GENERIC) (view view_1 (viewType NETLIST)
128  (interface
129   (port ( rename A_0_ "A(0)") (direction INPUT))
130   (port ( rename A_1_ "A(1)") (direction INPUT))
131   (port ( rename A_2_ "A(2)") (direction INPUT))
132   (port ( rename A_3_ "A(3)") (direction INPUT))
133   (port ( rename A_4_ "A(4)") (direction INPUT))
134   (port ( rename B_0_ "B(0)") (direction INPUT))
135   (port ( rename B_1_ "B(1)") (direction INPUT))
136   (port ( rename B_2_ "B(2)") (direction INPUT))
137   (port ( rename B_3_ "B(3)") (direction INPUT))
138   (port ( rename B_4_ "B(4)") (direction INPUT))
139   (port ( rename S_0_ "S(0)") (direction OUTPUT))
140   (port ( rename S_1_ "S(1)") (direction OUTPUT))
141   (port ( rename S_2_ "S(2)") (direction OUTPUT))
142   (port ( rename S_3_ "S(3)") (direction OUTPUT))
143   (port ( rename S_4_ "S(4)") (direction OUTPUT))
144   )
145  (contents
146   (instance VCC (viewRef view_1 (cellRef VCC  (libraryRef xilinxun))))
147   (instance GND (viewRef view_1 (cellRef GND  (libraryRef xilinxun))))
148   (instance BU3
149      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
150      (property RLOC (string "x3y4"))
151      (property RPM_GRID (string "GRID"))
152      (property INIT (string "9999"))
153   )
154   (instance BU4
155      (viewRef view_1 (cellRef MUXCY (libraryRef xilinxun)))
156      (property RLOC (string "x3y4"))
157      (property RPM_GRID (string "GRID"))
158   )
159   (instance BU5
160      (viewRef view_1 (cellRef XORCY (libraryRef xilinxun)))
161      (property RLOC (string "x3y4"))
162      (property RPM_GRID (string "GRID"))
163   )
164   (instance BU7
165      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
166      (property RLOC (string "x3y4"))
167      (property RPM_GRID (string "GRID"))
168      (property INIT (string "9999"))
169   )
170   (instance BU8
171      (viewRef view_1 (cellRef MUXCY (libraryRef xilinxun)))
172      (property RLOC (string "x3y4"))
173      (property RPM_GRID (string "GRID"))
174   )
175   (instance BU9
176      (viewRef view_1 (cellRef XORCY (libraryRef xilinxun)))
177      (property RLOC (string "x3y4"))
178      (property RPM_GRID (string "GRID"))
179   )
180   (instance BU11
181      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
182      (property RLOC (string "x3y5"))
183      (property RPM_GRID (string "GRID"))
184      (property INIT (string "9999"))
185   )
186   (instance BU12
187      (viewRef view_1 (cellRef MUXCY (libraryRef xilinxun)))
188      (property RLOC (string "x3y5"))
189      (property RPM_GRID (string "GRID"))
190   )
191   (instance BU13
192      (viewRef view_1 (cellRef XORCY (libraryRef xilinxun)))
193      (property RLOC (string "x3y5"))
194      (property RPM_GRID (string "GRID"))
195   )
196   (instance BU15
197      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
198      (property RLOC (string "x3y5"))
199      (property RPM_GRID (string "GRID"))
200      (property INIT (string "9999"))
201   )
202   (instance BU16
203      (viewRef view_1 (cellRef MUXCY (libraryRef xilinxun)))
204      (property RLOC (string "x3y5"))
205      (property RPM_GRID (string "GRID"))
206   )
207   (instance BU17
208      (viewRef view_1 (cellRef XORCY (libraryRef xilinxun)))
209      (property RLOC (string "x3y5"))
210      (property RPM_GRID (string "GRID"))
211   )
212   (instance BU19
213      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
214      (property RLOC (string "x3y8"))
215      (property RPM_GRID (string "GRID"))
216      (property INIT (string "9999"))
217   )
218   (instance BU20
219      (viewRef view_1 (cellRef XORCY (libraryRef xilinxun)))
220      (property RLOC (string "x3y8"))
221      (property RPM_GRID (string "GRID"))
222   )
223   (net N0
224    (joined
225      (portRef G (instanceRef GND))
226      (portRef I2 (instanceRef BU3))
227      (portRef I3 (instanceRef BU3))
228      (portRef I2 (instanceRef BU7))
229      (portRef I3 (instanceRef BU7))
230      (portRef I2 (instanceRef BU11))
231      (portRef I3 (instanceRef BU11))
232      (portRef I2 (instanceRef BU15))
233      (portRef I3 (instanceRef BU15))
234      (portRef I2 (instanceRef BU19))
235      (portRef I3 (instanceRef BU19))
236    )
237   )
238   (net N1
239    (joined
240      (portRef P (instanceRef VCC))
241      (portRef CI (instanceRef BU4))
242      (portRef CI (instanceRef BU5))
243    )
244   )
245   (net N2
246    (joined
247      (portRef S (instanceRef BU4))
248      (portRef LI (instanceRef BU5))
249      (portRef O (instanceRef BU3))
250    )
251   )
252   (net N5
253    (joined
254      (portRef O (instanceRef BU4))
255      (portRef CI (instanceRef BU8))
256      (portRef CI (instanceRef BU9))
257    )
258   )
259   (net N7
260    (joined
261      (portRef S (instanceRef BU8))
262      (portRef LI (instanceRef BU9))
263      (portRef O (instanceRef BU7))
264    )
265   )
266   (net N10
267    (joined
268      (portRef O (instanceRef BU8))
269      (portRef CI (instanceRef BU12))
270      (portRef CI (instanceRef BU13))
271    )
272   )
273   (net N12
274    (joined
275      (portRef S (instanceRef BU12))
276      (portRef LI (instanceRef BU13))
277      (portRef O (instanceRef BU11))
278    )
279   )
280   (net N15
281    (joined
282      (portRef O (instanceRef BU12))
283      (portRef CI (instanceRef BU16))
284      (portRef CI (instanceRef BU17))
285    )
286   )
287   (net N17
288    (joined
289      (portRef S (instanceRef BU16))
290      (portRef LI (instanceRef BU17))
291      (portRef O (instanceRef BU15))
292    )
293   )
294   (net N20
295    (joined
296      (portRef O (instanceRef BU16))
297      (portRef CI (instanceRef BU20))
298    )
299   )
300   (net N22
301    (joined
302      (portRef LI (instanceRef BU20))
303      (portRef O (instanceRef BU19))
304    )
305   )
306   (net (rename N26 "A(0)")
307    (joined
308      (portRef A_0_)
309      (portRef DI (instanceRef BU4))
310      (portRef I0 (instanceRef BU3))
311    )
312   )
313   (net (rename N27 "A(1)")
314    (joined
315      (portRef A_1_)
316      (portRef DI (instanceRef BU8))
317      (portRef I0 (instanceRef BU7))
318    )
319   )
320   (net (rename N28 "A(2)")
321    (joined
322      (portRef A_2_)
323      (portRef DI (instanceRef BU12))
324      (portRef I0 (instanceRef BU11))
325    )
326   )
327   (net (rename N29 "A(3)")
328    (joined
329      (portRef A_3_)
330      (portRef DI (instanceRef BU16))
331      (portRef I0 (instanceRef BU15))
332    )
333   )
334   (net (rename N30 "A(4)")
335    (joined
336      (portRef A_4_)
337      (portRef I0 (instanceRef BU19))
338    )
339   )
340   (net (rename N31 "B(0)")
341    (joined
342      (portRef B_0_)
343      (portRef I1 (instanceRef BU3))
344    )
345   )
346   (net (rename N32 "B(1)")
347    (joined
348      (portRef B_1_)
349      (portRef I1 (instanceRef BU7))
350    )
351   )
352   (net (rename N33 "B(2)")
353    (joined
354      (portRef B_2_)
355      (portRef I1 (instanceRef BU11))
356    )
357   )
358   (net (rename N34 "B(3)")
359    (joined
360      (portRef B_3_)
361      (portRef I1 (instanceRef BU15))
362    )
363   )
364   (net (rename N35 "B(4)")
365    (joined
366      (portRef B_4_)
367      (portRef I1 (instanceRef BU19))
368    )
369   )
370   (net (rename N36 "S(0)")
371    (joined
372      (portRef S_0_)
373      (portRef O (instanceRef BU5))
374    )
375   )
376   (net (rename N37 "S(1)")
377    (joined
378      (portRef S_1_)
379      (portRef O (instanceRef BU9))
380    )
381   )
382   (net (rename N38 "S(2)")
383    (joined
384      (portRef S_2_)
385      (portRef O (instanceRef BU13))
386    )
387   )
388   (net (rename N39 "S(3)")
389    (joined
390      (portRef S_3_)
391      (portRef O (instanceRef BU17))
392    )
393   )
394   (net (rename N40 "S(4)")
395    (joined
396      (portRef S_4_)
397      (portRef O (instanceRef BU20))
398    )
399   )
400))))
401(design adder_subtracter_virtex2p_7_0_cb748602b0616a72 (cellRef adder_subtracter_virtex2p_7_0_cb748602b0616a72 (libraryRef test_lib))
402  (property X_CORE_INFO (string "C_ADDSUB_V7_0, Coregen 8.2.03i"))
403  (property PART (string "xc2vp2-fg256-7") (owner "Xilinx")))
404)
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